HDTV Continuously Variable Anti-Aliasing Filters MAX7469/MAX7470

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HDTV Continuously Variable Anti-Aliasing Filters MAX7469/MAX7470

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19-0548; 5/06
HDTV Continuously Variable Anti-Aliasing Filters
MAX7469/MAX7470 triple-channel, anti-aliasing filters buffers ideal high-definition (HD) standard-definition (SD) television (TV) applications. Compatible with 1080i, 720p, 720i, 480p, 480i scanning system standards computer format signals, MAX7469/MAX7470 support component video GsBR, RGBHV), well composite (CVBS) S-video (Y/C). MAX7469/MAX7470 limit input bandwidth anti-aliasing out-of-band noise reduction prior digital conversion video decoder. MAX7469/MAX7470 frequency response continuously varied linear steps through I2C* interface from below resolution beyond resolution. output buffers MAX7469/MAX7470 drive 2VP-P video signal into standard load. inputs AC-coupled, outputs either AC-coupled. MAX7469 gain 0dB, MAX7470 gain +6dB. Both devices available 20-pin TQFN package fully specified over +85°C upper-commercial temperature range.
Features
Continuously Variable Anti-Aliasing Filter 5MHz 34MHz Steps Supports Standard Video Computer Input Formats 480i, 480p, 720i, 720p, 1080i QVGA, VGA, SVGA, XGA, SXGA, UXGA GsBR, RGBHV, Y/C, CVBS Accepts Input Sync Format Sync Sync External Sync (Positive Negative) Sync Channels Buffered Outputs Drive Standard Video Load (MAX7469) +6dB (MAX7470) AC-Coupled Outputs Single Analog +3.3V Digital Supplies Power-Down Mode 20-Pin TQFN Lead-Free Package
MAX7469/MAX7470
Applications
HDTV (LCD, PDP, DLP, CRT) Set-Top Boxes Personal Video Recorders Home Theaters
Configuration
AVDD
VIEW
*Purchase components from Maxim Integrated Products, Inc., sublicensed Associate Companies, conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips.
Ordering Information
OUT1
PART
AVDD OUT2 AVDD OUT3
PIN-PACKAGE TQFN-EP* TQFN-EP*
BUFFER GAIN (dB)
CODE T2055-4 T2055-4
MAX7469UTP+ MAX7470UTP+**
MAX7469 MAX7470
DGND EXTSYNC
DVDD
Note: devices specified over +85°C operating temperature range. Indicates lead-free packaging. Exposed pad. **Future product-contact factory availability.
TQFN (5mm 5mm)
*EXPOSED PAD. DESCRIPTION CONNECTION.
Typical Operating Circuit appears data sheet.
Maxim Integrated Products
pricing delivery, ordering information please contact Maxim/Dallas Direct! 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
HDTV Continuously Variable Anti-Aliasing Filters MAX7469/MAX7470
ABSOLUTE MAXIMUM RATINGS
AVDD GND.-0.3V DVDD DGND.-0.3V IN_, EXTSYNC .-0.3V lower (AVDD OUT_ .-0.3V lower (AVDD .-0.3V lower (AVDD SCL, DGND .-0.3V Continuous Power Dissipation +70°C) 20-Pin TQFN (derate 33.3mW/°C above +70°C) .2666.7mW Maximum Current into IN_, GND, SCL, SDA, EXTSYNC.±50mA Operating Temperature Range.0°C +85°C Storage Temperature Range .-65°C +150°C Junction Temperature .+150°C Lead Temperature (soldering, 10s) .+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD ±5%, DVDD 2.7V 3.6V, RLOAD GND, 0.1µF, +85°C, unless otherwise noted. Typical values AVDD DVDD 3.3V, +25°C.)
PARAMETER SYMBOL CONDITIONS 100kHz 30MHz, relative 100kHz (Note Filter Passband Response 100kHz 5.75MHz, relative 100kHz (Note 74MHz (Note 27MHz (Note 100kHz 30MHz, relative 100kHz (Note 100kHz 5.75MHz, relative 100kHz (Note channel channel, 100kHz 2MHz, (Note Group Delay Matching tG(MATCH) channel channel, 100kHz 500kHz, (Note -3dB, bypass mode, independent filter setting HDIST VDIST Five-step modulated staircase (Note Five-step modulated staircase (Note Output signal (2VP-P) noise (100kHz 30MHz), 30MHz Deviations line with 18µs, bar; line 63.5µs (Note Deviations lines with 18µs, bars (Note -0.6 ±0.1 0.25 0.25 Degrees ±1.0 UNITS
Filter Stopband Attenuation
Group Delay Deviation
Bypass Frequency Response Differential Gain Differential Phase Signal-to-Noise Ratio Line-Time Distortion Field-Time Distortion
HDTV Continuously Variable Anti-Aliasing Filters MAX7469/MAX7470
ELECTRICAL CHARACTERISTICS (continued)
(AVDD ±5%, DVDD 2.7V 3.6V, RLOAD GND, 0.1µF, +85°C, unless otherwise noted. Typical values AVDD DVDD 3.3V, +25°C.)
PARAMETER Clamp Settling Time Minimum Functional Input Sync Amplitude Low-Frequency Gain (Note Low-Frequency Gain Matching Maximum Output Voltage Amplitude Maximum Input Voltage Amplitude Channel-to-Channel Isolation Output Clamping Level Variation Power-Supply Rejection Ratio DIGITAL INPUTS (EXTSYNC, Input Logic-High Voltage Input Logic-Low Voltage Input Leakage Current Input Capacitance DIGITAL INPUTS (SDA, SCL) Input Logic-High Voltage Input Logic-Low Voltage Input Hysteresis Input Leakage Current Input Capacitance DIGITAL OUTPUT (SDA) Output Logic-Low Voltage Tri-State Leakage Current Tri-State Output Capacitance POWER REQUIREMENTS Analog Supply Voltage Range Digital Supply Voltage Range Analog Supply Current Digital Supply Current AVDD DVDD IAVDD IDVDD Normal operation, load Power-down mode, load fSCL 400kHz 4.75 5.25 COUT ISINK DVDD ±0.1 VHYST DVDD 0.05 DVDD ±0.1 DVDD DVDD DVDD PSRR (Notes MAX7469 MAX7470 100kHz 30MHz MAX7469 MAX7470 SYMBOL CONDITIONS with step (Note Positive Negative -0.5 0.05 ±100 +0.5 UNITS VP-P VP-P
HDTV Continuously Variable Anti-Aliasing Filters MAX7469/MAX7470
TIMING CHARACTERISTICS
(AVDD ±5%, DVDD 2.7V 3.6V, RLOAD GND, 0.1µF, +85°C, unless otherwise noted. Typical values AVDD DVDD 3.3V, +25°C.)
PARAMETER Serial-Clock Frequency Free Time Between STOP START Condition Hold Time (Repeated) START (Sr) Condition Pulse-Width Pulse-Width High Setup Time Repeated START (Sr) Condition Data Hold Time Data Setup Time Rise Time Both Signals, Receiving Fall Time Both Signals, Receiving Fall Time Signal, Transmitting Setup Time STOP Condition Capacitive Load Each Line Pulse Width Spikes that Suppressed Input Filter SYMBOL fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO (Note (Note (Note After this period, first clock pulse generated CONDITIONS 0.1Cb UNITS
Note filter passband edge code 255. Note filter passband edge code Note total line period, depending video standard. NTSC, this 63.5µs; HDTV, line period 29.64µs. Note clamp level sync signals with sync pulses, blanking level otherwise. Note master device must provide hold time least 300ns signal (referred signal) bridge undefined region SCL's falling edge. Note total capacitance line measured between 0.3VDD 0.7VDD. Note Input filters inputs suppress noise spikes less than 50ns.
HDTV Continuously Variable Anti-Aliasing Filters MAX7469/MAX7470
tLOW
tSU;DAT
tHD;STA
tHD;STA tHD;DAT tHIGH
tSU;STA
tSU;STO
Figure 2-Wire, Serial-Interface Timing Diagram
Typical Operating Characteristics
(AVDD +5V, DVDD 3.3V, RLOAD GND, CLOAD 20pF GND, 0.1µF, +25°C, unless otherwise noted.)
FREQUENCY RESPONSE (MAX7469)
RESPONSE (dB) 1000 FREQUENCY (MHz) CODE CODE CODE CODE RESPONSE (dB)
MAX7469 toc01
PASSBAND FLATNESS (MAX7469)
MAX7469 toc02
FREQUENCY RESPONSE (MAX7470)
RESPONSE (dB) CODE 1000 CODE CODE CODE
MAX7469 toc03
-0.5 -1.0 CODE -1.5 -2.0 -2.5 -3.0 CODE CODE CODE
FREQUENCY (MHz)
FREQUENCY (MHz)
PASSBAND FLATNESS (MAX7470)
MAX7469 toc04
GROUP DELAY
DELAY (ns)
MAX7469 toc05
RESPONSE 7.14mV)
MAX7469 toc06
RESPONSE (dB) CODE CODE CODE CODE
300mV/div
300mV/div
200ns/div
FREQUENCY (MHz)
FREQUENCY (MHz)
HDTV Continuously Variable Anti-Aliasing Filters MAX7469/MAX7470
Typical Operating Characteristics (continued)
(AVDD +5V, DVDD 3.3V, RLOAD GND, CLOAD 20pF GND, 0.1µF, +25°C, unless otherwise noted.)
MODULATED 12.5T RESPONSE 7.14mV)
DIFFERENTIAL GAIN
MAX7469 toc07
DIFFERENTIAL GAIN
MEASURED -3dB FREQUENCY (MHz) -0.1 -0.2 -0.1 -0.2
MAX7469 toc08
-3dB FREQUENCY CONTROL CODE
MAX7469 toc09
300mV/div
300mV/div
DIFFERENTIAL PHASE (deg)
DIFFERENTIAL PHASE
400ns/div
CODE
BYPASS-MODE FREQUENCY RESPONSE
MAX7469 toc10
BYPASS-MODE GROUP DELAY
MAX7469 toc11
RESPONSE (dB) MAX7470 MAX7469
DELAY (ns)
1000 FREQUENCY (MHz) FREQUENCY (MHz)
HDTV Continuously Variable Anti-Aliasing Filters
Description
NAME DGND EXTSYNC DVDD OUT3 AVDD OUT2 OUT1 FUNCTION Digital Ground. Power-Supply Bypassing Layout Considerations section. External Sync Input. EXTSYNC internal resistor ground. Connect ground used. I2C-Compatible Serial-Clock Input I2C-Compatible Serial-Data Input/Output Digital Power Supply. Bypass DGND with 0.1µF capacitor. Power-Supply Bypassing Layout Considerations section. Video Output OUT3 either AC-coupled. Analog Power Supply. Bypass with 0.1µF capacitor. Power-Supply Bypassing Layout Considerations section. Video Output OUT2 either AC-coupled. Video Output OUT1 either AC-coupled. Device Address Device Address Ground. Connect pins ground plane. Power-Supply Bypassing Layout Considerations section. Video Input AC-couple with series 0.1µF capacitor. Video Input AC-couple with series 0.1µF capacitor. Video Input AC-couple with series 0.1µF capacitor. Exposed Pad. Internally connected GND. route board traces under package. Connect ground plane. Power-Supply Bypassing Layout Considerations section.
MAX7469/MAX7470
Detailed Description
MAX7469/MAX7470 complete video anti-aliasing solutions, ideal fixed-pixel HDTV display technologies, such plasma LCD, which digitize input video signal then scale resolution match native pixel format display. With software-selectable corner frequency ranging from 5MHz 34MHz, MAX7469/MAX7470 support both video signals, including 1080i, 720p, 720i, 480p, 480i. Higher bandwidth computer resolution signals also supported. Integrated lowpass filters limit analog video input bandwidth anti-aliasing out-of-band noise reduction prior sampling video decoder. allowing corner frequency adjusted from below resolution beyond resolutions linear steps, filter's corner frequency optimized dynamically specific input video signal sampling frequency video decoder. applications requiring passband greater than maximum frequency setting, filter bypass mode also provided.
interface allows microcontroller (µC) configure MAX7469/MAX7470s' performance functionality, including clamp voltage, filter corner frequency, sync source (internal/external), filter bypassing, etc. Typical Operating Circuit shows MAX7469/ MAX7470 block diagram typical external connections.
Sync Detector Clamp Settings
MAX7469/MAX7470 video clamp circuit establish offset incoming video signal after AC-coupling capacitor. This video clamp sets bias level circuit optimum operating point. MAX7469/MAX7470 support both internal external sync detection. Selection internal external detection achieved programming command byte (see Table After extracting sync information from channel external sync: SYNCA, SYNCB, SYNC), MAX7469/MAX7470 clamp video signal during sync portion video. Select possible clamp levels according input signal format. level when input signal contains sync information, such (luma) CVBS signal.
HDTV Continuously Variable Anti-Aliasing Filters MAX7469/MAX7470
Table Clamp Levels
INPUT SIGNAL FORMAT GSBR CVBS (sync signals) RGBHV CLAMP LEVEL CHANNEL CHANNEL CHANNEL High High High High High High High High
data word that corresponds desired frequency. Frequency Register section more details. frequency MAX7469/MAX7470 -3dB point. frequency according desired flat passband response.
high level bipolar signals, such (chroma) Pb/Pr. Table more details.
Component/Composite Selection MAX7469/MAX7470 accept component composite inputs. When configured composite video inputs, color-burst filter enabled; configured component video inputs, color-burst filter disabled. This filter separate from main filter direct signal path that effect overall frequency response. With normal video signals levels, this color-burst filter negligible effect sync detection. more significant effect under conditions low-signal amplitude coupled with higher relative amplitude color burst. External Sync Detection (EXTSYNC) When filtering video signal without embedded sync information, such computer formats (RGBHV) with separate sync signals, external sync mode (see Table apply horizontal sync source EXTSYNC pin. sync detector determines when clamp circuit turned MAX7469/MAX7470 able detect positive negative polarity external syncs with logic levels. interface program polarity external sync signal.
Optimizing Frequency Response Select frequency response according resolution video-signal format. High-definition signals require higher bandwidth, while standard-definition signals require less bandwidth. actual bandwidth contained video signal function visual resolution signal. This bandwidth typically less than what indicated format resolution (1080i, 720p, etc.). more information, Maxim Application Note 750: Bandwidth Versus Video Resolution, which available www.maxim-ic.com. frequency response optimized improve overall performance. important, minimum, meet Nyquist criterion. Beyond this, frequency response further optimized. oversampled systems, sample rate significantly more than desired passband response. extra frequency span between passband sample rate contains noise other undesirable interferers that eliminated setting corner frequency filter just pass desired bandwidth. This results higher signal-to-noise ratio overall system. Filter Bypass MAX7469/MAX7470 offer selectable filter bypassing that allows input video signals bypass internal filters reach output buffers unfiltered. Write appropriate command byte enable (0Eh) disable (0Fh) filter-bypass mode shown Table
Output Buffer
Each output buffer drive 2VP-P signal into video load. MAX7469/MAX7470 drive AC-coupled load. Output AC-coupling capacitors eliminated when driving cable, thereby eliminating normal adverse effects caused these large capacitors, such line, field-time distortion, also known droop. output level controlled limit voltage cable that blanking level video signal always less than meeting digital specification. Output Considerations section more information.
Filter
internal video filter delivers optimized response with steep transition band achieve wide passband along with excellent stopband rejection. addition, filter optimized provide excellent time domain response with overshoot.
Setting Filter Frequency interface vary frequency response (-3dB cutoff frequency) filter MAX7469/ MAX7470 from less than passband beyond passband linear steps. Write command byte access frequency register, followed 8-bit
Gain Options MAX7469 features overall gain 0dB, while MAX7470 features overall gain +6dB. MAX7470 when driving back-matched cable
HDTV Continuously Variable Anti-Aliasing Filters
MAX7469 when driving video decoder with input range same input MAX7469. added flexibility, MAX7469 accepts input signals with twice standard video-signal range, which used driving video decoder with input signal range that accepts larger signal swing. MAX7470 also used drive video decoder when gain desired.
Power-On Reset (POR)
MAX7469/MAX7470 include circuit that resets internal registers interface their default conditions (see Tables
MAX7469/MAX7470
Serial Interface
MAX7469/MAX7470 feature I2C-compatible, 2-wire serial interface consisting bidirectional serial-data line (SDA) serial-clock line (SCL). facilitate bidirectional communication between MAX7469/ MAX7470 master rates 400kHz. MAX7469/MAX7470 have command interpreter that accessed writing valid command byte. Once command byte written MAX7469/ MAX7470, command interpreter updates control/status register accordingly. Control/Status Register section more information. command interpreter also controls access frequency register through command byte (see Command Byte (Write Cycle) section). MAX7469/MAX7470 transmit/receive slave-only devices, relying upon master generate clock signal. master (typically initiates data transfer generates SCL. master device communicates MAX7469/ MAX7470 transmitting proper address (see Slave Address section) followed command and/or data words. Each transmit sequence framed with START REPEATED START (Sr) condition STOP condition. driver open-drain output, requiring pullup resistor (2.4k greater) generate logichigh voltage. Optional resistors (24) series with protect device inputs from high-voltage spikes lines. Series resistors also minimize crosstalk undershoot signals.
Output Clamp Level MAX7469/MAX7470 output ACcoupled. nominal output clamp level DC-coupled case depends clamp voltage setting determined according Table
Table Output Clamp Level
CLAMP SETTING High OUTPUT CLAMP LEVEL (typ) (typ)
shown Sync Detector Clamp Settings section, clamp level used signals with sync information determines voltage level sync tip, while high clamp level used signals without sync information sets blanking level. absolute voltage level output signal relative output clamp level. video signal containing sync information (i.e., CVBS unipolar above clamp level conversely, video signal without sync (i.e., bipolar around clamp level.
Power-Down Mode
MAX7469/MAX7470 include power-down mode that reduces supply current from 180mA (typ) (typ) powering down analog circuitry. interface remains active, allowing device return full-power operation. clamp settling time (see Electrical Characteristics section) limits wake-up time MAX7469/MAX7470. After exiting power-down mode, MAX7469/MAX7470 resume normal operation using settings stored prior power-down. power-down wake-up modes controlled through command byte (see Table software reset sets control/status register default conditions, frequency register affected.
Transfer Each rising edge transfers data bit. Nine clock cycles required transfer data into MAX7469/MAX7470. data must remain stable during high period clock pulse. Changes while high read control signals (see START STOP Conditions section). When serial interface inactive, idle high.
HDTV Continuously Variable Anti-Aliasing Filters MAX7469/MAX7470
START STOP Conditions master device initiates communication issuing START condition, high-to-low transition with high (Figure master terminates transmission STOP condition (see Acknowledge (ACK) NotAcknowledge (NACK) section). STOP condition low-to-high transition while high (Figure STOP condition frees bus. repeated START condition generated instead STOP condition, remains active. When STOP condition incorrect address detected, MAX7469/ MAX7470 then ignore communication until next START REPEATED START condition, minimizing digital noise feedthrough. Early STOP Conditions MAX7469/MAX7470 recognize STOP condition point during transmission except when STOP
condition occurs same high pulse START condition (Figure This condition legal format; least clock pulse must separate START STOP conditions. MAX7469/MAX7470 discard data received during data transfer aborted early STOP condition.
Repeated START (Sr) Conditions condition used indicate change direction data flow (see Read Cycle section). also used when master writing several devices does want relinquish control bus. MAX7469/MAX7470 serial interface supports continuous write operations with without) condition separating them.
Figure START/STOP Conditions
LEGAL STOP CONDITION ILLEGAL STOP CONDITION
STOP
START
START
ILLEGAL STOP
Figure Early STOP Conditions
HDTV Continuously Variable Anti-Aliasing Filters
Acknowledge (ACK) Not-Acknowledge (NACK) Successful data transfers acknowledged with acknowledge (ACK) not-acknowledge (NACK). Both master MAX7469/MAX7470 (slave) generate acknowledge bits. generate acknowledge, receiving device must pull before rising edge acknowledge-related clock pulse (ninth pulse) keep during high period clock pulse (Figure generate NACK, receiver allows pulled high before rising edge acknowledge-related clock pulse (ninth pulse) leaves high during high period clock pulse. Monitoring acknowledge bits allows detection unsuccessful data transfers. unsuccessful data transfer happens receiving device busy system fault occurred. event unsuccessful data transfer, master should reattempt communication later time. MAX7469/MAX7470 generate acknowledge when receiving address data pulling during ninth clock pulse. When transmitting data during read, MAX7469/MAX7470 drive during ninth clock pulse (i.e., external pullups define logic-high) that receiver data pull acknowledge receipt data.
Slave Address master initiates communication with slave device issuing START condition, followed 7-bit slave address (Figure When idle, MAX7469/MAX7470 wait START condition, followed their slave address. serial interface compares each address bit, allowing interface power down disconnect from immediately incorrect address detected. After recognizing START condition followed correct address, MAX7469/MAX7470 ready accept send data. least significant (LSB) address byte (R/W) determines whether master writing reading from MAX7469/MAX7470 (R/W selects write condition, selects read condition). After receiving proper address, MAX7469/MAX7470 (slave) issue pulling clock cycle. MAX7469/MAX7470 slave address consists fixed bits, A6-A2 (set 10010), followed pin-programmable bits, most significant address (A6) transmitted first, followed remaining bits. Addresses also driven dynamically required, values must stable when they expected address sequence.
MAX7469/MAX7470
ACKNOWLEDGE
ACKNOWLEDGE
Figure Acknowledge Not-Acknowledge Bits
Figure Slave-Address Byte Definition
HDTV Continuously Variable Anti-Aliasing Filters MAX7469/MAX7470
Command Byte (Write Cycle) write cycle begins with master issuing START condition followed address bits (Figure write (R/W After successfully receiving address, MAX7469/MAX7470 (slave) issue ACK. slave recognizes next byte after successfully received address command byte (Table
command byte configure MAX7469/ MAX7470. While most commands listed Table modify functionality MAX7469/MAX7470, some commands prepare device further data transfers (see Control/Status Register Frequency Register sections). write cycle prematurely aborted, register updated,
Table Command Byte Definition
COMMAND BYTE: INDIVIDUAL DEFINITIONS Enters power-down mode. Wake-up; resumes normal operation using frequency/status previously stored (unless power been cycled). Sets clamp voltage level low. Sets clamp voltage level high. Sets clamp voltage level low. Sets clamp voltage level high. Sets clamp voltage level low. Sets clamp voltage level high. Selects component input, color-burst filter disabled. Selects composite input, color-burst filter enabled. Selects internal sync. Selects external sync. Selects positive polarity external sync. Selects negative polarity external sync. Enables filters. Disables filters, enters bypass mode. Resets control/status register default values described Control/ Status Register section. This command does affect frequency register. Requests control/status register read. interface expects condition follow with address read/write read data driven onto bus. Loads frequency register with data byte following command byte. Requests frequency register read. interface expects condition follow with address read/write read data driven onto bus. DESCRIPTION
HDTV Continuously Variable Anti-Aliasing Filters
write sequence must repeated. Figures show examples write sequences.
Read Cycle read mode (R/W MAX7469/MAX7470 write contents control/status frequency registers bus. When command byte indicates read operation either control/status frequency register, serial interface expects condition
follow command byte. After sending master sends MAX7469/MAX7470 slave address byte followed (set indicate read). slave device (MAX7469/MAX7470) generates second address word immediately after clock pulse, direction data flow reverses. slave (MAX7469/MAX7470) then transmits byte data containing value register that
MAX7469/MAX7470
DIRECTION
MAX7469/MAX7470
START
(CONT) (CONT) DIRECTION COMMAND BYTE C7-C0 0010010. STOP
Figure Write Sequence Update Frequency Register
DIRECTION
MAX7469/MAX7470
START
COMMAND BYTE POWER-DOWN.
STOP
Figure Write Sequence Command Byte
HDTV Continuously Variable Anti-Aliasing Filters MAX7469/MAX7470
DIRECTION
MAX7469/MAX7470
START (CONT) (CONT) DIRECTION
STOP
Figure Basic Read Sequence
selected command byte. Figure shows basic read sequence. Note: master write command byte, requesting read control/status frequency register, slave (MAX7469/MAX7470) before master read contents selected register.
Table Control/Status Register Description
DESCRIPTION component input signal selected (default). composite input signal selected. internal sync enabled (default). external sync enabled. external sync: positive polarity (default). external sync: negative polarity. normal operation mode (default). power-down mode. filters enabled (default). bypass mode-no filtering. clamp voltage (default). clamp voltage high. clamp voltage low. clamp voltage high (default). clamp voltage low. clamp voltage high (default).
Control/Status Register MAX7469/MAX7470 store their status 8-bit register that read back master. individual bits control/status register summarized Tables power-on default value this register 03h. Frequency Register frequency response (-3dB passband edge) MAX7469/MAX7470 continuously varied linear steps changing codes frequency register (Table Command Byte (Write Cycle) section write sequence update frequency register.
Table Control/Status Register
CONTROL/STATUS REGISTER
Table Frequency Register Setting Different Video-Signal Formats
VIDEO-SIGNAL FORMAT Standard Definition (Interlaced) Standard Definition (Progressive) High-Definition Bandwidth High-Definition High Bandwidth CODE APPROXIMATE FREQUENCY (-3dB) (default)
HDTV Continuously Variable Anti-Aliasing Filters
Compatibility MAX7469/MAX7470 compatible with existing systems supporting standard 8-bit communications. general call address ignored, CBUS formats supported. device's address compatible with 7-bit addressing protocol only; 10bit address formats supported.
Power-Supply Bypassing Layout Considerations
MAX7469/MAX7470 operate from single analog supply +3.3V digital supply. Bypass AVDD with 0.1µF capacitor additional capacitor parallel additional low-frequency decoupling. Determine proper power-supply bypassing necessary taking into account desired disturbance level tolerable output, power-supply rejection MAX7469/MAX7470, amplitude frequency disturbance signals present vicinity MAX7469/MAX7470. extensive ground plane ensure optimum performance. three AVDD pins (pins that supply individual channels connected together bypassed one, provided components close pins. Bypass DGND with 0.1µF capacitor. ground pins (GND) must connected impedance ground plane close possible device. Place input termination resistors close possible device. Alternatively, terminations placed further from device board traces designed controlled impedance Minimize parasitic capacitance much possible avoid performance degradation upper frequency range possible with MAX7469/MAX7470. Refer MAX7469/MAX7470 evaluation proven board layout.
MAX7469/MAX7470
Applications Information
Input Considerations
0.1µF ceramic capacitors AC-couple inputs. inputs cannot DC-coupled. internal clamp circuit stores voltage across input capacitors obtain appropriate output voltage level. Increasing value these capacitors improve linetime distortion necessary extremely input leakage current yielding very line-time distortion performance. MAX7469/MAX7470 provide high input impedance allow nonzero source impedance used, such when input connected directly backmatched video cable, ensuring external resistance determines termination impedance.
Output Considerations
MAX7469/MAX7470 outputs ACcoupled. MAX7470, with +6dB gain, typically connected series back-match resistor followed video cable. Because inherent divide-by-two this configuration, blanking level video signal always less than which complies with digital requirements. MAX7469, with gain, typically connected video decoder. This connection. connection used, ensure that input requirements video decoder compatible. connection used, choose AC-coupling capacitor value that ensures that lowest frequency content video signal passed line-time distortion kept within desired limits. selection this value function input impedance and, more importantly, input leakage circuit being driven. video clamp reestablish level, already included subsequent circuit. outputs MAX7469/MAX7470 fully protected against short-circuit condition either ground positive supply device.
Exposed Heat Dissipation
MAX7469/MAX7470 TQFN package exposed bottom. This electrically connected, internal device, GND. route board traces under package. MAX7469/MAX7470 typically dissipate 900mW power, therefore, careful attention heat dispersion. least two-layer board with good ground plane recommended. maximize heat dispersion, place copper directly under MAX7469/ MAX7470 package that matches outline plastic encapsulated area. same thing bottom ground plane layer then place many vias possible connecting bottom layers thermally connect ground plane. Maxim evaluated four-layer board using FR-4 material copper with equal areas metal bottom side coincident with plastic encapsulated area 20-pin TQFN package. middle layers used power ground
HDTV Continuously Variable Anti-Aliasing Filters MAX7469/MAX7470
planes. board 15-mil, plated-through holes between top, bottom, ground plane layers. Thermocouple measurements confirm device temperatures safely within maximum limits.
Chip Information
PROCESS: BiCMOS
Typical Operating Circuit
SYNC AVDD
SYNC DETECTOR
MAX7469 MAX7470
(+6dB) OUT1
DECODER
0.1F
CLAMP/ BIAS
5MHz 34MHz PROGRAMMABLE PASSBAND LOWPASS FILTER
0.1F
Pb/B 0.1F
(+6dB) CLAMP/ BIAS 5MHz 34MHz PROGRAMMABLE PASSBAND LOWPASS FILTER
OUT2 0.1F
Pr/R 0.1F
(+6dB) CLAMP/ BIAS 5MHz 34MHz PROGRAMMABLE PASSBAND LOWPASS FILTER FREQUENCY SELECT INTERFACE SYNC ENABLE
OUT3 0.1F
BYPASS CLAMP LEVEL
MAX7470
DGND DVDD
HDTV Continuously Variable Anti-Aliasing Filters
Package Information
(The package drawing(s) this data sheet reflect most current specifications. latest package outline information www.maxim-ic.com/packages.)
THIN.EPS
MAX7469/MAX7470
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600
2006 Maxim Integrated Products Printed registered trademark Maxim Integrated Products, Inc.
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HDTV Continuously Variable Anti-Aliasing Filters MAX7469/MAX7470

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