8-Mbit Uniform Block) supply, Firmware Flash memory Feature summa
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M50FW080
8-Mbit Uniform Block) supply, Firmware Flash memory
Feature summary
Supply voltage Program, Erase Read operations fast program fast erase (optional) interfaces Firmware (FWH) Interface embedded operation with Chipsets Address/Address Multiplexed (A/A Mux) Interface programming equipment compatibility Firmware (FWH) hardware interface mode signal communication interface supporting Read Write operations Hardware Write Protect pins block protection Register-based Read Write Protection additional general-purpose inputs platform design flexibility Synchronized with clock Programming time typical Quadruple Byte Programming option uniform Kbyte memory blocks Program/Erase Controller Embedded Byte Program Block/Chip Erase algorithms Status Register bits Program Erase Suspend Read other Blocks during Program/Erase Suspend Program other Blocks during Erase Suspend BIOS applications
PLCC32
TSOP32 (NB) 14mm
TSOP40 20mm
Electronic signature Manufacturer code: Device Code: Packages ECOPACK® (RoHS compliant)
October 2006
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www.st.com
Contents
M50FW080
Contents
Summary description Signal descriptions
Firmware (FWH) signal descriptions
2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6 2.1.7 2.1.8 2.1.9 2.1.10 2.1.11 Input/Output communications (FWH0-FWH3) Input communication frame (FWH4) Identification inputs (ID0-ID3) General-purpose inputs (FGPI0-FGPI4) Interface configuration (IC) Interface Reset (RP) Reset (INIT) Clock (CLK) Block Lock (TBL) Write Protect (WP) Reserved Future (RFU)
Address/Address Multiplexed (A/A Mux) signal descriptions
2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 Address inputs (A0-A10) Data inputs/outputs (DQ0-DQ7) Output Enable Write Enable Row/Column Address Select (RC) Ready/Busy Output (RB)
Supply signal descriptions
2.3.1 2.3.2 2.3.3 supply voltage optional supply voltage ground
operations
Firmware (FWH) operations
3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 Read Write Abort Standby Reset
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M50FW080 3.1.6
Contents Block Protection
Address/Address Multiplexed (A/A Mux) operations
3.2.1 3.2.2 3.2.3 3.2.4 Read Write Output Disable Reset
Command interface
4.10 Read Memory Array command Read Status Register command Read Electronic Signature command Program command Quadruple Byte Program command Chip Erase command Block Erase command Clear Status Register command Program/Erase Suspend command Program/Erase Resume command
Status Register
Program/Erase Controller status (bit Erase Suspend status (bit Erase status (bit Program status (bit status (bit Program Suspend status (bit Block Protection status (bit
5.7.1 Reserved (Bit
Firmware (FWH) interface Configuration Registers
Lock Registers
6.1.1 6.1.2 6.1.3 Write Lock Read Lock Lock Down
Firmware (FWH) General-Purpose Input Register
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Contents
M50FW080
Manufacturer Code Register Device Code Register
Program Erase times Maximum rating parameters Package mechanical Part numbering
Appendix Flowcharts pseudo codes Revision history
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M50FW080
List tables
List tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Signal names (FWH Interface) Signal names (A/A Interface) Block addresses Read field definitions Write field definitions operations Manufacturer device codes Read Electronic Signature Commands Status Register bits. Firmware Register Configuration map. Lock Register definitions General-Purpose Input Register definition Program Erase times Absolute maximum ratings Operating conditions interface measurement conditions. interface measurement conditions Impedance characteristics. interface clock characteristics interface signal timing characteristics Reset characteristics interface Read characteristics interface Write characteristics PLCC32 Rectangular Plastic Leaded Chip Carrier, package data TSOP32 lead Plastic Thin Small Outline, 8x14 package mechanical data TSOP40 lead Plastic Thin Small Outline, 20mm, package mechanical data Ordering information scheme Document revision history
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List figures
M50FW080
List figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Logic diagram (FWH interface) Logic diagram (A/A interface) PLCC connections TSOP32 connections TSOP40 connections Read waveforms Write waveforms. interface testing input output waveforms interface testing input output waveform interface clock waveform interface signal timing waveforms Reset waveforms interface Read waveforms interface Write waveforms PLCC32 Rectangular Plastic Leaded Chip Carrier, package outline TSOP32 lead Plastic Thin Small Outline, 8x14 package outline TSOP40 lead Plastic Thin Small Outline, 20mm, package outline Program flowchart pseudo code Quadruple Byte Program flowchart pseudo code (A/A interface only). Program Suspend Resume flowchart pseudo code Chip Erase flowchart pseudo code (A/A interface only). Block Erase flowchart pseudo code. Erase Suspend Resume flowchart pseudo code
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M50FW080
Summary description
Summary description
M50FW080 Mbit (1Mbit non-volatile memory that read, erased reprogrammed. These operations performed using single voltage (3.0 3.6V) supply. fast programming fast erasing production lines optional power supply used reduce programming erasing times. memory divided into blocks that erased independently possible preserve valid data while data erased. Blocks protected individually prevent accidental Program Erase commands from modifying memory. Program Erase commands written Command Interface memory. on-chip Program/Erase Controller simplifies process programming erasing memory taking care special operations that required update memory contents. program erase operation detected error conditions identified. command required control memory consistent with JEDEC standards. different interfaces supported memory. primary interface, Firmware FWH) Interface, uses Intel's proprietary protocol. This been designed remove need current Chipsets; M50FW080 acts BIOS Count these Chipsets. secondary interface, Address/Address Multiplexed Mux) Interface, designed compatible with current Flash Programmers production line programming prior fitting Motherboard. order meet environmental requirements, offers M50FW080 ECOPACK® packages. ECOPACK® packages Lead-free RoHS compliant. ECOPACK trademark. ECOPACK specifications available www.st.com.
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Summary description Figure Logic diagram (FWH interface)
ID0-ID3 FGPI0FGPI4 FWH4 INIT M50FW080 FWH0FWH3
M50FW080
AI03979
Table
FWH4 ID0-ID3
Signal names (FWH Interface)
Input/Output Communications Input Communication Frame Identification Inputs General Purpose Inputs Interface Configuration Interface Reset Reset Clock Block Lock Write Protect Reserved Future Use. Leave disconnected Supply Voltage Optional Supply Voltage Fast Erase Operations Ground Connected Internally
FWH0-FWH3
FGPI0-FGPI4 INIT
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M50FW080 Figure Logic diagram (A/A interface)
Summary description
A0-A10 DQ0-DQ7
M50FW080
AI03981
Table
A0-A10 DQ0-DQ7
Signal names (A/A Interface)
Interface Configuration Address Inputs Data Inputs/Outputs Output Enable Write Enable Row/Column Address Select Ready/Busy Output Interface Reset Supply Voltage Optional Supply Voltage Fast Program Fast Erase Operations Ground Connected Internally
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Summary description Figure PLCC connections
M50FW080
FGPI2 FGPI3 FGPI4 FGPI1 FGPI0 FWH0 (VIL) INIT FWH4 (VIH) M50FW080 FWH1 FWH2 FWH3
AI04897
Pins internally connected.
Figure
TSOP32 connections
(VIH)
GPI4 GPI3 GPI2 GPI1 GPI0
INIT FWH4/LFRAME FWH3/LAD3 FWH2/LAD2 FWH1/LAD1 FWH0/LAD0
M50FW080
AI09757B
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M50FW080 Figure TSOP40 connections
Summary description
(VIH)
(VIL) FGPI4 FGPI3 FGPI2 FGPI1 FGPI0
M50FW080
FWH4 INIT FWH3 FWH2 FWH1 FWH0
AI03980
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Signal descriptions
M50FW080
Signal descriptions
There distinct interfaces available this device. active interface selected before power-up, during Reset, using Interface Configuration Pin, signals each interface discussed Firmware (FWH) signal descriptions section Address/Address Multiplexed (A/A Mux) signal descriptions section, respectively, while supply signals discussed Supply signal descriptions section.
Firmware (FWH) signal descriptions
Firmware (FWH) Interface Figure Table
2.1.1
Input/Output communications (FWH0-FWH3)
Input Output Communication with memory take place these pins. Addresses Data Read Write operations encoded these pins.
2.1.2
Input communication frame (FWH4)
Input Communication Frame (FWH4) signals start operation. When Input Communication Frame Low, VIL, rising edge Clock operation initiated. Input Communication Frame Low, VIL, during operation then operation aborted. When Input Communication Frame High, VIH, current operation proceeding idle.
2.1.3
Identification inputs (ID0-ID3)
Identification Inputs select address that memory responds memories addressed bus. address left floating driven Low, VIL; internal pull-down resistor included with value RIL. address must driven High, VIH; there will leakage current ILI2 through each when pulled VIH; Table convention boot memory must have address `0000' additional memories take sequential addresses starting from `0001'.
2.1.4
General-purpose inputs (FGPI0-FGPI4)
General Purpose Inputs used digital inputs read. General Purpose Input Register holds values these pins. pins must have stable data from before start cycle that reads General Purpose Input Register until after cycle complete. These pins must left float, they should driven Low, VIL, High, VIH.
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M50FW080
Signal descriptions
2.1.5
Interface configuration (IC)
Interface Configuration input selects whether Firmware (FWH) Address/Address Multiplexed (A/A Mux) Interface used. chosen interface must selected before power-up during Reset and, thereafter, cannot changed. state Interface Configuration, should changed during operation. select Firmware (FWH) Interface Interface Configuration should left float driven Low, VIL; select Address/Address Multiplexed (A/A Mux) Interface should driven High, VIH. internal pull-down resistor included with value RIL; there will leakage current ILI2 through each when pulled VIH; Table
2.1.6
Interface Reset (RP)
Interface Reset (RP) input used reset memory. When Interface Reset (RP) Low, VIL, memory Reset mode: outputs high impedance current consumption minimized. When High, VIH, memory normal operation. After exiting Reset mode, memory enters Read mode.
2.1.7
Reset (INIT)
Reset, INIT, used Reset memory when reset. behaves identically Interface Reset, internal Reset line logical (electrical AND) INIT.
2.1.8
Clock (CLK)
Clock, CLK, input used clock signals Input/Output Communication Pins, FWH0-FWH3. Clock conforms specification.
2.1.9
Block Lock (TBL)
Block Lock input used prevent Block (Block from being changed. When Block Lock, TBL, Low, VIL, Program Block Erase operations Block have effect, regardless state Lock Register. When Block Lock, TBL, High, VIH, protection Block determined Lock Register. state Block Lock, TBL, does affect protection Main Blocks (Blocks 14). Block Lock, TBL, must prior Program Block Erase operation initiated must changed until operation completes unpredictable results occur. Care should taken avoid unpredictable behavior changing during Program Erase Suspend.
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Signal descriptions
M50FW080
2.1.10
Write Protect (WP)
Write Protect input used prevent Main Blocks (Blocks from being changed. When Write Protect, Low, VIL, Program Block Erase operations Main Blocks have effect, regardless state Lock Register. When Write Protect, High, VIH, protection Block determined Lock Register. state Write Protect, does affect protection Block (Block 15). Write Protect, must prior Program Block Erase operation initiated must changed until operation completes unpredictable results occur. Care should taken avoid unpredictable behavior changing during Program Erase Suspend.
2.1.11
Reserved Future (RFU)
These pins have assigned functions this revision part. They must left disconnected. Table Block addresses
Address Range F0000h-FFFFFh E0000h-EFFFFh D0000h-DFFFFh C0000h-CFFFFh B0000h-BFFFFh A0000h-AFFFFh 90000h-9FFFFh 80000h-8FFFFh 70000h-7FFFFh 60000h-6FFFFh 50000h-5FFFFh 40000h-4FFFFh 30000h-3FFFFh 20000h-2FFFFh 10000h-1FFFFh 00000h-0FFFFh Block Number Block Type Block Main Block Main Block Main Block Main Block Main Block Main Block Main Block Main Block Main Block Main Block Main Block Main Block Main Block Main Block Main Block
Size (Kbytes)
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M50FW080
Signal descriptions
Address/Address Multiplexed (A/A Mux) signal descriptions
Address/Address Multiplexed (A/A Mux) Interface Figure Table
2.2.1
Address inputs (A0-A10)
Address Inputs used Address bits (A0-A10) Column Address bits (A11-A19). They latched during operation Row/Column Address Select input,
2.2.2
Data inputs/outputs (DQ0-DQ7)
Data Inputs/Outputs hold data that written read from memory. They output data stored selected address during Read operation. During Write operations they represent commands sent Command Interface internal state machine. Data Inputs/Outputs, DQ0-DQ7, latched during Write operation.
2.2.3
Output Enable
Output Enable, controls Read operation memory.
2.2.4
Write Enable
Write Enable, controls Write operation memory's Command Interface.
2.2.5
Row/Column Address Select (RC)
Row/Column Address Select input selects whether Address Inputs should latched into Address bits (A0-A10) Column Address bits (A11-A19). Address bits latched falling edge whereas Column Address bits latched rising edge.
2.2.6
Ready/Busy Output (RB)
Ready/Busy gives status memory's Program/Erase Controller. When Ready/Busy Low, VOL, memory busy with Program Erase operation will accept additional Program Erase command except Program/Erase Suspend command. When Ready/Busy High, VOH, memory ready Read, Program Erase operation.
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Signal descriptions
M50FW080
Supply signal descriptions
Supply Signals same both interfaces.
2.3.1
supply voltage
Supply Voltage supplies power operations (Read, Program, Erase etc.). Command Interface disabled when Supply Voltage less than Lockout Voltage, VLKO. This prevents Write operations from accidentally damaging data during power power down power surges. Program/Erase Controller programming erasing during this time then operation aborts memory contents being altered will invalid. After becomes valid Command Interface reset Read mode. 0.1µF capacitor should connected between Supply Voltage pins Ground decouple current surges from power supply. Both Supply Voltage pins must connected power supply. track widths must sufficient carry currents required during program erase operations.
2.3.2
optional supply voltage
Optional Supply Voltage used select Fast Program (see Quadruple Byte Program Command description) Fast Erase options memory protect memory. When VPPLK Program Erase operations cannot performed error reported Status Register attempt change memory contents made. When Program Erase operations take place normal. When VPPH Fast Program interface selected) Fast Erase operations used. other voltage input will result undefined behavior should used. should VPPH more than hours during life memory.
2.3.3
ground
reference voltage measurements.
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M50FW080
operations
operations
interfaces have similar operations signals timings completely different. Firmware (FWH) Interface usual interface functionality part available through this interface. Only subset functions available through Address/Address Multiplexed (A/A Mux) Interface. sections: Firmware (FWH) operations Address/Address Multiplexed (A/A Mux) operations, details operations each interface.
Firmware (FWH) operations
Firmware (FWH) Interface consists four data signals (FWH0-FWH3), control line (FWH4) clock (CLK). addition protection against accidental malicious data corruption achieved using further signals (TBL WP). Finally reset signals INIT) available memory into known state. data signals, control signal clock designed compatible with electrical specifications. interface operates with clock speeds 33MHz. following operations performed using appropriate cycles: Read, Write, Standby, Reset Block Protection.
3.1.1
Read
Read operations read from memory cells, specific registers Command Interface Firmware Registers. valid Read operation starts when Input Communication Frame, FWH4, Low, VIL, Clock rises correct Start cycle FWH0-FWH3. following clock cycles Host will send Memory Select, Address other control bits FWH0-FWH3. memory responds outputting Sync data until wait-states have elapsed followed Data0-Data3 Data4-Data7. Table Figure description Field definitions each clock cycle transfer. Table Figure details timings signals.
3.1.2
Write
Write operations write Command Interface Firmware Registers. valid Write operation starts when Input Communication Frame, FWH4, Low, VIL, Clock rises correct Start cycle FWH0-FWH3. following Clock cycles Host will send Memory Select, Address, other control bits, Data0-Data3 Data4-Data7 FWH0-FWH3. memory outputs Sync data until wait-states have elapsed. Table Figure description Field definitions each clock cycle transfer. Table Figure details timings signals.
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operations
M50FW080
3.1.3
Abort
Abort operation used immediately abort current operation. Abort occurs when FWH4 driven Low, VIL, during operation; memory will tristate Input/Output Communication pins, FWH0-FWH3. Note that, during Write operation, Command Interface starts executing command soon data fully received; Abort during final cycles guaranteed abort command; bus, however, will released immediately.
3.1.4
Standby
When FWH4 High, VIH, memory into Standby mode where FWH0-FWH3 into high-impedance state Supply Current reduced Standby level, ICC1.
3.1.5
Reset
During Reset mode internal circuits switched off, memory deselected outputs high-impedance. memory Reset mode when Interface Reset, Reset, INIT, Low, VIL. INIT must held Low, VIL, tPLPH. memory resets Read mode upon return from Reset mode Lock Registers return their default states regardless their state before Reset, Table INIT goes Low, VIL, during Program Erase operation, operation aborted memory cells affected longer contain valid data; memory take tPLRH abort Program Erase operation.
3.1.6
Block Protection
Block Protection forced using signals Block Lock, TBL, Write Protect, regardless state Lock Registers.
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M50FW080
operations
Address/Address Multiplexed (A/A Mux) operations
Address/Address Multiplexed (A/A Mux) Interface more traditional style interface. signals consist multiplexed address signals (A0-A10), data signals, (DQ0-DQ7) three control signals (RC, additional signal, used reset memory. Address/Address Multiplexed (A/A Mux) Interface included Flash Programming equipment faster factory programming. Only subset features available Firmware (FWH) Interface available; these include Commands exclude Security features other registers. following operations performed using appropriate cycles: Read, Write, Output Disable Reset. When Address/Address Multiplexed (A/A Mux) Interface selected blocks unprotected. possible protect blocks through this interface.
3.2.1
Read
Read operations used output contents Memory Array, Electronic Signature Status Register. valid Read operation begins latching Address Column Address signals into memory using Address Inputs, A0-A10, Row/Column Address Select Then Write Enable Interface Reset (RP) must High, VIH, Output Enable, Low, VIL, order perform Read operation. Data Inputs/Outputs will output value, Figure Table details when output becomes valid.
3.2.2
Write
Write operations write Command Interface. valid Write operation begins latching Address Column Address signals into memory using Address Inputs, A0-A10, Row/Column Address Select data should Data Inputs/Outputs; Output Enable, Interface Reset, must High, Write Enable, must Low, VIL. Data Inputs/Outputs latched rising edge Write Enable, Figure Table details timing requirements.
3.2.3
Output Disable
data outputs high-impedance when Output Enable, VIH.
3.2.4
Reset
During Reset mode internal circuits switched off, memory deselected outputs high-impedance. memory Reset mode when Low, VIL. must held Low, tPLPH. goes Low, VIL, during Program Erase operation, operation aborted memory cells affected longer contain valid data; memory take tPLRH abort Program Erase operation.
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operations Table Read field definitions
Field FWH0FWH3 Memory Description
M50FW080
Clock Clock Cycle Cycle Number Count
START
1101b
rising edge with FWH4 Low, contents FWH0-FWH3 indicate start Read cycle. Indicates which Flash Memory selected. value FWH0-FWH3 compared IDSEL strapping Flash Memory pins select which Flash Memory being addressed. 28-bit address phase transferred starting with most significant nibble first. Always 0000b (only single byte transfers supported). host drives FWH0-FWH3 1111b indicate turnaround cycle. Flash Memory takes control FWH0FWH3 during this cycle. Flash Memory drives FWH0-FWH3 0101b (short wait-sync) clock cycles, indicating that data available. wait-states always included. Flash Memory drives FWH0-FWH3 0000b, indicating that data will available during next clock cycle. Data transfer cycles, starting with least significant nibble. Flash Memory drives FWH0-FWH3 1111b indicate turnaround cycle. Flash Memory floats outputs, host takes control FWH0-FWH3.
IDSEL
XXXX
ADDR MSIZE
XXXX 0000b 1111b 1111b (float)
13-14
WSYNC
0101b
RSYNC
0000b
16-17
DATA
XXXX 1111b 1111b (float)
Figure
Read waveforms
FWH4
FWH0-FWH3 Number clock cycles
START
IDSEL
ADDR
MSIZE
SYNC
DATA
AI03437
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M50FW080 Table Write field definitions
Field FWH0FWH3 Memory Description
operations
Clock Clock Cycle Cycle Number Count
START
1110b
rising edge with FWH4 Low, contents FWH0-FWH3 indicate start Write Cycle. Indicates which Flash Memory selected. value FWH0-FWH3 compared IDSEL strapping Flash Memory pins select which Flash Memory being addressed. 28-bit address phase transferred starting with most significant nibble first. Always 0000b (single byte transfer). Data transfer cycles, starting with least significant nibble. host drives FWH0-FWH3 1111b indicate turnaround cycle. Flash Memory takes control FWH0FWH3 during this cycle. Flash Memory drives FWH0-FWH3 0000b, indicating received data command. Flash Memory drives FWH0-FWH3 1111b, indicating turnaround cycle. Flash Memory floats outputs host takes control FWH0-FWH3.
IDSEL
XXXX
11-12
ADDR MSIZE DATA
XXXX 0000b XXXX 1111b 1111b (float) 0000b
SYNC
1111b 1111b (float)
Figure
Write waveforms
FWH4
FWH0-FWH3 Number clock cycles
START
IDSEL
ADDR
MSIZE
DATA
SYNC
AI03441
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operations Table operations
Don't Care VPPH Don't Care Don't Care
M50FW080
Operation Read Write Output Disable Reset
DQ7-DQ0 Data Output Data Input Hi-Z Hi-Z
Table
Manufacturer device codes
Operation A19-A1 DQ7-DQ0
Manufacturer Code Device Code
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M50FW080
Command interface
Command interface
Write operations memory interpreted Command Interface. Commands consist more sequential Write operations. After power-up Reset operation memory enters Read mode. commands summarized Table Commands. following text descriptions should read conjunction with Table
Read Memory Array command
Read Memory Array command returns memory Read mode where behaves like EPROM. Write cycle required issue Read Memory Array command return memory Read mode. Once command issued memory remains Read mode until another command issued. From Read mode Read operations will access memory array. While Program/Erase Controller executing Program Erase operation memory will accept Read Memory Array command until operation completes.
Read Status Register command
Read Status Register command used read Status Register. Write cycle required issue Read Status Register command. Once command issued subsequent Read operations read Status Register until another command issued. section Status Register details definitions Status Register bits.
Read Electronic Signature command
Read Electronic Signature command used read Manufacturer Code Device Code. Write cycle required issue Read Electronic Signature command. Once command issued subsequent Read operations read Manufacturer Code Device Code until another command issued. After Read Electronic Signature Command issued Manufacturer Code Device Code read using Read operations using addresses Table Table Read Electronic Signature
Code Manufacturer Code Device Code Address 00000h 00001h Data
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Command interface
M50FW080
Program command
Program command used program value address memory array time. Write operations required issue command; second Write cycle latches address data internal state machine starts Program/Erase Controller. Once command issued subsequent Read operations read Status Register. section Status Register details definitions Status Register bits. address falls protected block then Program operation will abort, data memory array will changed Status Register will output error. During Program operation memory will only accept Read Status Register command Program/Erase Suspend command. other commands will ignored. Typical Program times given Table Note that Program command cannot change back attempting will cause modification value. Erase commands must used bits block `1'. Figure suggested flowchart using Program command.
Quadruple Byte Program command
Qua-druple Byte Program Command only used mode program four adjacent bytes memory array time. four bytes must differ only addresses A10. Programming should attempted when VPPH. operation also executed below VPPH, result could uncertain. Five Write operations required issue command. second, third fourth Write cycle latches respectively address data first, second third byte internal state machine. fifth Write cycle latches address data fourth byte internal state machine starts Program/Erase Controller. Once command issued subsequent Read operations read Status Register. section Status Register details definitions Status Register bits. During Quadruple Byte Program operation memory will only accept Read Status register command Program/Erase Suspend command. other commands will ignored. Typical Quadruple Byte Program times given Table Note that Quadruple Byte Program command cannot change back attempting will cause modification value. Erase commands must used bits block `1'. Figure Quadruple Byte Program Flowchart Pseudo Code, suggested flowchart using Quadruple Byte Program command.
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M50FW080
Command interface
Chip Erase command
Chip Erase Command only used mode erase entire chip time. Erasing should attempted when VPPH. operation also executed below VPPH, result could uncertain. Write operations required issue command start Program/Erase Controller. Once command issued subsequent Read operations read Status Register. section Status Register details definitions Status Register bits. During Chip Erase operation memory will only accept Read Status Register command. other commands will ignored. Typical Chip Erase times given Table Chip Erase command sets bits memory `1'. Figure suggested flowchart using Chip Erase command.
Block Erase command
Block Erase command used erase block. Write operations required issue command; second Write cycle latches block address internal state machine starts Program/Erase Controller. Once command issued subsequent Read operations read Status Register. section Status Register details definitions Status Register bits. block protected then Block Erase operation will abort, data block will changed Status Register will output error. During Block Erase operation memory will only accept Read Status Register command Program/Erase Suspend command. other commands will ignored. Typical Block Erase times given Table Block Erase command sets bits block `1'. previous data block lost. Figure suggested flowchart using Erase command.
Clear Status Register command
Clear Status Register command used reset bits Status Register `0'. Write required issue Clear Status Register command. Once command issued memory returns previous mode, subsequent Read operations continue output same data. bits Status Register sticky automatically return when Program Erase command issued. error occurs then essential clear error bits Status Register issuing Clear Status Register command before attempting Program Erase command.
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Command interface
M50FW080
Program/Erase Suspend command
Program/Erase Suspend command used pause Program Block Erase operation. Write cycle required issue Program/Erase Suspend command pause Program/Erase Controller. Once command issued necessary poll Program/Erase Controller Status find when Program/Erase Controller paused; other commands will accepted until Program/Erase Controller paused. After Program/Erase Controller paused, memory will continue output Status Register until another command issued. During polling period between issuing Program/Erase Suspend command Program/Erase Controller pausing possible operation complete. Once Program/Erase Controller Status indicates that Program/Erase Controller longer active, Program Suspend Status Erase Suspend Status used determine operation completed suspended. timing delay between issuing Program/Erase Suspend command Program/Erase Controller pausing Table During Program/Erase Suspend Read Memory Array, Read Status Register, Read Electronic Signature Program/Erase Resume commands will accepted Command Interface. Additionally, suspended operation Block Erase then Program command will also accepted; only blocks being erased read programmed correctly. Figure Figure suggested flowcharts using Program/Erase Suspend command.
4.10
Program/Erase Resume command
Program/Erase Resume command used restart Program/Erase Controller after Program/Erase Suspend paused Write cycle required issue Program/Erase Resume command. Once command issued subsequent Read operations read Status Register.
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M50FW080 Table Commands(1)
Command interface
Write operations Cycles Command
Addr Data Addr Data Addr Data Addr Data Addr Data Read Memory Array(2) Quadruple Byte Chip Erase Block
Read Status Register(3) Read Electronic Signature(4) Program(5) Program(6)
Erase(5)
Clear Status Register(8) Program/Erase Suspend Program/Erase
Resume(10)
Invalid/Reserved
(11)
Don't Care, Program Address, Program Data, A1,2,3,4 Consecutive Addresses, address Block. Read Memory Array. After Read Memory Array command, read memory normal until another command issued. Read Status Register. After Read Status Register command, read Status Register normal until another command issued. Read Electronic Signature. After Read Electronic Signature command, read Manufacturer Code, Device Code until another command issued. Block Erase, Program. After these commands read Status Register until command completes another command issued. Quadruple Byte Program. This command only valid mode. Addresses must consecutive addresses differing only address A10. After this command read Status Register until command completes another command issued. Chip Erase. This command only valid mode. After this command read Status Register until command completes another command issued. Clear Status Register. After Clear Status Register command bits Status Register reset `0'. Program/Erase Suspend. After Program/Erase Suspend command been accepted, issue Read Memory Array, Read Status Register, Program (during Erase suspend) Program/Erase resume commands. Program/Erase Resume. After Program/Erase Resume command suspended Program/Erase operation resumes, read Status Register until Program/Erase Controller completes memory returns Read Mode. Invalid/Reserved. Invalid Reserved commands.
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Status Register
M50FW080
Status Register
Status Register provides information current previous Program Erase operation. Different bits Status Register convey different information errors operation. read Status Register Read Status Register command issued. Status Register automatically read after Program, Erase Program/Erase Resume commands issued. Status Register read from address. Status Register bits summarized Table following text descriptions should read conjunction with Table
Program/Erase Controller status (bit
Program/Erase Controller Status indicates whether Program/Erase Controller active inactive. When Program/Erase Controller Status `0', Program/Erase Controller active; when `1', Program/Erase Controller inactive. Program/Erase Controller Status immediately after Program/Erase Suspend command issued until Program/Erase Controller pauses. After Program/Erase Controller pauses `1'. During Program Erase operation Program/Erase Controller Status polled find operation. other bits Status Register should tested until Program/Erase Controller completes operation `1'. After Program/Erase Controller completes operation Erase Status, Program Status, Status Block Protection Status bits should tested errors.
Erase Suspend status (bit
Erase Suspend Status indicates that Block Erase operation been suspended waiting resumed. Erase Suspend Status should only considered valid when Program/Erase Controller Status (Program/Erase Controller inactive); after Program/Erase Suspend command issued memory still complete operation rather than entering Suspend mode. When Erase Suspend Status Program/Erase Controller active completed operation; when Program/Erase Suspend command been issued memory waiting Program/Erase Resume command. When Program/Erase Resume command issued Erase Suspend Status returns `0'.
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M50FW080
Status Register
Erase status (bit
Erase Status used identify memory applied maximum number erase pulses block(s) still failed verify that block(s) erased correctly. Erase Status should read once Program/Erase Controller Status (Program/Erase Controller inactive). When Erase Status memory successfully verified that block(s) erased correctly; when Erase Status Program/Erase Controller applied maximum number pulses block(s) still failed verify that block(s) erased correctly. Once Erase Status only reset Clear Status Register command hardware reset. should reset before Program Erase command issued, otherwise command will appear fail.
Program status (bit
Program Status used identify memory applied maximum number program pulses byte still failed verify that byte programmed correctly. Program Status should read once Program/Erase Controller Status (Program/Erase Controller inactive). When Program Status memory successfully verified that byte programmed correctly; when Program Status Program/Erase Controller applied maximum number pulses byte still failed verify that byte programmed correctly. Once Program Status only reset Clear Status Register command hardware reset. should reset before Program Erase command issued, otherwise command will appear fail.
status (bit
Status used identify invalid voltage during Program Erase operations. only sampled beginning Program Erase operation. Indeterminate results occur becomes invalid during Program Erase operation. When Status voltage sampled valid voltage; when Status voltage that below Lockout Voltage, VPPLK, memory protected; Program Erase operation cannot performed. Once Status only reset Clear Status Register command hardware reset. should reset before Program Erase command issued, otherwise command will appear fail.
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Status Register
M50FW080
Program Suspend status (bit
Program Suspend Status indicates that Program operation been suspended waiting resumed. Program Suspend Status should only considered valid when Program/Erase Controller Status (Program/Erase Controller inactive); after Program/Erase Suspend command issued memory still complete operation rather than entering Suspend mode. When Program Suspend Status Program/Erase Controller active completed operation; when Program/Erase Suspend command been issued memory waiting Program/Erase Resume command. When Program/Erase Resume command issued Program Suspend Status returns `0'.
Block Protection status (bit
Block Protection Status used identify Program Block Erase operation tried modify contents protected block. When Block Protection Status Program Block Erase operations have been attempted protected blocks since last Clear Status Register command hardware reset; when Block Protection Status Program Block Erase operation been attempted protected block. Once Block Protection Status only reset Clear Status Register command hardware reset. should reset before Program Block Erase command issued, otherwise command will appear fail. Using Interface Block Protection Status always `0'.
5.7.1
Reserved (Bit
Status Register reserved. value should masked.
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M50FW080 Table Status Register bits
Operation Program active Program suspended Program completed successfully Program failure Error Program failure Block Protection (FWH Interface only) Program failure cell failure Erase active Block Erase suspended Erase completed successfully Erase failure Error Block Erase failure Block Protection (FWH Interface only) Erase failure failed cell(s)
Status Register
X(1)
X(1) X(1) X(1)
Program operations during Erase Suspend `1', otherwise `0'.
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Firmware (FWH) interface Configuration Registers
M50FW080
Firmware (FWH) interface Configuration Registers
When Firmware Interface selected several additional registers accessed. These registers control protection status Blocks, read General Purpose Input pins identify memory using Electronic Signature codes. Table memory Configuration Registers.
Lock Registers
Lock Registers control protection status Blocks. Each Block Lock Register. Three bits within each Lock Register control protection each block, Write Lock Bit, Read Lock Lock Down Bit. Lock Registers read written, though care should taken when writing once Lock Down set, `1', further modifications Lock Register cannot made until cleared, `0', reset power-up. Table details definitions Lock Registers.
6.1.1
Write Lock
Write Lock determines whether contents Block modified (using Program Block Erase Command). When Write Lock set, `1', block write protected; operations that attempt change data block will fail Status Register will report error. When Write Lock reset, `0', block write protected through Lock Register modified unless write protected through some other means. When less than VPPLK blocks protected cannot modified, regardless state Write Lock Bit. Block Lock, TBL, Low, VIL, then Block (Block write protected cannot modified. Similarly, Write Protect, Low, VIL, then Main Blocks (Blocks write protected cannot modified. After power-up reset Write Lock always (write protected).
6.1.2
Read Lock
Read Lock determines whether contents Block read (from Read mode). When Read Lock set, `1', block read protected; operation that attempts read contents block will read instead. When Read Lock reset, `0', read operations Block return data programmed into block expected. After power-up reset Read Lock always reset (not read protected).
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M50FW080
Firmware (FWH) interface Configuration Registers
6.1.3
Lock Down
Lock Down provides mechanism protecting software data from simple hacking malicious attack. When Lock Down set, `1', further modification Write Lock, Read Lock Lock Down Bits cannot performed. reset power-up required before changes these bits made. When Lock Down reset, `0', Write Lock, Read Lock Lock Down Bits changed. Table Firmware Register Configuration
Register Name Block Lock Register (Block Memory Address FBF0002h FBE0002h FBD0002h FBC0002h FBB0002h FBA0002h FB90002h FB80002h FB70002h FB60002h FB50002h FB40002h FB30002h FB20002h FB10002h FB00002h FBC0100h FBC0000h FBC0001h Default Value Access
Mnemonic T_BLOCK_LK
T_MINUS01_LK Block [-1] Lock Register (Block T_MINUS02_LK Block [-2] Lock Register (Block T_MINUS03_LK Block [-3] Lock Register (Block T_MINUS04_LK Block [-4] Lock Register (Block T_MINUS05_LK Block [-5] Lock Register (Block T_MINUS06_LK Block [-6] Lock Register (Block T_MINUS07_LK Block [-7] Lock Register (Block T_MINUS08_LK Block [-8] Lock Register (Block T_MINUS09_LK Block [-9] Lock Register (Block T_MINUS10_LK Block [-10] Lock Register (Block T_MINUS11_LK Block [-11] Lock Register (Block T_MINUS12_LK Block [-12] Lock Register (Block T_MINUS13_LK Block [-13] Lock Register (Block T_MINUS14_LK Block [-14] Lock Register (Block T_MINUS15_LK Block [-15] Lock Register (Block FGPI_REG MANUF_REG DEV_REG Firmware (FWH) General Purpose Input Register Manufacturer Code Register Device Code Register
Firmware (FWH) General-Purpose Input Register
Firmware (FWH) General Purpose Input Register holds state Firmware Interface General Purpose Input pins, FGPI0-FGPI4. When this register read, state these pins returned. This register read-only writing effect. signals Firmware Interface General Purpose Input pins should remain constant throughout whole Read cycle order guarantee that correct data read.
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Firmware (FWH) interface Configuration Registers
M50FW080
Manufacturer Code Register
Reading Manufacturer Code Register returns manufacturer code memory. manufacturer code STMicroelectronics 20h. This register read-only writing effect.
Device Code Register
Reading Device Code Register returns device code memory, 2Dh. This register read-only writing effect. Table
Read-Lock
Lock Register definitions(1)
Value Reserved Read operations this Block always return 00h. read operations this Block return Memory Array contents. (Default value). Changes Read-Lock Write-Lock cannot performed. Once written Lock-Down cannot cleared `0'; always reset following Reset (using INIT) after power-up. Read-Lock Write-Lock changed writing values them. (Default value). Program Block Erase operations this Block will error Status Register. memory contents will changed. (Default value). Program Block Erase operations this Block executed will modify Block contents. Function
name
Lock-Down
Write-Lock
Applies Block Lock Register (T_BLOCK_LK) Block [-1] Lock Register (T_MINUS01_LK) Block [-15] Lock Register (T_MINUS15_LK).
Table
General-Purpose Input Register definition(1)
Name Value Reserved FGPI4 Input FGPI4 Input FGPI4 Input FGPI3 Input FGPI3 Input FGPI2 Input FGPI2 Input FGPI1 Input FGPI1 Input FGPI0 Input FGPI0 Function
FGPI3
FGPI2
FGPI1
FGPI0
Applies General Purpose Input Register (FGPI_REG).
34/55
M50FW080
Program Erase times
Program Erase times
Program Erase times shown Table Table Program Erase times
Parameter Byte Program Quadruple Byte Program Chip Erase Block Program Block Erase Program/Erase Suspend Program pause(3) Program/Erase Suspend Block Erase pause(3)
25°C, 3.3V This time obtained executing Quadruple Byte Program Command. Sampled only, 100% tested.
Interface
Test Condition
Typ(1)
Unit
0.75
35/55
Maximum rating
M50FW080
Maximum rating
Stressing device above rating listed Absolute Maximum Ratings table cause permanent damage device. These stress ratings only operation device these other conditions above those indicated Operating sections this specification implied. Exposure Absolute Maximum Rating conditions extended periods affect device reliability. Refer also STMicroelectronics SURE Program other relevant quality documents. Table
Symbol TSTG VESD
Absolute maximum ratings
Parameter Storage Temperature Input Output range Supply Voltage Program Voltage Electrostatic Discharge Voltage (Human Body model)(2) Min. -0.50 -0.50 -0.6 -2000 Max. 2000 Unit
Minimum voltage undershoot less than 20ns during transitions. Maximum voltage overshoot less than 20ns during transitions. JEDEC JESD22-A114A (C1=100 R1=1500 R2=500
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M50FW080
parameters
parameters
This section summarizes operating measurement conditions, characteristics device. parameters characteristics Tables that follow, derived from tests performed under Measurement Conditions summarized Table Table Table Designers should check that operating conditions their circuit match operating conditions when relying quoted parameters. Table
Symbol Supply Voltage Ambient Operating Temperature (Device Grade
Operating conditions
Parameter Min. Max. Unit
Table
interface measurement conditions
Parameter Value Unit
Load Capacitance (CL) Input Rise Fall Times Input Pulse Voltages Input Output Timing Ref. Voltages
Table
interface measurement conditions
Parameter Value Unit
Load Capacitance (CL) Input Rise Fall Times Input Pulse Voltages Input Output Timing Ref. Voltages
Figure
interface testing input output waveforms
Input Output Testing Waveform
Output Tri-state Testing Waveform
AI03404
37/55
parameters Figure interface testing input output waveform
1.5V
AI01417
M50FW080
Table
Symbol CIN(2) CCLK(2) LPIN(3)
Impedance(1)
Parameter Input Capacitance Clock Capacitance Recommended Inductance Test Condition Unit
25°C, 1MHz. Sampled only, 100% tested. Specification.
38/55
M50FW080 Table
Symbol
parameters characteristics
Parameter Input High Voltage Input Voltage INIT Input High Voltage INIT Input Voltage Input Leakage Current Input Leakage Current Input Pull Resistor Output High Voltage Output Voltage Output Leakage Current Voltage Voltage (Fast Program/Fast Erase) Lockout Voltage Lockout Voltage Supply Current (Standby) Supply Current (Standby) Supply Current (Any internal operation active) Supply Current (Read) Supply Current (Program/Erase) Supply Current (Read/Standby) Supply Current (Program/Erase active) FWH4 0.9VCC, other inputs 0.9VCC 0.1VCC f(CLK) FWH4 0.1VCC, other inputs 0.9VCC 0.1VCC f(CLK) max, f(CLK) IOUT VIH, 6MHz Program/Erase Controller Active -500µA -100µA 1.5mA 1.8mA VOUT 11.4 ID0, ID1, ID2, 0.45 12.6 -0.5 1.35 -0.5 Interface Test condition -0.5 Unit
VIH(INIT) VIL(INIT) ILI(1) ILI2
VPP1 VPPH VPPLK(2) VLKO(2) ICC1
ICC2
ICC3 ICC4 ICC5(2) IPP1(2)
Input leakage currents include High-Z output leakage bi-directional buffers with tri-state outputs. Sampled only, 100% tested.
39/55
parameters Figure interface clock waveform
tCYC tHIGH tLOW
M50FW080
VCC, p-to-p (minimum)
AI03403
Table
Symbol tCYC tHIGH tLOW
interface clock characteristics
Parameter Cycle Time(1) High Time Time Slew Rate peak peak V/ns Test Condition Value Unit V/ns
Devices must work with clock frequency between 33MHz. Below 16MHz devices guaranteed design rather than tested. Refer Specification.
40/55
M50FW080 Figure interface signal timing waveforms
parameters
tCHQV tCHQZ tCHQX FWH0-FWH3 VALID OUTPUT DATA FLOAT OUTPUT DATA tCHDX VALID VALID INPUT DATA
AI03405
tDVCH
Table
Symbol tCHQV tCHQX(1) tCHQZ tAVCH tDVCH tCHAX tCHDX
interface signal timing characteristics
Symbol tval toff Parameter Data Active (Float Active Delay) Inactive (Active Float Delay) Input Set-up Time(2) Input Hold Time(2) Test condition Value Unit
timing measurements Active/Float transitions defined when current through equals leakage current specification. Applies inputs except CLK.
41/55
parameters Figure Reset waveforms
M50FW080
INIT tPLPH FWH4 tPHWL, tPHGL, tPHFL
tPLRH
AI03420
Table
Symbol tPLPH tPLRH
Reset characteristics
Parameter INIT Reset Pulse Width Program/Erase Inactive Program/Erase Active INIT Slew Rate(1) Rising edge only Interface only Test Condition Value Unit mV/ns
INIT Reset
tPHFL tPHWL tPHGL
INIT High FWH4 High Write Enable Output Enable
Interface only
Chapter Specification.
42/55
M50FW080 Figure interface Read waveforms
tAVAV A0-A10 tAVCL tCLAX tCHQV tGLQV tGLQX DQ0-DQ7 ADDR VALID COLUMN ADDR VALID tAVCH tCHAX
parameters
NEXT ADDR VALID
tGHQZ tGHQX VALID
tPHAV
AI03406
Table
Symbol tAVAV tAVCL tCLAX tAVCH tCHAX tCHQV(1) tGLQV(1) tPHAV tGLQX tGHQZ tGHQX
interface Read characteristics
Parameter Read Cycle Time Address Valid Address Transition Column Address Valid high High Column Address Transition High Output Valid Output Enable Output Valid High Address Valid Output Enable Output Transition Output Enable High Output Hi-Z Output Hold from Output Enable High Test Condition Value Unit
delayed tCHQV tGLQV after rising edge without impact tCHQV.
43/55
parameters Figure interface Write waveforms
Write erase program setup A0-A10 tCLAX tAVCL tWHWL tWLWH tVPHWH tWHRL tQVVPL tDVWH DQ0-DQ7 DIN1 DIN2 tWHDX VALID tWHGL tCHWH Write erase confirm valid address data tAVCH tCHAX Automated erase program delay Read Status Register Data
M50FW080
Ready write another command
AI04194
Table
Symbol tWLWH tDVWH tWHDX tAVCL tCLAX tAVCH tCHAX tWHWL tCHWH tVPHWH
interface Write characteristics
Parameter Write Enable Write Enable High Data Valid Write Enable High Write Enable High Data Transition Address Valid Address Transition Column Address Valid High High Column Address Transition Write Enable High Write Enable High Write Enable High High Write Enable High Write Enable High Output Enable Write Enable High Test condition Value Unit
tWHGL tWHRL
tQVVPL(1),(2) Output Valid, High
Sampled only, 100% tested. Applicable seen logic input (VPP 3.6V).
44/55
M50FW080
Package mechanical
Package mechanical
Figure PLCC32 Rectangular Plastic Leaded Chip Carrier, package outline
0.51 (.020) 1.14 (.045)
PLCC-A
Drawing scale.
Table
Symbol
PLCC32 Rectangular Plastic Leaded Chip Carrier, package data
millimeters 3.18 1.53 0.38 0.33 0.66 3.56 2.41 0.53 0.81 0.10 12.32 11.35 4.78 7.62 14.86 13.89 6.05 10.16 1.27 0.00 0.89 12.57 11.51 5.66 15.11 14.05 6.93 0.13 0.035 0.400 0.050 0.300 0.485 0.447 0.188 0.585 0.547 0.238 0.000 inches 0.125 0.060 0.015 0.013 0.026 0.140 0.095 0.021 0.032 0.004 0.495 0.453 0.223 0.595 0.553 0.273 0.005
45/55
Package mechanical
M50FW080
Figure TSOP32 lead Plastic Thin Small Outline, 8x14 package outline
TSOP-a
Drawing scale.
Table
TSOP32 lead Plastic Thin Small Outline, 8x14 package mechanical data
millimeters inches 1.200 0.050 0.950 0.170 0.100 0.150 1.050 0.270 0.210 0.100 13.800 12.300 0.500 7.900 0.500 14.200 12.500 8.100 0.700 0.0197 0.5433 0.4843 0.3110 0.0197 0.0020 0.0374 0.0067 0.0039 0.0472 0.0059 0.0413 0.0106 0.0083 0.0039 0.5591 0.4921 0.3189 0.0276
Symbol
46/55
M50FW080
Package mechanical Figure TSOP40 lead Plastic Thin Small Outline, 20mm, package outline
TSOP-a
Drawing scale.
Table
TSOP40 lead Plastic Thin Small Outline, 20mm, package mechanical data
millimeters inches 1.200 0.050 0.950 0.170 0.100 0.150 1.050 0.270 0.210 0.100 19.800 18.300 0.500 9.900 0.500 20.200 18.500 10.100 0.700
Symbol
47/55
Part numbering
M50FW080
Part numbering
Table
Example: Device Type Flash Memory BIOS Architecture Firmware Interface Operating Voltage 3.6V Device Function Mbit (1Mbx8), Uniform Blocks Package PLCC32 TSOP32: 14mm(1) TSOP40: 20mm Device Grade Temperature range Device tested with standard test flow Option blank Standard Packing Tape Reel Packing Plating Technology ECOPACK® (RoHs compliant)
Devices sold this package Recommended Design.
Ordering information scheme
M50FW080
Devices shipped from factory with memory content bits erased '1'. list available options (Speed, Package, etc.) further information aspect this device, please contact Sales Office nearest you. category second-Level Interconnect marked package inner label, compliance with JEDEC Standard JESD97. maximum ratings related soldering conditions also marked inner label.
48/55
M50FW080
Flowcharts pseudo codes
Appendix
Flowcharts pseudo codes
Figure Program flowchart pseudo code
Start
Write
Write Address Data
Program command: Write Write Address Data (memory enters read status state after Program command)
Read Status Register Suspend Suspend Loop
Read Status Register SR7=0 Program/Erase Suspend command been executed Enter suspend program loop
FWH/LPC Interface Only
Invalid Error
Enter "VPP invalid" error handler
Program Error
Enter "Program error" error handler
Program Protected Block Error
Enter "Program protected block" error handler
AI08425B
Status check (Protected Block), (VPP invalid) (Program Error) made after each Program operation following correct command sequence. error found, Status Register must cleared before further Program/Erase Controller operations.
49/55
Flowcharts pseudo codes
M50FW080
Figure Quadruple Byte Program flowchart pseudo code (A/A interface only)
Start
Write
Write Address Data
Write Address Data
Quadruple Byte Program command: write write Address Data write Address Data write Address Data write Address Data (memory enters read status state after Quadruple Byte Program command)
Write Address Data
Write Address Data Read Status Register SR7=0 Program/Erase Suspend command been executed Enter suspend program loop
Read Status Register Suspend Suspend Loop
Invalid Error
invalid error: error handler
Program Error
Program error: error handler
AI08437B
Status check (VPP invalid) (Program Error) made after each Program operation following correct command sequence. error found, Status Register must cleared before further Program/Erase Controller operations. Address1, Address Address Address must consecutive addresses differing only address bits
50/55
M50FW080
Flowcharts pseudo codes Figure Program Suspend Resume flowchart pseudo code
Start
Write
Write
Program/Erase Suspend command: write write read Status Register
Read Status Register
Write read Command
while
Program Complete
Program completed
Read data from another address
Write
Write
Program Continues
Read Data
Program/Erase Resume command: write resume program Program operation completed then this necessary. device returns Read normal Program/Erase suspend issued).
AI08426B
error found, Status Register must cleared before further Program/Erase operations. address within bank equally used.
51/55
Flowcharts pseudo codes
M50FW080
Figure Chip Erase flowchart pseudo code (A/A interface only)
Start
Write
Chip Erase command: write write (memory enters read Status Register after Chip Erase command)
Write read Status Register
Read Status Register
while
SR4,
AI08428B
Invalid Error
invalid error: error handler
Command Sequence Error
SR4, Command sequence error: error handler
Erase Error
Erase error: error handler
error found, Status Register must cleared before further Program/Erase Controller operations.
52/55
M50FW080 Figure Block Erase flowchart pseudo code
Start
Flowcharts pseudo codes
Write 20h/32h
Write Block Address
Block Erase command: Write 20h/32h Write block Address (memory enters read Status Register after Block Erase command)
Read Status Register
Suspend
Read Status Register SR7=0 Program/Erase Suspend command been executed Enter suspend program loop
Suspend Loop
SR4, FWH/LPC Interface Only
AI08424B
Invalid Error
Enter "VPP invalid" error handler
Command Sequence Error
SR4, Enter "Command sequence"error handler
Erase Error
Enter "Erase Error" error handler
Erase Protected Block Error
Enter "Erase protected block" error handler
error found, Status Register must cleared before further Program/Erase Controller operations.
53/55
Flowcharts pseudo codes Figure Erase Suspend Resume flowchart pseudo code
Start
M50FW080
Write
Write
Program/Erase Suspend command: write write read Status Register
Read Status Register
while
Erase Complete
Erase completed
Read data from another block/sector Program
Write
Write
Erase Continues
Read Data
Program/Erase Resume command: write resume erase Erase operation completed then this necessary. device returns Read normal Program/Erase suspend issued).
AI08429B
54/55
M50FW080
Revision history
Revision history
Table
Date April 2001 18-May-2001 22-Jun-2001 6-Jul-2001 30-Jan-2002 01-Mar-2002 12-Mar-2002 19-May-2004 19-Aug-2004
Document revision history
Version First Issue Document type: from Product Preview Preliminary Data PLCC32 package added Note changed (Table Absolute Maximum Ratings) Document promoted from Preliminary Data Full Data Sheet pins must left disconnected Specification PLCC32 package mechanical data revised TSOP32 package added. Part numbering information updated. Flowchart illustrations, Appendix, updated. Document reformatted Pins TSOP32 Connections illustration corrected Document converted template. Small text changes. Device Grade removed. Packages ECOPACK® compliant. TLEAD removed from Table Absolute maximum ratings. Blank option removed from below Plating Technology Table Ordering information scheme. Changes
24-Oct-2006
55/55
M50FW080
Please Read Carefully:
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