LM5100A/B/C LM5101A/B/C High Voltage High-Side Low-Side Gate Drivers

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LM5100A/B/C LM5101A/B/C High Voltage High-Side Low-Side Gate Drivers

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LM5100A/B/C, LM5101A/B/C High Voltage High-Side Low-Side Gate Drivers
LM5100A/B/C LM5101A/B/C High Voltage High-Side Low-Side Gate Drivers
LM5100A/B/C LM5101A/B/C High Voltage Gate Drivers designed drive both high-side low-side N-Channel MOSFETs synchronous buck half-bridge configuration. floating high-side driver capable operating with supply voltages 100V. versions provide full gate drive while versions provide respectively. outputs independently controlled with CMOS input thresholds (LM5100A/B/C) input thresholds (LM5101A/B/C). integrated high voltage diode provided charge highside gate drive bootstrap capacitor. robust level shifter operates high speed while consuming power providing clean level transitions from control logic high-side gate driver. Under-voltage lockout provided both low-side high-side power rails. These devices available standard SOIC packages.
Features
Drives both high-side low-side N-Channel MOSFETs Independent high driver logic inputs Bootstrap supply voltage 118V Fast propagation times typical) Drives 1000 load with rise fall times Excellent propagation delay matching typical) Supply rail under-voltage lockout power consumption compatible with HIP2100/HIP2101
Typical Applications
Current push-pull converters Half Full Bridge power converters Synchronous buck converters switch forward power converters Forward with Active Clamp converters
Package
SOIC-8 LLP-10
Simplified Block Diagram
20203103
FIGURE
2006 National Semiconductor Corporation
DS202031
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LM5100A/B/C, LM5101A/B/C
Input/Output Options
Part Number LM5100A LM5101A LM5100B LM5101B LM5100C LM5101C Input Thresholds CMOS CMOS CMOS Peak Output Current
Connection Diagrams
20203101
20203102
FIGURE
Ordering Information
Ordering Number LM5100A/LM5101A LM5100A/LM5101A LM5100A /LM5101A LM5100A/LM5101A LM5100B/LM5101B LM5100B/LM5101B LM5100B/LM5101B LM5100B/LM5101B LM5100C/LM5101C LM5100C/LM5101C LM5100C /LM5101C LM5100C/LM5101C Package Type SOIC SOIC SOIC SOIC SOIC SOIC Package Drawing M08A M08A M08A M08A M08A M08A Supplied units shipped anti static rails 2500 shipped Tape Reel 1000 shipped Tape Reel 4500 shipped Tape Reel units shipped anti static rails 2500 shipped Tape Reel 1000 shipped Tape Reel 4500 shipped Tape Reel units shipped anti static rails 2500 shipped Tape Reel 1000 shipped Tape Reel 4500 shipped Tape Reel
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LM5100A/B/C, LM5101A/B/C
Descriptions
SO-8 LLP-10 Name Description Positive gate drive supply High-side gate driver bootstrap rail High-side gate driver output High-side MOSFET source connection High-side driver control input Application Information Locally decouple using ESR/ESL capacitor located close possible. Connect positive terminal bootstrap capacitor negative terminal bootstrap capacitor should placed close possible. Connect gate high-side MOSFET with short, inductance path. Connect bootstrap capacitor negative terminal source high-side MOSFET. LM5100A/B/C inputs have CMOS type thresholds. LM5101A/B/C inputs have type thresholds. Unused inputs should tied ground left open. LM5100A/B/C inputs have CMOS type thresholds. LM5101A/B/C inputs have type thresholds. Unused inputs should tied ground left open. signals referenced this ground. Connect gate low-side MOSFET with short, inductance path.
Low-side driver control input
Ground return Low-side gate driver output
Note: LLP-10 package, recommended that exposed bottom package soldered ground plane board, that ground plane should extend from beneath help dissipate heat. Pins have connection.
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LM5100A/B/C, LM5101A/B/C
Absolute Maximum Ratings (Note
Military/Aerospace specified devices required, please contact National Semiconductor Sales Office/ Distributors availability specifications. Input Output Output (Note Junction Temperature -0.3V +18V -0.3V +18V -0.3V +0.3V -0.3V +0.3V -0.3V +0.3V +100V 118V +150°C
Storage Temperature Range Rating (Note
-55°C +150°C
Recommended Operating Conditions
Slew Rate Junction Temperature +14V 100V +14V
V/ns
-40°C +125°C
Electrical Characteristics
Limits standard type 25°C only; limits boldface type apply over junction temperature (TJ) range -40°C +125°C. Minimum Maximum limits guaranteed through test, design, statistical correlation. Typical values represent most likely parametric norm 25°C, provided reference purposes only. Unless otherwise specified, 12V, Load (Note Symbol SUPPLY CURRENTS IDDO IHBO IHBS IHBSO VIHYS VIHYS VDDR VDDH VHBR VHBH Quiescent Current, LM5100A/B/C Quiescent Current, LM5101A/B/C Operating Current Total Quiescent Current Total Operating Current Current, Quiescent Current, Operating Input Voltage Threshold LM5100A/B/C Input Voltage Threshold LM5101A/B/C Input Voltage Hysteresis LM5100A/B/C Input Voltage Hysteresis LM5101A/B/C Input Pulldown Resistance Rising Threshold Threshold Hysteresis Rising Threshold Threshold Hysteresis Low-Current Forward Voltage High-Current Forward Voltage Dynamic Resistance LM5100A/B/C, LM5101A/B/C Low-Level Output Voltage LM5100A/LM5101A Low-Level Output Voltage LM5100B/LM5101B Low-Level Output Voltage LM5100C/LM5101C IVDD-HB IVDD-HB IVDD-HB 100V Rising Edge Rising Edge 0.25 0.06 0.52 0.85 1.65 Parameter Conditions Units
INPUT PINS
UNDER VOLTAGE PROTECTION
BOOT STRAP DIODE
GATE DRIVER 0.12 0.16 0.28 0.25 0.65
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LM5100A/B/C, LM5101A/B/C
Electrical Characteristics
(Continued) Limits standard type 25°C only; limits boldface type apply over junction temperature (TJ) range -40°C +125°C. Minimum Maximum limits guaranteed through test, design, statistical correlation. Typical values represent most likely parametric norm 25°C, provided reference purposes only. Unless otherwise specified, 12V, Load (Note Parameter High-Level Output Voltage LM5100A/LM5101A High-Level Output Voltage LM5100B/LM5101B High-Level Output Voltage LM5100C/LM5101C Conditions VDD- Units
Symbol GATE DRIVER
0.24 0.28 0.60
0.45 0.60 1.10
IOHL
Peak Pullup Current LM5100A/LM5101A Peak Pullup Current LM5100B/LM5101B Peak Pullup Current LM5100C/LM5101C
IOLL
Peak Pulldown Current LM5100A/LM5101A Peak Pulldown Current LM5100B/LM5101B Peak Pulldown Current LM5100C/LM5101C
THERMAL RESISTANCE Junction Ambient SOIC-8 LLP-10 (Note °C/W
Switching Characteristics
Limits standard type 25°C only; limits boldface type apply over junction temperature (TJ) range -40°C +125°C. Minimum Maximum limits guaranteed through test, design, statistical correlation. Typical values represent most likely parametric norm 25°C, provided reference purposes only. Unless otherwise specified, 12V, Load (Note Symbol tLPHL Parameter Turn-Off Propagation Delay LM5100A/B/C Turn-Off Propagation Delay LM5101A/B/C tLPLH Turn-On Propagation Delay LM5100A/B/C Turn-On Propagation Delay LM5101A/B/C tHPHL Turn-Off Propagation Delay LM5100A/B/C Turn-Off Propagation Delay LM5101A/B/C tHPLH Turn-On Propagation Delay LM5100A/B/C Turn-On Propagation Delay LM5101A/B/C tMON Delay Matching: LM5100A/B/C Delay Matching: LM5101A/B/C tMOFF Delay Matching: LM5100A/B/C Delay Matching: LM5101A/B/C tRC, Either Output Rise/Fall Time 1000 Rising Rising Falling Falling Rising Rising Conditions Falling Falling Units
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LM5100A/B/C, LM5101A/B/C
Switching Characteristics
(Continued) Limits standard type 25°C only; limits boldface type apply over junction temperature (TJ) range -40°C +125°C. Minimum Maximum limits guaranteed through test, design, statistical correlation. Typical values represent most likely parametric norm 25°C, provided reference purposes only. Unless otherwise specified, 12V, Load (Note Parameter Output Rise Time LM5100A/LM5101A Output Rise Time LM5100B/LM5101B Output Rise Time LM5100C/LM5101C Conditions Units
Symbol
Output Fall Time LM5100A/LM5101A Output Fall Time LM5100B/LM5101B Output Fall Time LM5100C/LM5101C
Minimum Input Pulse Width that Changes Output Bootstrap Diode Reverse Recovery Time
Note Absolute Maximum Ratings indicate limits beyond which damage component occur. Operating Ratings conditions under which operation device guaranteed. Operating Ratings imply guaranteed performance limits. guaranteed performance limits associated test conditions, Electrical Characteristics tables. Note human body model capacitor discharged through 1.5k resistor into each pin. pins except which rated 1000V. Note layer board with finished thickness 1.5/1/1/1.5 Maximum size used. body length trace top. 50mm ground power planes embedded PCB. Application Note AN-1187. Note limits 100% production tested 25°C. Limits over operating temperature range guaranteed through correlation using Statistical Quality Control (SQC) methods. Limits used calculate National's Average Outgoing Quality Level (AOQL). Note given constant package depends printed circuit board design operating environment. Note application node clamped body diode external lower N-MOSFET, therefore node will generally exceed -1V. However, some applications, board resistance inductance result node exceeding this stated voltage transiently. negative transients occur, voltage must never more negative than VDD-15V. example 10V, negative transients must exceed -5V.
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LM5100A/B/C, LM5101A/B/C
Typical Performance Characteristics
Peak Sourcing Current Peak Sinking Current
20203127
20203128
Sink Current Output Voltage
Source Current Output Voltage
20203129
20203130
LM5100A/B/C Frequency
LM5101A/B/C Frequency
20203110 20203109
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LM5100A/B/C, LM5101A/B/C
Typical Performance Characteristics
Operating Current Temperature
(Continued) Frequency
20203111
20203114
Quiescent Current Supply Voltage
Quiescent Current Temperature
20203118
20203119
Undervoltage Rising Thresholds Temperature
Undervoltage Threshold Hysteresis Temperature
20203122
20203117
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LM5100A/B/C, LM5101A/B/C
Typical Performance Characteristics
Bootstrap Diode Forward Voltage
(Continued) LM5100A/B/C Input Threshold Temperature
20203123 20203115
LM5101A/B/C Input Threshold Temperature
LM5100A/B/C Input Threshold
20203124
20203125
LM5101A/B/C Input Threshold
LM5100A/B/C Propagation Delay Temperature
20203126
20203112
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LM5100A/B/C, LM5101A/B/C
Typical Performance Characteristics
LM5101A/B/C Propagation Delay Temperature
(Continued) Gate Drive High Level Output Voltage Temperature
20203120 20203113
Gate Drive Level Output Voltage Temperature
Gate Drive Output High Voltage
20203121
20203131
Gate Drive Output Voltage
20203132
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LM5100A/B/C, LM5101A/B/C
Timing Diagram
20203104
FIGURE
Layout Considerations
optimum performance high low-side gate drivers cannot achieved without taking considerations during circuit board layout. Following points emphasized. capacitors must connected close between pins between pins support high peak currents being drawn from during turn-on external MOSFET. prevent large voltage transients drain MOSFET, electrolytic capacitor must connected between MOSFET drain ground (VSS). order avoid large negative transients switch node pin), parasitic inductances source MOSFET drain bottom MOSFET (synchronous rectifier) must minimized. Grounding Considerations: first priority designing grounding connections confine high peak currents that charge discharge MOSFET gate into minimal physical area. This will decrease loop inductance minimize noise issues gate terminal MOSFET. MOSFETs should placed close possible gate driver. second high current path includes bootstrap capacitor, bootstrap diode, local ground referenced bypass capacitor low-side MOSFET body diode. bootstrap capacitor recharged cycle-by-cycle basis through bootstrap diode from ground referenced bypass capacitor. recharging occurs short time interval involves high peak current. Minimizing this loop length area circuit board important ensure reliable operation.
losses related switching frequency (f), output load capacitance (CL), supply voltage (VDD) roughly calculated PDGATES VDD2 There some additional losses gate drivers internal CMOS stages used buffer outputs. following plot shows measured gate driver power dissipation versus frequency load capacitance. higher frequencies load capacitance values, power dissipation dominated power losses driving output loads agrees well with above equation. This plot used approximate power losses gate drivers. Gate Driver Power Dissipation 12V, Neglecting Diode Losses
20203105
Power Dissipation Considerations
total power dissipation gate driver losses bootstrap diode losses. gate driver
bootstrap diode power loss forward bias power loss that occurs while charging bootstrap capacitor reverse bias power loss that occurs during reverse recovery. Since each these events happens once cycle, diode power loss proportional frequency.
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LM5100A/B/C, LM5101A/B/C
Power Dissipation Considerations
(Continued) Larger capacitive loads require more energy recharge bootstrap capacitor resulting more losses. Higher input voltages (VIN) half bridge result higher reverse recovery losses. following plot generated based calculations measurements diode recovery time current under several operating conditions. This useful approximating diode power dissipation. total power dissipation estimated from previous plots summing gate drive losses with bootstrap diode losses intended application.
Diode Power Dissipation
20203106
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LM5100A/B/C, LM5101A/B/C
Physical Dimensions
inches (millimeters) unless otherwise noted
Controlling dimension inch. Values millimeters. Notes: Unless otherwise specified.
Standard lead finish microinches/5.08 micrometers minimum lead/tin (solder) copper. Dimension does include mold flash. Reference JEDEC registration MS-012, Variation dated 1990. SOIC-8 Outline Drawing Package Number M08A
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LM5100A/B/C, LM5101A/B/C High Voltage High-Side Low-Side Gate Drivers
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Notes: Unless otherwise specified.
solder thickness composition, "Solder Information" packaging section National Semiconductor page (www.national.com). Maximum allowable metal burr lead tips package edges microns. JEDEC registration 2003. LLP-10 Outline Drawing Package Number SDC10A
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LM5100A/B/C, LM5101A/B/C High Voltage High-Side Low-Side Gate Drivers
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LM5100A/B/C LM5101A/B/C High Voltage High-Side Low-Side Gate Drivers

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