IRS20954S Protected Digital Audio Driver Floating input enab

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IRS20954S Protected Digital Audio Driver Floating input enab

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Data Sheet PD60276
IRS20954S
Protected Digital Audio Driver
Floating input enables easy half bridge implementation Integrated programmable bi-directional over-current protection with self-reset function Programmable compensated preset deadtime improved performances High noise immunity ±100 high voltage ratings deliver output power logic compatible input Operates RoHS compliant
Product Summary
VOFFSET (max) Gate driver Selectable Deadtime Propagation delay protection delay
(max)
Description
IRS20954 high voltage, high speed MOSFET driver with floating input, specially designed Class audio amplifier applications. bi-directional current sensing requires external shunt resistors. capture over-current conditions either positive negative load current direction. built-in control block provides secure protection sequence against over-current conditions, including programmable reset timer. internal deadtime generation block provides accurate gate switch timing enables optimum deadtime settings better audio performances, such audio noise floor.
Package
16-Lead SOIC (narrow body)
Typical Connection
20954
VREF Speaker
(Please refer Lead Assignments correct configuration. This diagram shows electrical connections only)
OCSET
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IRS20954S
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage device occur. voltage parameters absolute voltages referenced VSS; currents defined positive into lead. thermal resistance power dissipation ratings measured under board mounted still conditions.
Symbol
VCSH VCSD VOCSET VREF IDDZ ICCZ IBSZ IOREF Rth,JA
Definition
High-side floating supply voltage High-side floating supply voltage (Note High-side floating output voltage input voltage Low-side fixed supply voltage (Note Low-side output voltage Floating input supply voltage Floating input supply voltage (Note input voltage input voltage input voltage OCSET input voltage VREF voltage Floating input supply zener clamp current (Note Low-side supply zener clamp current (Note Floating supply zener clamp current (Note Reference output current Allowable voltage slew rate Allowable voltage slew rate (Note Allowable voltage slew rate upon power-up (Note Maximum power dissipation Thermal resistance, junction ambient Junction temperature Storage temperature Lead temperature (soldering, seconds)
Min.
-0.3 VB-20 Vs-0.3 Vs-0.3 -0.3 -0.3 -0.3 (see IDDZ) -0.3 -0.3 -0.3 -0.3 -0.3
Max.
VB+0.3 VB+0.3 VB+0.3 +0.3 VDD+0.3 VDD+0.3 VDD+0.3 +0.3 +0.3 +0.3
Units
V/ns V/ms °C/W
Note1: VSS, -COM contain internal shunt zener diodes. Please note that voltage ratings these limited clamping current. Note2: rising falling edges step signal Vss=15 Note3: ramps from
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IRS20954S
Recommended Operating Conditions
proper operation, device should used within recommended conditions below. offset ratings tested with supplies biased IDD=5 VCC=12 VB-VS=12
Symbol
IDDZ VCSD IOREF VOCSET
Definition
High-side floating supply absolute voltage High-side floating supply offset voltage Floating input supply Zener clamp current Floating input supply absolute voltage High-side floating output voltage Low-side fixed supply voltage Low-side output voltage input voltage input voltage input voltage Reference output current (Note OCSET input voltage
Min.
Vs+10 Note
Max.
Vs+18
Units
Ambient temperature Note Logic operational equal +200 Logic state held equal -VBS. Note Nominal voltage VREF IOREF dictates total external resistor value VREF 16.7
Electrical Characteristics
VCC, VBS= IDD=5 VSS=20 VS=0 CL=1 TA=25 unless otherwise specified.
Symbol
Definition
Min. 19.8 19.8
Typ. 20.8 20.8 10.4
Max. 21.8
Units
Test Conditions
Low-side Supply UVCC+ supply UVLO positive threshold UVCCVCC supply UVLO negative threshold IQCC Low-side quiescent current VCLAMPL Low-side Zener diode clamp voltage High-side Floating Supply High-side well UVLO positive UVBS+ threshold High-side well UVLO negative UVBSthreshold IQBS High-side quiescent current ILKH High-side low-side leakage current VCLAMPH High-side Zener diode clamp voltage Floating Input Supply VDD, floating supply UVLO UVDD+ positive threshold VDD, floating supply UVLO UVDDnegative threshold IQDD Floating input quiescent current Floating input Zener diode clamp VCLAMPM voltage Floating input side low-side leakage ILKM current
ICC=2
21.8 10.9 VDD=9.5 +Vss IDD=2 VDD=VSS =200 VB=VS =200 IBS=2
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IRS20954S
Electrical Characteristics (cont.)
Symbol
Definition
Min. 1.0+ 0.62 0.26
Typ. 1.2+ 0.70 0.30
Max. 1.4+ 0.78 0.34
Units
Test Conditions
Floating Input Logic high input threshold voltage Logic input threshold voltage IIN+ Logic input bias current IINLogic input bias current Protection VREF Reference output voltage Vth,OCL Vth,OCH Vth,1 Vth,2 ICSD+ ICSDLow-side threshold High-side threshold VCSH
=3.3 IOREF =0.5 OCSET=1.2 Fig. Vs=200 Fig.
shutdown release threshold self reset threshold discharge current charge current Shutdown propagation delay from VCSD VthOCH shutdown Propagation delay time from VCSH tOCH VthOCH shutdown Propagation delay time from tOCL VthOCL shutdown Gate Driver (Fig.5) Output high short circuit current (source) IoOutput short circuit current (sink) level output voltage COM, High level output voltage Turn-on rise time Turn-off fall time High- low-side turn-on propagation ton_1 delay, floating inputs High- low-side turn-off propagation toff_1 delay, floating inputs High- low-side turn-on propagation ton_2 delay, non-floating inputs High- low-side turn-off propagation toff_2 delay, non-floating inputs Deadtime: turn-off turn-on (DTLO-HO) turn-off turn-on (DTHO-LO) Deadtime: turn-off turn-on (DTLO-HO) turn-off turn-on (DTHO-LO) Deadtime: turn-off turn-on (DTLO-HO) turn-off turn-on (DTHO-LO) Deadtime: turn-off turn-on (DTLO-HO) turn-off turn-on (DTHO-LO)VDT= VDT4
Fig.
Fig. Fig.
Vo=0 PW<10 Vo=12 PW<10
VDT>VDT1, VDT1>VDT> VDT2, VDT2>VDT> VDT3, VDT3>VDT> VDT4, VCC, Io=0
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IRS20954S
Electrical Characteristics (cont.)
Symbol VDT1 VDT2 VDT3
Definition
mode select threshold mode select threshold mode select threshold
Min.
Typ.
Max.
Units
Test Conditions
Lead Definitions
Symbol
VREF OCSET
Description
Floating input positive supply Shutdown timing capacitor, referenced non-inverting input, phase with Floating input supply return reference output setting OCSET Low-side over-current threshold setting, referenced Input programmable deadtime, referenced Low-side supply return Low-side output Low-side logic supply High-side floating supply return High-side output High-side floating supply High-side over-current sensing input, referenced
VREF OCSET
20954
IRS20954 Lead SOIC (narrow body)
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IRS20954S
Block Diagram
FLOATING INPUT
DETECT
DETECT
10.4V
INPUT LOGIC
HIGH SIDE
20.8V
LEVEL SHIFT
LEVEL SHIFT
FLOATING HIGH SIDE
LEVEL SHIFT
CHARGE/ DISCHARGE
DETECT
DEAD-TIME
PROTECTION CONTROL
LEVEL SHIFT
LEVEL SHIFT
20.8V
SIDE
OCSET
5.1V REFERENCE
VREF
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IRS20954S
Figure Switching Time Waveform Definitions
Vth1
HO/LO
Figure Shutdown Waveform Definitions
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IRS20954S
Vth1
HO/LO
Figure Shutdown Waveform Definitions
VTHCSL
tOCL
Figure VTH,SCL Shutdown Waveform Definitions
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IRS20954S
Functional Description
Floating Input IRS20954 floating input interface which enables easy half bridge implementation. Three pins, VDD, referenced VSS. result, input signal directly into referencing ground, which typically middle point half bridge configuration. IRS20954 also non-floating input with tied COM.
10.4V
LEVEL SHIFT
PROTECTION
Floating Bias 200V
Floating Input Isolation
IRS20954
Figure Floating Input Structure Over-Current Protection (OCP)
IRS20954 features over-current protection protect power MOSFET from over load conditions. IRS20954 enters shutdown mode when detects over-current condition either from side high side current sensing. timing control block measures resume timing interval with external timing capacitor critical timing over-current protection specified guaranteed secure protection. sequence over-current detection soon either high side current sensing block detects over-current condition, Latch (OCL) flips shutdowns outputs starts discharging external capacitor When VSCD crosses lower threshold Vth2, output signal from COMP2 resets OCL. starts charging external capacitor When VSCD crosses upper threshold Vth1, COMP1 flips enables shutdown signal released. current sensing block detects over-current condition, sequence repeated until cause over-current goes away.
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IRS20954S
VCSD
Vth1 Vth2
detection
Charge
Capacitor
Discharge
Shutdown
Power mute
Release
Normal operation
Protection reset interval
Normal operation
Figure Over-Current Protection Timing Chart
Protection Control internal protection control block manages operational mode between shutdown normal, with help from pin. Shutdown mode forces output respectively turn power MOSFET off. external capacitor pin, CSD, provides five functions. Power delay timer self reset configuration Self-reset configuration Shutdown input Latched protection configuration Shutdown status output (host I/F)
Vth1
COMP1
UVLO(VB)
COMP2
Vth2
LEVEL SHIFT
FLOATING INPUT
LEVEL SHIFT
LEVEL SHIFT
FLOATING HIGH SIDE
SIDE
UVLO(VCC)
DEAD TIME
Figure Shutdown Functional Block Diagram
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IRS20954S
Self Reset Protection simply putting capacitor between VSS, IRS20954 acts self.
VREF OCSET
Figure Self-Reset Protection Configuration Designing
Timing capacitor programs protection resume interval timing given
[sec]
example, with capacitor VDD=10.8 start-up time tSU, from power-up shutdown release, given
[sec]
where ICSD charge/discharge current pin, supply voltage respect VSS. Protection-resume timing should long enough avoid over heating failure MOSFET from repetitive sequences shutdown resume when load continuous short circuit. most applications, minimum recommended protection-resume timing Shutdown Input
externally discharging down below Vth2, example with transistor shown Fig. IRS20954 enters shutdown mode. operation resumes when voltage comes back cross upper threshold CSD, Vth1, charging process.
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IRS20954S
SHUTDOWN
VREF OCSET
Figure Shutdown Input
Latched Protection Connecting through less resistor configures IRS20954 latched over-current protection. over-current protection stays shutdown mode after over-current condition detected. reset latch status, external reset switch brings voltage down below lower threshold, Vth2. Minimum reset pulse width required
<10k
RESET
VREF OCSET
Figure Latched Protection Configuration
Interfacing with System Controller
IRS20954 communicates with external system controller adding simple interfacing circuit shown Fig. generic PNP-BJT such 2N3906, send signal when event happens capturing sinking current pin. Another generic NPN-BJT such 2N3094, reset internal protection logic pulling voltage below Vth2. Note that configured latched type this configuration.
<10k
RESET
VREF
OCSET
Figure Interfacing System Controller Programming Trip Level
Class audio amplifier, direction load current alternates according audio input signal. overcurrent condition therefore happen during either positive current cycle negative current cycle. IRS20954 uses RDS(ON) output MOSFET current sensing resistors. high voltage structural constraints, high side have different implementations current sensing. Once measured current gets exceeded predetermined threshold, output signal protection block shutdown MOSFET protect devices.
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IRS20954S
DETECT
HIGH SIDE
LEVEL SHIFT
FLOATING HIGH SIDE
DETECT
LEVEL SHIFT
DEAD TIME
SIDE
OCSET
VREF
Figure Bi-Directional Over-Current Protection Side Over-Current Sensing negative load current, side over-current sensing monitors over load condition shutdown switching operation load current exceeds preset trip level. side current sensing based measurement during side MOFET state. order avoid incorrect current value overshoot sensing ignores first signal after turned OCSET program threshold side over-current sensing. threshold voltage turning protection same voltage applied OCSET COM. recommended VREF supply reference voltage resistive divider, generating voltage OCSET better immunity against fluctuations.
OCREF
5.1V
0.5mA
OCSET
Comparator
IRS20954
Figure Low-Side Over-Current Sensing
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IRS20954S
Since sensed voltage compared with voltages OCSET pin, required voltage OCSET with respect trip level ITRIP+ VOCSET VDS(LOW SIDE) ITRIP+ RDS(ON) order neglect input bias current OCSET pin, recommended total drain through resistors. High Side Over-Current Sensing positive load current, high side over-current sensing monitors over load condition measuring with pins shutdown operation. detect drain-to-source voltage refers which source high side MOSFET. order neglect overshoot ringing switching edges, sensing circuitry starts monitoring after first blanking signal from pin. contrast side current sensing, threshold engage protection internally fixed external resistive divider used program higher threshold. external reverse blocking diode, block high voltage feeding into while high side off. subtracting forward voltage drop minimum threshold which high side across drain source. With configuration Fig. voltage
VCSH HIGHSIDE
Where: VDS(HIGH SIDE) drain source voltage high side MOSFET state VF(D1) forward drop voltage Since VDS(HIGH SIDE) determined product drain current RDS(ON) high side MOSFET. VCSH written
VCSH
(RDS
VthOCH
reverse blocking diode forward biased resistor when high side MOSFET
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IRS20954S
Comparator
1.2V
IRS20954
Figure Programming High Side Over-Current Threshold Design Example
High Side Over-current Setting
Fig. demonstrates typical peripheral circuit high side current sensing. example, over-current protection level trip with MOSFET with RDS(ON) component values calculated Choose R2+R3=10 thus
VthOCH
VthOCL
VDS@ID=30A
voltage drop ID=30 across RDS(ON) high side MOSFET. forward voltage reverse blocking diode, values from E-12 series are:
Choosing Right Reverse Blocking Diode
reverse blocking diode determined voltage rating speed. block voltage, reverse voltage higher than (+B)-(-B). Also reverse recovery time needs fast bootstrap charging diode. Philips BAV21W, high speed switching diode, more than sufficient.
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IRS20954S
Side Over-current Setting Designing with same MOSFET high side with RDS(ON) OCSET voltage, VOCSET, trip level given VOCSET ITRIP+ RDS(ON)
Choose R4+R5=10 proper loading VREF pin, thus
VOCSET VREF
3.0V 5.1V 5.8k
Where VREF output voltage VREF pin, typical. Choose from E-12 series. general, RDS(ON) positive temperature coefficient that needs considered when threshold level being set. Although this characteristic preferable from device protection point view, these variation needs considered well variations external internal component values.
Deadtime Generator
deadtime generator block provides blanking time between high-side low-side avoid simultaneous state causing shoot-through. IRS20954 internal deadtime generation block reduce number external components output stage Class audio amplifier. Selectable deadtime programmed through DT/SD voltage easy reliable function, which requires only external resistors. This selectable deadtime setting prevents outside noise from modulating switching timing, which critical audio performances.
Determine Optimal Deadtime effective deadtime actual application differs from deadtime specified this datasheet finite switching fall time, deadtime value this datasheet defined time period from starting point turn-off side switching stage starting point turn-on other side shown Fig. fall time MOSFET gate voltage must subtracted from deadtime value datasheet determine effective dead time Class audio amplifier. (Effective deadtime) (Deadtime datasheet) (fall time,
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IRS20954S
Effective dead-time
Deadtime
Figure Effective Deadtime
longer dead time period required MOSFET with larger gate charge value because longer shorter effective deadtime setting always beneficial achieve better linearity Class switching stage. However, likelihood shoot-through current increases with narrower deadtime settings mass production. Negative values effective deadtime cause excessive heat dissipation MOSFETs, potentially leading serious damage. calculate optimal deadtime given application, fall time both output voltages, actual circuit needs measured. addition, effective deadtime also vary with temperature device parameter variations. Therefore, minimum effective deadtime recommended avoid shoot-through current over range operating temperatures supply voltages.
Programming Deadtime provides function setting deadtime. IRS20954 determines deadtime based voltage applied pin. internal comparator translates which pre-determined deadtime being used comparing internal reference voltages. Threshold voltages each mode internally resistive voltage divider VCC, negating need using precise absolute voltage mode. relationship between operation mode voltage illustrated Fig. below.
Dead- time
15nS 25nS 35nS 45nS
0.23 xVcc
0.36 xVcc
0.57 xVcc
Figure Deadtime Settings Voltage
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IRS20954S
Table shows suggested values resistance setting deadtime. Resistors with tolerance used these listed values followed.
IRS20954
>0.5mA
Figure External Resistor Deadtime DT/SD mode voltage Open 4.7k Table Suggested Resistor Values Deadtime Settings Power Supply Considerations Supplying designed supplied with internal zener diode clamp. supply current estimated switching frequency (Dynamic power consumption) (Static) (zener bias) resistance feed this therefore
10.8V
case average switching frequency, required 1.18 condition using power supply voltage yields Rdd=33 Make sure below maximum zener diode bias current, IDDZ, static state conditions such condition with input.
10.8V 0.5mA
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IRS20954S
IRS20954S
10.4V
VREF
OCSET
Figure Supplying
Charging Prior start
high side bootstrap power supply charged through resistor from positive supply utilizing internal 20.8 zener diode clamp between Advantage this scheme eliminate minimum duration required initial low-side determine requirement Rcharge, following condition met;
CHARGE
Where ICHARGE required charging current through Rcharge IQBS high side quiescent current Note that Rcharge drain floating supply charge during state high side, which limits maximum modulation index capability system. Rcharge should large enough discharge floating power supply during high side
Icharge
IRS20954S
Rcharge
IQBS
20.8V
IQBC
VREF
OCSET
20.8V
Figure Bootstrap Supply Pre-Charging
Start-up Sequence (UVLO)
protection control block monitors status power supply whether voltages above Under Voltage Lockout threshold. IRS20954 disabled shutdown until UVLO released timer capacitor charged After UVLO released, resets power-on timer. time voltage reached release threshold, Vth1, shutdown logic enables detection blocks side high side disabled until UVLO released.
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IRS20954S
Power-down Sequence soon reaches UVLO negative going threshold, protection logic makes turn MOSFET.
UVLO(
CHARGE DISCHARGE
Discharge
Figure IRS20954 Power-Down Timing Chart
Power Supply Decoupling IRS20954 contains analog circuitry, careful attention power supply decoupling should taken achieve proper operation. Ceramic capacitors more close power supply pins recommended. Please also refer application note AN-978 general considerations high voltage gate driver
Negative Bias Clamping There case that below potential such case missing negative supply dual supply configuration. This causes excessive negative voltage damage IRS20954. recommended have diode clamp potential negative bias VSS, there possibility. standard recovery diode such 1N4002 sufficient most cases this purpose.
VREF Negative Clamping Diode OCSET
-Vbus
Figure Negative Clamping
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IRS20954S
Junction Temperature Estimation power dissipation IRS20954 consists following dominant items; PMID: dissipation floating input logic protection PLOW: dissipation side PHIGH: dissipation high side PMID: Dissipation Floating Input Section
dissipation floating input section given
PMID PZDD PLDD
Where PZDD dissipation from internal zener diode clamping voltage. PLDD dissipation from internal logic circuitry. V+BUS positive voltage feeding from. resistor feeding from V+BUS. obtaining value RDD, refer Supplying section above. PLOW: Dissipation Side
dissipation side includes loss from logic circuitry loss from driving given
PLOW PLDD (int)
Where PLDD dissipation from internal logic circuitry. dissipation from gate drive stage equivalent output impedance typically IRS20954. Rg(int) internal gate resistance MOSFET. external gate resistance. total gate charge side MOSFET.
PHIGH: Dissipation High Side
dissipation high side includes loss from logic circuitry loss from driving given
PHIGH PLDD (int)
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IRS20954S
Where PLDD dissipation from internal logic circuitry. dissipation from gate drive stage equivalent output impedance typically IRS20954. Rg(int) internal gate resistance high side MOSFET. external gate resistance. total gate charge high side MOSFET. Then, total dissipation given
PMID PLOW PHIGH
Estimated from thermal resistance between ambient junction temperature, RthJA;
RthJA 150°C
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IRS20954S
Case Outline
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5W-1982 CONTROLLING DIMENSION. MILLIMETER DIMENSIONS SHOWN MILLIMETER [INCHES] OUTLINE CONFORMS JEDEC OUTLINE MS-012AC DIMENSION LENGTH LEAD SOLDERING SUBSTRATE DIMENSION DOES INCLUDE MOLD PROTUSIONS. MOLD PROTUSIONS SHALL EXCEED 0.15 [.006] 16-Lead SOIC (narrow body)
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IRS20954S
LOADED TAPE FEED DIRECTION
CONTROLLING ENSION
CARRIER TAPE DIMENSION Metric Code 7.90 8.10 3.90 4.10 15.70 16.30 7.40 7.60 6.40 6.60 10.20 10.40 1.50 1.50 1.60
16SOICN Imperial 0.311 0.318 0.153 0.161 0.618 0.641 0.291 0.299 0.252 0.260 0.402 0.409 0.059 0.059 0.062
REEL DIMENSIONS 16SOICN Metric Imperial Code 329.60 330.25 12.976 13.001 20.95 21.45 0.824 0.844 12.80 13.20 0.503 0.519 1.95 2.45 0.767 0.096 98.00 102.00 3.858 4.015 22.40 0.881 18.50 21.10 0.728 0.830 16.40 18.40 0.645 0.724
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IRS20954S
LEAD-FREE PART MARKING INFORMATION
Part number Date code
IRSxxxxx YWW?
logo
Identifier
MARKING CODE Lead Free Released Non-Lead Free Relased
?XXXX
Code (Prod mode digit code)
Assembly site code SCOP 200-002
ORDER INFORMATION
16-Lead SOIC IRS20954SPbF 16-Lead SOIC Tape Reel IRS20954STRPbF
SO-16 package MSL3 qualified. This product been designed qualified industrial level. Qualification standards found www.irf.com WORLD HEADQUARTERS: Kansas St., Segundo, California 90245 Tel: (310) 252-7105 Data specifications subject change without notice. 12/3/2006
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IRS20954S Protected Digital Audio Driver Floating input enab

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