EOREX Memory EDO/FPM D-RAMBUS DDRSDRAM DDRSGRAM SGRAM SDRAM

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EOREX Memory EDO/FPM D-RAMBUS DDRSDRAM DDRSGRAM SGRAM SDRAM

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64Mb SDRAM
EOREX Memory
EDO/FPM D-RAMBUS DDRSDRAM DDRSGRAM SGRAM SDRAM
Power Blank Standard power Industrial free package
Density Mega Bits Mega Bits Mega Bits Mega Bits Mega Organization Refresh :16K
Cycle Time Freq.) 200MHz 167MHz 143MHz 7.5ns 133MHz 125MHz 10ns 100MHz
Bank 2Bank 16Bank 4Bank 32Bank 8Bank
Revision :4th
Interface 3.3V 2.5V
Package uBGA TSOP TQFP PQFP
Rev.02
1/18
64Mb SDRAM
64Mb 4Banks Synchronous DRAM
EM484M1644VTA (4Mx16)
Description
EM484M1644VTA, Synchronous Dynamic Random Access Memory (SDRAM) organized 1,048,576 words banks bits. inputs outputs synchronized with positive edge clock. 64Mb SDRAM uses synchronized pipelined architecture achieve high speed data transfer rates designed operate 3.3V power memory system. also provides auto refresh with power saving down mode. inputs outputs voltage levels compatible with LVTTL
Feature
Fully Single
synchronous positive clock edge 3.3V 0.3V power supply LVTTL compatible with multiplexed address Programmable Burst Length 1,2,4,8 full page Programmable Latency Data Mask (DQM) Read Write masking Programmable wrap sequence Sequential 1/2/4/8/full page Interleave 1/2/4/8 Burst read with single-bit write operation inputs sampled rising edge system clock. Auto refresh self refresh 4,096 refresh cycles 64ms
EOREX reserves right change products specification without notice.
Rev.02
2/18
64Mb SDRAM
Assignment View
VDDQ VSSQ VDDQ VSSQ LDQM /CAS /RAS A10/AP DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 VDDQ UDQM
54pin TSOP-II (400mil 875mil) (0.8mm pitch)
Rev.02
3/18
64Mb SDRAM
Descriptions Simplified
Name
System Clock Chip select Clock Enable
Function
Master Clock Input(Active Positive rising edge) Selects chip when active Activates when deactivates when "L". should enabled least cycle prior command. Disable input buffers power down standby. address A11) determined level bank active command cycle rising edge. CA(CA0 CA7) determined level read write command cycle rising edge. this column address becomes burst access start address. defines pre-charge mode. When High pre-charge command cycle, banks pre-charged. when pre-charge command cycle, only bank that selected BA0/BA1 pre-charged.
Address
BA0,
Bank Address
Selects which bank active.
/RAS
address strobe
Latches Addresses positive rising edge with /RAS "L". Enables access pre-charge. Latches Column Addresses positive rising edge with /CAS low. Enables column access. Latches Column Addresses positive rising edge with /CAS low. Enables column access.
/CAS
Column address strobe
Write Enable
UDQM /LDQM
Data input/output Mask
controls buffers.
Data input/output
pins have same function pins conventional DRAM.
VDD/VSS VDDQ/VSSQ
Power supply/Ground Power supply/Ground connection
power supply pins internal circuits. VDDQ VSSQ power supply pins output buffers. This recommended left Connection device.
Rev.02
4/18
64Mb SDRAM
Block Diagram
Add. Buffer
Auto/Self Refresh Counter
Address Register
Decoder
Memory Array
Write Control
Data gating Col. Decoder Data
Col. Add. Buffer
Read Control
Mode Register
Col. Add. Counter Burst Counter
Timing Register
/RAS
/CAS
Rev.02
5/18
64Mb SDRAM
Simplified State Diagram
Self Refresh
Mode Register
IDLE
Refresh
Write
Active
Power Down
Read
Active Power Down
WRITE Suspend
WRITE
Read
READ
Write
READ Suspend
WRITEA Suspend
WRITEA
READA
READA Suspend
POWER
Precharge
Precharge
Manual Input Automatic Sequence
Rev.02
6/18
64Mb SDRAM
Address Input Mode Register
Operation Mode
Latency
Burst Length
Sequential Reserved Reserved Reserved Full Page
Burst Length Interleave Reserved Reserved Reserved Reserved
Burst Type Interleave Sequential
Latency Reserved Reserved Reserved Reserved Reserved Reserved
Operation Mode Normal Burst read with Single-bit Write
Rev.02
7/18
64Mb SDRAM
Burst Type
Burst Length Sequential Addressing 0123 1230 2301 3012 01234567 12345670 23456701 34567012 45670123 56701234 67012345 70123456 Cn+1 Cn+2 Interleave Addressing 0123 1032 2301 3210 01234567 10325476 23016745 32107654 45670123 54761032 67452301 76543210
Full Page
Page length function organization column addressing (CA0 CA7) Full page bits
Rev.02
8/18
64Mb SDRAM
Truth Table
Command Truth Table
Command
Ignore Command operation Burst stop Read Read with auto pre-charge Write Write with auto pre-charge Bank activate Pre-charge select bank Pre-charge banks Mode register
Symbol
DESL BSTH READ READA WRIT WRITA PALL
/RAS /CAS
BA0,
A11, A9~A0
Note High level, level, High level (Don't care), Valid data input
Truth Table
Command
Data rite output enable Data mask output disable Upper byte rite enable output enable Read Read auto pre-charge Write Write auto pre-charge Bank activate Pre-charge select bank Pre-charge banks Mode register
Symbol
MASK BSTH READ READA WRIT WRITA PALL
Note High level, level, High level (Don't care), Valid data input
Truth Table
Command
Activating Clock suspend Idle Idle Self refresh Idle Power down
Command
Clock suspend mode entry Clock suspend mode Clock suspend mode exit refresh command Self refresh entry Self refresh exit entry exit
Symbol
/RAS /CAS
Addr.
SELF
High level, level, High level (Don't care)
Rev.02
9/18
64Mb SDRAM
Operative Command Table
Current state
Idle active Write
Addr.
BA/CA/A10 BA/CA/A10 BA/RA Op-Code BA/CA/A10 BA/CA/A10 BA/RA Op-Code BA/CA/A10 BA/CA/A10 BA/RA BA/A10 Op-Code BA/CA/A10 BA/CA/A10 BA/RA BA/A10 Op-Code
Command
DESL READ/READA WRIT/WRITA PRE/PALL REF/SELF DESL READ/READA WRIT/WRITA PRE/PALL REF/SELF DESL READ/READA WRIT/WRITA PRE/PALL REF/SELF DESL READ/READA WRIT/WRITA PRE/PALL REF/SELF ILLEGAL ILLEGAL activating
Action
Notes
Refresh self refresh Mode register accessing Begin read Determine Begin rite Determine ILLEGAL Precharge ILLEGAL ILLEGAL Continue burst active Continue burst active Burst stop active Terminate burst, read Determine Terminate burst, start rite Determine ILLEGAL Terminate burst, pre-charging ILLEGAL ILLEGAL Continue burst Write recovering Continue burst Write recovering Burst stop active Terminate burst, start read Determine Terminate burst, rite Determine ILLEGAL Terminate burst, pre-charging ILLEGAL ILLEGAL
High level, level, High level (Don't care)
Rev.02
10/18
64Mb SDRAM
Current state
Addr.
BA/CA/A10 BA/CA/A10 BA/RA Op-Code BA/CA/A10 BA/CA/A10 BA/RA Op-Code BA/CA/A10 BA/CA/A10 BA/RA Op-Code BA/CA/A10 BA/CA/A10 BA/RA Op-Code
Command
DESL READ/READA WRIT/WRITA PRE/PALL REF/SELF DESL READ/READA WRIT/WRITA PRE/PALL REF/SELF DESL READ/READA WRIT/WRITA PRE/PALL REF/SELF DESL READ/READA WRIT/WRITA PRE/PALL REF/SELF
Action
Continue burst Precharging Continue burst Precharging ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL burst Write recovering auto precharge Continue burst Write recovering auto precharge ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Enter idle Enter idle ILLEGAL ILLEGAL ILLEGAL ILLEGAL Enter idle ILLEGAL ILLEGAL Enter idle tRCD Enter idle tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Notes
Write
Precharging
3,10
activating
High level, level, High level (Don't care), Auto Precharge
Rev.02
11/18
64Mb SDRAM
Current state
Addr.
BA/CA/A10 BA/CA/A10 BA/RA Op-Code BA/CA/A10 BA/CA/A10 BA/RA Op-Code
Command
DESL READ/READA WRIT/WRITA PRE/PALL REF/SELF DESL READ/READA WRIT/WRITA PRE/PALL REF/SELF DESL NOP/ READ/WRIT ACT/PRE/PALL REF/SELF/MRS DESL READ/WRIT ACT/PRE/PALL/ REF/SELF/MRS
Action
Enter active tDPL Enter active tDPL Enter active tDPL Start read, Determine rite, Determine ILLEGAL ILLEGAL ILLEGAL ILLEGAL Enter precharge tDPL Enter precharge tDPL Enter precharge tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Enter idle after Enter idle after ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Notes
Write cove ring
Write cove ring
shing
giste Acces sing
High level, level, High level (Don't care), Auto Precharge
Notes entries assume that active (High level) during preceding clock cycle. banks idle, inactive (Low level), SDRAM enter mode. input buffers except disabled. Illegal bank specified states; Function legal bank indicated Bank Address (BA), depending state that bank. banks idle, inactive (Low level), SDRAM enter Self refresh mode. input buffers except disabled. Illegal tRCD satisfied. Illegal tRAS satisfied. Must satisfy burst interrupt condition. Must satisfy contention, turn around, and/or rite recovery requirements. Must mask preceding data hich don't satisfy tDPL. Illegal tRRD satisfied.
Rev.02
12/18
64Mb SDRAM
Command Truth Table
Current state
cove Both banks idle active state other than liste above
Addr.
Action
INVALID, ould exit self refresh Self refresh recovery Self refresh recovery ILLEGAL ILLEGAL Maintain self refresh Idle after Idle after ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL INVALID, CLK(n-1) ould exit Exit Idle Maintain mode Refer operations Operative Command Table Refer operations Operative Command Table Refer operations Operative Command Table
Notes
Op-Code
Refresh Refer operations Operative Command Table Refer operations Operative Command Table Refer operations Operative Command Table Refer operations Operative Command Table
Op-Code
Self refresh Refer operations Operative Command Table Refer operations Operative Command Table Refer operations Operative Command Table Begin clock suspend next cycle Exit clock suspend next cycle Maintain clock suspend
High level, level, High level (Don't care) Notes Self refresh entered only from both banks idle state. entered only from both banks idle active state. Must legal command defined Operative Command Table.
Rev.02
13/18
64Mb SDRAM
Absolute Maximum Ratings
Symbol
VIN, VOUT VDD, VDDQ TSTG
Item
Input, Output Voltage Power Supply Voltage Operating Temperature Storage Temperature Power Dissipation Short Circuit Current
Rating
-0.3 -0.3
Units
Note Caution Exposing device stress above those listed Absolute Maximum Ratings could cause permanent damage. device meant operated under conditions outside limits described operational section this specification. Exposure Absolute Maximum Rating conditions extended periods affect device reliability.
Recommended Operation Conditions
Symbol
VDDQ
Parameter
Power Supply Voltage Power Supply Voltage (for Buffer) Input logic high voltage Input logic voltage
Min.
-0.3
Typical
Max.
VDD+0.3
Units
Note voltage referred (max) 5.6V pulse idth (min) -2.0V pulse idth
Capacitance =3.3V, 1MHz,
Symbol
CCLK
Parameter
Clock capacitance Input capacitance CLK, CKE, Address, /CS, /RAS, /CAS, /WE, DQML,DQMU Input/Output capacitance
Min.
Max.
Units
Rev.02
14/18
64Mb SDRAM
Recommended Operating Conditions 3.3V 6I/7I)
Parameter Symbol Test condition
Burst length (min), bank active (max.), (max.), (min.), (min.) Input signals changed time during 30ns (min.), Input signals stable
Units Notes -6/6I
-7/7L/7I
Operating current Precharge standby current power down mode
ICC1
ICC2P ICC2PS ICC2N
Precharge standby current non-power down mode
ICC2NS ICC3P ICC3PS ICC3N
Active standby current power down mode
VIL(max), 15ns VIL(max), VIL(min), 15ns,/ VIH(min) Input signals changed time during 30ns VIL(min), Input signals stable tCCD 2CLKs tRC(min.) 0.2V CL=3 CL=2
Active standby current non-power down mode
ICC3NS
operating current (Burst mode) Refresh current Self Refresh current
ICC4 ICC5 ICC6
Note ICC1 depends output loading cycle rates. Specified values obtained output open. Input signals changed only time during tCK(min) ICC4 depends output loading cycle rates. Specified values obtained output open. Input signals changed only time during tCK(min) Input signals changed only time during tCK(min) Standard version. version.
Rev.02
15/18
64Mb SDRAM
Recommended Operating Conditions Continued
Parameter Symbol Test condition Min. Max. Unit
Input leakage current
VDDQ, VDDQ=VDD other pins under test=0
-0.5
+0.5
Output leakage current High level output voltage level output voltage
VDDQ, DOUT disabled -4mA +4mA
-0.5
+0.5
Operating Test Conditions
3.3V 70°C
Output Reference Level Output Load Input Signal Level Transition Time Input Signals Input Reference Level
1.4V 1.4V diagram below 2.4V 0.4V 1.4V
1.4V
Output
50pF
Rev.02
16/18
64Mb SDRAM
Operating Characteristics
3.3V 6I/7I)
Min.
Data-out hold time Data-out high impedance time Data-out impedance time Input hold time Input setup time ACTIVE ACTIVE command period ACTIVE PRECHARGE command period PRECHARGE ACTIVE command period ACTIVE READ/WRITE delay time ACTIVE(one) ACTIVE(another) command READ/WRITE command READ/WRITE command Data-in PRECHARGE command Data-in BURST stop command Data-out high impedance from PRECHARGE command Refresh time(4,096 cycle) voltages referenced Vss. Note defines time which output achieve open circuit condition referenced output voltage levels. These parameters account number clock cycles depend operating frequency clock, follows number clock cycles Specified value timing/clock period (Count fractions whole number) tREF tRAS tRCD tRRD tCCD tBDL tROH 100k 100k 100k
Parameter
Clock cycle time Access time from high level width level width
Symbol
-6/6I
Min. Max.
-7/7L/7I
Min. Max.
Max.
Units Notes
Rev.02
17/18
64Mb SDRAM
Package Dimension
Rev.02
18/18

EOREX Memory EDO/FPM D-RAMBUS DDRSDRAM DDRSGRAM SGRAM SDRAM

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