EOREX Logo EDO/FPM D-RAMBUS DDRSDRAM DDRSGRAM SGRAM SDRAM fr

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

EOREX Logo EDO/FPM D-RAMBUS DDRSDRAM DDRSGRAM SGRAM SDRAM fr

Datasheet Thumbnail

Top Searches for this datasheet

64Mb SDRAM
EOREX Logo
EDO/FPM D-RAMBUS DDRSDRAM DDRSGRAM SGRAM SDRAM
free package Power Blank Standard power Industrial
Density Mega Bits Mega Bits Mega Bits Mega Bits Mega Organization Refresh :16K Bank 2Bank 16Bank 4Bank 32Bank 8Bank
Cycle Time Freq.) 200MHz 167MHz 143MHz 7.5ns 133MHz 125MHz 10ns 100MHz
Revision :4th version only
Interface 3.3V 2.5V
Package uBGA TSOP TQFP PQFP LQFP
URL: http://www.eorex.com Email: sales@eorex.com
Rev.01
1/33
64Mb SDRAM
64Mb( 4Banks Synchronous DRAM
EM482M3244VTA (2Mx32)
Description
EM482M3244VTA Synchronous Dynamic Random Access Memory SDRAM organized 524,288 words banks bits. inputs outputs synchronized with positive edge clock 64Mb SDRAM uses synchronized pipelined architecture achieve high speed data transfer rates designed operate 3.3V power memory system. also provides auto refresh with power saving down mode. inputs outputs voltage levels compatible with LVTTL
Features
Fully synchronous positive clock edge Single 3.3V 0.3V power supply LVTTL compatible with multiplexed address Programmable Burst Length 1,2,4,8 full page Programmable Latency Data Mask Read/Write masking Programmable wrap sequential Sequential 1/2/4/8/full page Interleave 1/2/4/8 Burst read with single-bit write operation inputs sampled positive rising edge system clock. Auto refresh self refresh 4,096 refresh cycles 64ms
EOREX reserves right change products specification without notice.
Rev.01
2/33
64Mb SDRAM
Assignment View
VDDQ VSSQ VDDQ VSSQ DQM0 /CAS /RAS A10/AP DQM2 DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23
DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 VDDQ DQM1 DQM3 DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24
86pin TSOP-II (400mil mil) (0.5mm pitch)
Rev.01
3/33
64Mb SDRAM
Descriptions Simplified
Name
System Clock Chip select Clock Enable
Function
Master Clock Input(Active Positive rising edge) Selects chip when active Activates when deactivates when "L". should enabled least cycle prior command. Disable input buffers power down standby. address A10) determined level bank active command cycle rising edge. CA(CA0 CA7) determined level read write command cycle rising edge. this column address becomes burst access start address. defines pre-charge mode. When High pre-charge command cycle, banks pre-charged. when pre-charge command cycle, only bank that selected pre-charged. Selects which bank active.
Address
BA0~BA1
Bank Address
/RAS
address strobe
Latches Addresses positive rising edge with /RAS "L". Enables access pre-charge. Latches Column Addresses positive rising edge with /CAS low. Enables column access. Latches Column Addresses positive rising edge with /CAS low. Enables column access.
/CAS
Column address strobe
Write Enable
DQM0 DQM3
Data input/output Mask
controls buffers.
Data input/output
pins have same function pins conventional DRAM.
VDD/VSS VDDQ/VSSQ
Power supply/Ground Power supply/Ground connection
power supply pins internal circuits. VDDQ VSSQ power supply pins output buffers. This recommended left Connection device.
Rev.01
4/33
64Mb SDRAM
Block Diagram
Add. Buffer
Auto/Self Refresh Counter
Decoder
Address Register
Memory Array
Write Control
Data gating Col. Decoder Data
Col. Add. Buffer
Read Control
Mode Register
Col. Add. Counter Burst Counter
Timing Register
/CLK
/RAS
/CAS
Rev.01
5/33
64Mb SDRAM
Commands
Mode register command /CS, /RAS, CAS,
/RAS /CAS
EM482M3244VTA have mode register that defines device operates. this command, through data input pins. After power mode register command must executed initialize device. mode register only when banks idle state. EO482M3244VTA, cannot accept other commands,only during 2CLK following this command.
Figure. Mode register command
Active command /CS, /RAS /CAS, High
/RAS /CAS
EM482M3244VTA have banks, each with 2,048 rows. This command activates bank selected address selected through A10.This command corresponds conventional DRAM's /RAS falling.
Figure. address strobe bank activate command
Rev.01
6/33
64Mb SDRAM
Precharge command /CS, /RAS, High
/RAS /CAS
This command begins precharge operation bank selected When high,all banks precharged, regardless When low,only bank selected precharged.
Figure. Precharged command
Write command /CS, /CAS, Low, /RAS High
/RAS /CAS
Column
mode register burst write mode, this command sets burst start address given column address begin burst write operation. first write data burst mode input with this command with subsequent data following clicks.
Figure. Column address write command
Rev.01
7/33
64Mb SDRAM
Read command /CS, /CAS RAS, High
/RAS /CAS
Column
Raed data available after /CAS latency requirements have been met. This command sets burst start address given column.
Figure. Column address read command
Auto refresh command /CS, /RAS, /CAS Low, /WE, High
/RAS /CAS
This command request begin refresh operation. refresh address generated internally. Before Executing refresh, banks must precharged. After this cycle, banks will idle (Precharged state ready activate command. During period from refresh command refresh activate command EM482M3244VTA cannot accept other command.
Figure. Auto refresh command
Rev.01
8/33
64Mb SDRAM
Self refresh entry command /CS, /CAS, High
/RAS /CAS
After command execution, self refresh operation continues while remains low. When goes high, memory exits self refresh mode. During self refresh mode, refresh interval refresh operation performed internally, there before need external control. Before executing self refresh, both banks must precharged.
Figure. Self refresh entry command
Burst stop command /CS, Low, /RAS, /CAS High
/RAS /CAS
This command stop current burst operation.
Figure. Burst stop command full page mode
Rev.01
9/33
64Mb SDRAM
operation Low, /CAS, High
/RAS /CAS
This command execution command there operations begin terminate this command.
Figure. operation
Initialization
synchronous DRAM initialized power-on sequence according following: stabilize internal circuits, when power applied, 100us longer pause must precede signal toggling. After pause, both banks must precharged using precharged command precharge banks command convenient Once precharge completed minimum satisfied, mode register programmed. more Arto refresh must performed.
Remanks: sequence Mode register programming Refresh above transposed. must held high until precharge command issued ensure data-bus Hi-Z.
Rev.01
10/33
64Mb SDRAM
Programming Mode Register
mode register programmed Mode register command using address bits through data inputs. register retains data until reprogrammed device loses power.
Options
through
/CAS Latency
through
Wrap type
Burst Length
through
Following mode register programming, command issued before least elapsed.
/CAS Latency
/CAS Latency most critical parameters begin set. tells device many clocks must elapse before data will available.
Burst Length
Burst length number words that will output input write cycle. After read burst completed, output will become Hi-Z. burst length programmable 1,2,4,8 full page.
Wrap Type Burst Sequence
wrap type specifies order which burst data will addressed. This order programmable either Sequence Interleave. method chosen will depend type system. Some microprocessor cache systems optimized sequential addressing others interleaved.
Rev.01
11/33
64Mb SDRAM
Simplified State Diagram
Self Refresh
Mode Register
IDLE
Refresh
Write
Active
Power Down
Read
Active Power Down
WRITE Suspend
WRITE
Read
READ
Write
READ Suspend
WRITEA Suspend
WRITEA
READA
READA Suspend
POWER
Precharge
Precharge
Manual Input Automatic Sequence
Rev.01
12/33
64Mb SDRAM
Address Input Mode Register
BA0/1
Operation Mode
Latency
Burst Length
Sequential Reserved Reserved Reserved Full Page
Burst Length Interleave Reserved Reserved Reserved Reserved
Burst Type Sequential Interleave
Latency Reserved Reserved Reserved Reserved Reserved
BA0/1
Operation Mode Normal Burst read with Single-bit Write
Rev.01
13/33
64Mb SDRAM
Burst Type
Burst Length
Full Page
Sequential Addressing 0123 1230 2301 3012 01234567 12345670 23456701 34567012 45670123 56701234 67012345 70123456 Cn+1 Cn+2
Interleave Addressing 0123 1032 2301 3210 01234567 10325476 23016745 32107654 45670123 54761032 67452301 76543210
Page length function organization column addressing (CA0 CA7) Full page bits
Rev.01
14/33
64Mb SDRAM
Precharge
precharge command issued anytime after tRAS min.) satisfied. Soon After precharge command issued, precharge operation performed synchronous DRAM enters idle state after satisfied. parameter time required perform precharge. earliest timing read cycle that precharege command issued without losing data burst follows. depends /CAS latency clock cycle time.
Command
Read
Hi-Z
Command
Read
Hi-Z
BL=4
order write data memory cell correctly, asynchronous parameter tDPL must satisfied. tDPL (min.) specification defines eariliest time that precharge command issued. Minimum number clocks calculated dividing tDPL(min.) with clock cycle time. word, precharge command issued relative reference clock that indicates last data word valid. minus following table means clocks before reference plus means time after reference.
/CAS latency
Read
Write
tDPL( min.) tDPL min.)
Rev.01
15/33
64Mb SDRAM
Auto precharge
During read write command cycle, controls whether auto precharge selected. high Read Write command Read with Auto precharge command Write with Auto precharge command auto precharge selected begins automatically. tRAS must satisfied with read with auto precharge write with auto precharge operation. addition, next activate command bank being precharged cannot executed until precharge cycle ends. read cycle, once auto precharge started activate command bank issued after been satisfied
Read with Auto Precharge
During read cycle, auto precharge begins same /CAS latency clock earlier /CAS latency last data word output.
Command
Read
Auto precharge starts
Hi-Z
Command
Read
Auto precharge starts
Hi-Z
BL=4 tRAS must satisfied
Remanks: Read means Read with auto precharge
Rev.01
16/33
64Mb SDRAM
Write with Auto Precharge
During write cycle, auto precharge starts timing that equal value tDPL( min.) after last dataword input device.
Command
Write
Auto precharge starts
tDPL( min.
Hi-Z
Command
Write
Auto precharge starts
tDPL( min.
Hi-Z
BL=4 tRAS must satisf
Remanks: Write means Write with auto precharge
summary, auto precharge begins relative reference clock that indicates last data word valid. following table minus means clocks before reference ,plus means after reference.
/CAS latency
Read
Write
tDPL( min.) tDPL min.)
Rev.01
17/33
64Mb SDRAM
Read Write command interval
Read read command interval
During read cycle, when Read command issued,it will effective after latency, even previous read operation does completed. Read will interrupted another Read. interval between commands cycle minimum. Each Read command issued every clock without restriction.
Command
Read
Read
Cycle
Hi-Z
Write write command interval
During write cycle, when write command issued, previous burst will terminate burst will begin with write command. Write will interrupted another Write. interval between commands minimum cycle. Each write command issued every clock without restriction.
Command
Write
Write
Hi-Z
Cycle
Rev.01
18/33
64Mb SDRAM
Write read command interval
Write Read command interval also cycle. Only write data before read command will written. data must Hi-Z least cycle prior first OUT.
Command
Write
Read
Hi-Z
Command
Write
Read
Hi-Z
BL=4
Rev.01
19/33
64Mb SDRAM
Read write command interval
During read cycle, Read interrupt Write. read write command interval cycle minimum. There's restriction avoid data conflict. data must Hi-Z using before write.
Command
Read
Write
Hi-Z
BL=4
Read interrupted Write. must high least clicks prior write command.
Command
Read
Write
Hi-Z necessar
Command
Read
Write
Hi-Z necessar
BL=8
Rev.01
20/33
64Mb SDRAM
Burst terminate
There ways terminate burst operation other than using Read Write command. burst stop command other precharge command.
Burst stop command
During read cycle,when burst stop command issued, burst read terminated data goes Hi-Z after /CAS latency from burst stop command.
Command
Burst Stop
Read
Hi-Z
Hi-Z
don't care
During write cycle,when burst stop command issued, burst write data terminated data goes Hi-Z same clock with burst stop command.
Command
Burst Stop
Write
Hi-Z
don't care
Rev.01
21/33
64Mb SDRAM
Precharge Termination
Precharge Termination READ Cycle During read cycle, burst read operation terminated precharge command. When precharge command issued, burst read operation terminated precharge starts. same banks activated again after from precharge command. issue precharge command tRAS must satisfied. When /CAS Latency read data will remain valid until clocks after precharge command.
Precharge
Command
Read
Activ
Hi-Z
don't care
When /CAS Latency read data will remain valid until clocks after precharge command.
Command
Precharge
Read
Activ
Hi-Z
don't care
Rev.01
22/33
64Mb SDRAM
Precharge Termination Write Cycle During write cycle, burst write operation terminated precharge command. When precharge command issued, burst write operation terminated precharge starts. same banks activated again after from precharge command. issue precharge command tRAS must satisfied. When /CAS Latency write data written prior precharge command will correctly stored. However, invalid data written same clock precharge command. order avoid this situation, must high same clock precharge command. This will mask invalid data.
Precharge
Command
Write
Activ
Hi-Z
don't care, tRAS must satisfied
When /CAS Latency write data written prior precharge command will correctly stored. However, invalid data written same clock precharge command. order avoid this situation, must high same clock precharge command. This will mask invalid data.
Precharge
Command
Write
Activ
Hi-Z
=don't care tRAS must satisf
Rev.01
23/33
64Mb SDRAM
Truth Table
Command Truth Table EM482M3244VTA
Command
Ignore Command operation Burst stop Read Read with auto pre-charge Write Write with auto pre-charge Bank activate Pre-charge select bank Pre-charge banks Mode register
Symbol
DESL BSTH READ READA WRIT WRITA PALL
/RAS /CAS
A9~A0
Note High level, level, High level (Don't care), Valid data input
Truth Table
Command
Data rite output enable Data mask output disable Upper byte rite enable output enable Read Read auto pre-charge Write Write auto pre-charge Bank activate Pre-charge select bank Pre-charge banks Mode register
Symbol
MASK BSTH READ READA WRIT WRITA PALL
Note High level, level, High level (Don't care), Valid data input
Truth Table
Command
Activating Clock suspend Idle Idle Self refresh Idle Power down
Command
Clock suspend mode entry Clock suspend mode Clock suspend mode exit refresh command Self refresh entry Self refresh exit entry exit
Symbol
/RAS /CAS Addr.
SELF
High level, level, High level (Don't care)
Rev.01
24/33
64Mb SDRAM
Operative Command Table
Current state
Idle active Read Write
Addr.
BA/CA/A10 BA/CA/A10 BA/RA Op-Code BA/CA/A10 BA/CA/A10 BA/RA Op-Code BA/CA/A10 BA/CA/A10 BA/RA BA/A10 Op-Code BA/CA/A10 BA/CA/A10 BA/RA BA/A10 Op-Code
Command
DESL READ/READA WRIT/WRITA PRE/PALL REF/SELF DESL READ/READA WRIT/WRITA PRE/PALL REF/SELF DESL READ/READA WRIT/WRITA PRE/PALL REF/SELF DESL READ/READA WRIT/WRITA PRE/PALL REF/SELF
Action
ILLEGAL ILLEGAL activating resh self refresh Mode register accessing Begin read Determine Begin rite Determine ILLEGAL Precharge ILLEGAL ILLEGAL Continue burst active Continue burst active Burst stop active Terminate burst, read Determine Terminate burst, start rite Determine ILLEGAL Terminate burst, pre-charging ILLEGAL ILLEGAL Continue burst Write recovering Continue burst Write recovering Burst stop active Terminate burst, start read Determine Terminate burst, rite Determine ILLEGAL Terminate burst, pre-charging ILLEGAL ILLEGAL
Notes
High level, level, High level (Don't care)
Rev.01
25/33
64Mb SDRAM
Current state
Addr.
BA/CA/A10 BA/CA/A10 BA/RA Op-Code BA/CA/A10 BA/CA/A10 BA/RA Op-Code BA/CA/A10 BA/CA/A10 BA/RA Op-Code BA/CA/A10 BA/CA/A10 BA/RA Op-Code
Command
DESL READ/READA WRIT/WRITA PRE/PALL REF/SELF DESL READ/READA WRIT/WRITA PRE/PALL REF/SELF DESL READ/READA WRIT/WRITA PRE/PALL REF/SELF DESL READ/READA WRIT/WRITA PRE/PALL REF/SELF
Action
Continue burst Precharging Continue burst Precharging ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL burst Write recovering auto precharge Continue burst Write recovering auto precharge ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Enter idle Enter idle ILLEGAL ILLEGAL ILLEGAL ILLEGAL Enter idle ILLEGAL ILLEGAL Enter idle tRCD Enter idle tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Notes
Read
Write
charging
3,10
activating
High level, level, High level (Don't care), Auto Precharge
Rev.01
26/33
64Mb SDRAM
Current state
Addr.
BA/CA/A10 BA/CA/A10 BA/RA Op-Code BA/CA/A10 BA/CA/A10 BA/RA Op-Code
Command
DESL READ/READA WRIT/WRITA PRE/PALL REF/SELF DESL READ/READA WRIT/WRITA PRE/PALL REF/SELF DESL NOP/ READ/WRIT ACT/PRE/PALL REF/SELF/MRS DESL READ/WRIT ACT/PRE/PALL/ REF/SELF/MRS
Action
Enter active tDPL Enter active tDPL Enter active tDPL Start read, Determine rite, Determine ILLEGAL ILLEGAL ILLEGAL ILLEGAL Enter precharge tDPL Enter precharge tDPL Enter precharge tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Enter idle after Enter idle after ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Notes
Write recovering
Write recovering
Refres hing
Regis Acces
High level, level, High level (Don't care), Auto Precharge
Notes entries assume that active (High level) during preceding clock cycle. banks idle, inactive (Low level), SDRAM enter mode. input fers except disabled. Illegal bank specified states; Function legal bank indicated Bank Address (BA0/1), depending state that bank. banks idle, inactive (Low level), SDRAM enter Self refresh mode. input fers except disabled. Illegal tRCD satisfied. Illegal tRAS satisfied. Must satisfy burst interrupt condition. Must satisfy contention, turn around, and/or rite recovery requirements. Must mask preceding data hich don't satisfy tDPL. Illegal tRRD satisfied.
Rev.01
27/33
64Mb SDRAM
Command Truth Table
Current state
Self fres Self fres covery Both bank idle active tate other than above
Addr.
Action
INVALID, ould exit self refresh Self refresh recovery Self refresh recovery ILLEGAL ILLEGAL Maintain self refresh Idle after Idle after ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL INVALID, CLK(n-1) ould exit Exit Idle Maintain mode Refer operations Operative Command Table Refer operations Operative Command Table Refer operations Operative Command Table
Notes
Op-Code
Refresh Refer operations Operative Command Table Refer operations Operative Command Table Refer operations Operative Command Table Refer operations Operative Command Table
Op-Code
Self refresh Refer operations Operative Command Table Refer operations Operative Command Table Refer operations Operative Command Table Begin clock suspend next cycle Exit clock suspend next cycle Maintain clock suspend
High level, level, High level (Don't care) Notes Self refresh entered only from both banks idle state. entered only from both banks idle active state. Must legal command defined Operative Command Table.
Rev.01
28/33
64Mb SDRAM
Absolute Maximum Ratings
Symbol
VIN, VOUT VDD, VDDQ TSTG
Item
Input, Output Voltage Power Supply Voltage Operating Temperature Storage Temperature Power Dissipation Short Circuit Current
Rating
-0.3 -0.3
Units
Note Caution Exposing device stress above those listed Absolute Maximum Ratings could cause permanent damage. device meant operated under conditions outside limits described operational section this specification. Exposure Absolute Maximum Rating conditions extended periods affect device reliability.
Recommended Operation Conditions 70°C)
Symbol
VDDQ
Parameter
Power Supply Voltage Power Supply Voltage (for Buffer) Input logic high voltage Input logic voltage
Min.
-0.3
Typical
Max.
VDD+0.3
Units
Note voltage referred (max) 5.6V pulse idth (min) -2.0V pulse idth
Capacitance =3.3V, 25°C
Symbol
CCLK
Parameter
Clock capacitance Input capacitance CLK, CKE, Address, /CS, /RAS, /CAS, /WE, DQM0 Input/Output capacitance
Min.
Max.
Units
Rev.01
29/33
64Mb SDRAM
Recommended Operating Conditions
3.3V 85°C
Parameter Symbol Test condition
Burst length (min), bank active (max.), (max.), (min.), (min.)Input signals changed time during 30ns (min.), Input signals stable IL(max), 15ns IL(max), IL(min), 15ns, IH(min) Input signals changed time during 30ns IL(min), Input signals stable
Units Notes -6/6I CL=2
CL=3
Operating current
ICC1
Precharge standby ICC2P current power down ICC2PS mode ICC2N
Precharge standby current non-power down mode
ICC2NS ICC3P ICC3PS
Active standby current power down mode
ICC3N Active standby current non-power down mode ICC3NS operating current (Burst mode) Refresh current Self Refresh current
CL=3 CL=2
ICC4 ICC5 ICC6
tCCD 2CLKs tRC(min.) 0.2V
Note ICC1 depends output loading cycle rates. Specified values obtained output open. Input signals changed only time during tCK(min) ICC4 depends output loading cycle rates. Specified values obtained output open. Input signals changed only time during tCK(min) Input signals changed only time during tCK(min) Standard version. version.
Rev.01
30/33
64Mb SDRAM
Recommended Operating Conditions Continued
Parameter Symbol Test condition Min. Max. Unit
Input leakage current
VDDQ, VDDQ=VDD other pins under test=0 VDDQ, DOUT disabled -4mA +4mA
-0.5
+0.5
Output leakage current High level output voltage level output voltage
-0.5
+0.5
Operating Test Conditions
3.3V 70°C
Output Reference Level Output Load Input Signal Level Transition Time Input Signals Input Reference Level 1.4V 1.4V diagram below 2.4V 0.4V 1.4V
1.4V Output
50pF
Rev.01
31/33
64Mb SDRAM
Operating Characteristics
3.3V 70°C, 85°C
Parameter
tRAS tRCD tRRD tCCD tDPL tBDL tROH tREF 100k 100k 100k 100k
Symbol
-6/6I
Min. Max. Min. Max. Min. Max. Min. Max.
1000 1000 1000 1000 1000 1000 1000
Units Notes
Clock cycle time
Access time from high level width level width Data-out hold time
Data-out high impedance time Data-out impedance time Input hold time Input setup time
ACTIVE ACTIVE command period ACTIVE PRECHARGE command period PRECHARGE ACTIVE command period ACTIVE READ/WRITE delay time ACTIVE(one) ACTIVE(another) command READ/WRITE command READ/WRITE command Data-in PRECHARGE command Data-in BURST stop command Data-out high impedance from PRECHARGE command Refresh time(4,096 cycle)
Note voltages referenced Vss. defines time which output achieve open circuit condition referenced output voltage levels. These parameters account number clock cycle depend operating frequency clock, follows number clock cycles Specified value timing/clock period (Count fractions whole number)
Rev.01
32/33
64Mb SDRAM
Package Dimension
1.20 0.047 1.00+/- 0.10 0.039+/- 0.004 0.21+/- 0.05 0.008+/- 0.002 0.05 0.002 PIN1
11.76 0.20 0.463 0.008
22.62 0.891
22.22+/- 0.10 0.875+/- 0.004
0.125 +0.075 -0.035 0.005+0.003 -0.001
0.10 0.004
0.61 0.024
0.50 0.020
0.20 +0.07 -0.03 0.008+0.003 -0.001
10.16 0.400
0.50 0.020
0.45 0.75 0.018 0.030
EOREX reserves right change products specification without notice.
Rev.01
0.25 0.010
33/33

EOREX Logo EDO/FPM D-RAMBUS DDRSDRAM DDRSGRAM SGRAM SDRAM fr

Top Searches for this datasheet

Other recent searches