DS3100DK easy-to-use demo evaluation DS3100 Stratum 3/3E timing card s

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DS3100DK easy-to-use demo evaluation DS3100 Stratum 3/3E timing card s

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DS3100DK Stratum 3/E3 Timing Card Demo
DS3100DK easy-to-use demo evaluation DS3100 Stratum 3/3E timing card surface-mounted DS3100 careful layout provide maximum signal integrity. on-board Dallas 8051-compatible microcontroller included software give point-and-click access configuration status registers from personal computer. LEDs board indicate interrupt, power-supply function, GPIO status. board provides bantam connectors composite clock BITS interfaces. Single-ended LVDS clocks accessed connectors. LEDs connectors clearly labeled with silkscreening identify associated signals.
FEATURES
Soldered DS3100 Best Signal Integrity Connectors, BNC, Bantam, Transformers, Termination Ease Connectivity Careful Layout Analog Signal Paths On-Board Stratum Oscillator with Footprints Stratum Oscillators DS3100 Configured Operation Complete Control Over Device On-Board Dallas Microcontroller Included Software Provide Point-and-Click Access DS3100 Register LEDs Interrupt, Power Supplies, GPIO Included International Power Supply Banana Jack Connectors Support Power Supplies Easy-to-Read Silkscreen Labels Identify Signals Associated with Connectors, Jumpers LEDs Header Provided Master/Slave Connection Second DS3100DK Software Provides Fields Most Commonly Used Features Plus Full Read/Write Access Entire Register Software Support Creating Running Configuration Scripts Saves Time During Evaluation
DEMO CONTENTS
DS3100DK CD_ROM Includes: DS3100 Software DS3100 Initialization File DS3100DK Data Sheet DS3100 Data Sheet/Errata Sheet
MINIMUM SYSTEM REQUIREMENTS
Running Windows® Windows 2000 Display with 1024 Resolution Higher Available Serial (COM) Port DB-9 Serial Cable
ORDERING INFORMATION
PART DS3100DK DESCRIPTION Demo DS3100
Windows registered trademark Microsoft Corp.
REV: 110206
DS3100DK
TABLE CONTENTS
BOARD FLOORPLAN.4
INPUT OUTPUT CLOCKS JUMPERS, HEADERS, SWITCH SETTINGS COMPOSITE CLOCK INTERFACE BITS INTERFACES MICROCONTROLLER POWER-SUPPLY CONNECTORS.5
BASIC HARDWARE SETUP.6 INSTALLING RUNNING SOFTWARE.6
COMMAND LINE OPTIONS
OVERVIEW SOFTWARE INTERFACE.7
GLOBAL CONFIGURATION INPUT CLOCK MONITOR, DIVIDER, SELECTOR DPLL DPLL APLL. APLL. OUTPUT CLOCKS.11 DPLL FREQUENCY LIMITS, PHASE DETECTORS, DPLL LOCK CRITERIA BITS RECEIVERS BITS TRANSMITTERS
Note About Working with BITS Receivers Transmitters
4.9.1
4.10 4.11 4.12 4.13
4.13.1 4.13.2
COMPOSITE CLOCK RECEIVERS REFCLK CALIBRATION REGISTER VIEW WINDOW CONFIGURATION SCRIPTS FILE
Configuration File Configuration Scripts.
ADDITIONAL INFORMATION RESOURCES
DS3100 INFORMATION DS3100DK INFORMATION TECHNICAL SUPPORT
APPENDIX HARDWARE COMPONENTS.16 APPENDIX BITS MODE WRITE SEQUENCES.19 SCHEMATICS DOCUMENT REVISION HISTORY
DS3100DK
LIST FIGURES
Figure 1-1. Board Floorplan.
LIST TABLES
Table 4-1. Mapping Between Input Clock Software Fields DS3100 Register Fields Table 4-2. Mapping Between DPLL Software Fields DS3100 Register Fields Table 4-3. Mapping Between DPLL Software Fields DS3100 Register Fields Table 4-4. Mapping Between APLL Software Fields DS3100 Register Fields Table 4-5. Mapping Between APLL Software Fields DS3100 Register Fields Table 4-6. Mapping Between Output Clock Software Fields DS3100 Register Fields Table 4-7. Mapping Between DPLL Software Fields DS3100 Register Fields Table 4-8. Mapping Between BITS Software Fields DS3100 Register Fields Table 4-9. Mapping Between Software Fields DS3100 Register Fields Table 4-10. Mapping Between REFCLK Software Fields DS3100 Register Fields
DS3100DK
BOARD FLOORPLAN
Figure shows floorplan DS3100DK. DS3100 center board, input clock connectors along edge board, output clock connectors bottom edge. Between input clock connectors DS3100, land patterns provided several different types local oscillators, ranging from tiny, inexpensive TCXOs larger, high-performance OCXOs. right edge contains, from bottom, power supply connectors, DC-DC converters power-indicator LEDs, reset push-button, serial connector connector. on-board DS87C520 microcontroller located near connector. left edge board occupied connectors transformers DS3100's built-in BITS (DS1/E1/2048kHz) composite clock (64kHz) receivers transmitters. Between BITS composite clock connectors JTAG header three switches control DS3100's MASTSLV, SONSDH, SRCSW pins. APPENDIX HARDWARE COMPONENTS complete component list. Complete board schematics follow Appendix
Figure 1-1. Board Floorplan
Power Option Banana Jack
LVDS Input Clocks
Single-ended Input Clocks
Banana Jack
Oscillator Circuitry BITS Interfaces
DS3100 GPIO Circuitry
Reset
Power Supply Circuitry RS232 9-Pin Connector
JTAG Header
Switches
Connector
Microprocessor
Composite Clock Input Composite Clock Output
LVDS Output Clocks
Single-ended Output Clocks
DS3100DK
Input Output Clocks
There connectors board labeled IC1-IC4, IC7-IC14, SYNC2K that provide single-ended clock input DS3100. single-ended clock inputs connected DS3100 with characteristic impedance trace terminated with device. Four additional connectors labeled IC5P, IC5N, IC6P, IC6N provide differential clock inputs DS3100. These differential inputs have trace impedance termination device (i.e., differential). other eight clock output connectors labeled OC1-OC5 OC9, OC10, OC11. single-ended clock outputs buffered DS3100 connected connector characteristic impedance trace. Four additional connectors labeled OC6P, OC6N, OC7P, OC7N provide connections differential outputs from DS3100.
Jumpers, Headers, Switch Settings
Jumpers JMP1 JMP4 (upper right board) provide input settings four DS3100 GPIO pins. jumper installed corresponding GPIO input high. With jumper GPIO defaults low. LEDs DS5-DS8 indicate logic level GPIO pins (LED means GPIO high). Switches SONSDH, SRCSW MASTSLV pins, respectively, high indicated silkscreen. Headers provide access BITS1 BITS2 framer signals, respectively. Header provides access JTAG port DS3100. Header provides interface master slave board depending position switch SW6.
Composite Clock Interface
Bantam jacks provide access composite clock inputs IC1A IC2A through transformer. Jumpers JMP7 JMP6 configure termination IC1A IC2A respectively. Silkscreen text indicates which jumper necessary interface 110, 120, 133. Bantam jack J117 provides interface through transformer composite clock output. Jumpers JMP8, JMP9, JMP10 provide different attenuation configurations that represented silkscreen with jumper installed). schematics additional details composite clock termination circuitry.
BITS Interfaces
BITS1 DS1/E1 uses bantam connectors connectors transmit receive interfaces, respectively. BITS2 uses bantam connectors connectors transmit receive, respectively. There dual transformer package each BITS transceiver (component BITS1 BITS2). schematics additional details BITS termination circuitry.
Microcontroller
DS87C520 microcontroller factory-installed firmware on-chip nonvolatile memory. This firmware translates memory access requests from RS-232 serial port port into register accesses DS3100. When microcontroller starts turns DS16 indicate that controller working correctly. pushbutton switch labeled RESET (SW5) right middle board resets microcontroller well DS3100.
Power-Supply Connectors
included international power supply connected jack power board power supply connected across (J13) black (J19) banana jacks. input then regulated 3.3V 1.8V distributed board components.
DS3100DK
BASIC HARDWARE SETUP
following steps provide quick start using DS3100DK. Configure board serial (RS-232) communication placing jumpers connect left middle pins JMP62 JMP63 (near serial connector). operation supported. Ensure switch (near connectors) "MAS" position. switch (MASTSLV) (master) position. switch (normal operation) position. switch have 1.544/2.048MHz frequency options DS3100 default 1.544MHz. 2.048MHz. Connect standard DB-9 serial cable between serial port connector DS3100DK available serial port host computer. sure cable standard straight-through cable rather than null-modem cable. Null-modem cables prevent proper operation.) Attach appropriate power supply prongs included international power supply. Plug power supply into power outlet connect output supply connector (PWR Figure 1-1). this point power indicator LEDs DS1-DS4 should lit. Microcontroller status DS16 right connector) should also lit.
INSTALLING RUNNING SOFTWARE
this time DS3100 demo software only runs Windows 2000 Windows operating systems. install demo software, SETUP.EXE from disk included DS3100DK from file downloadable website www.maxim-ic.com/DS3100DK. After software installation complete, hardware described above software doubleclicking DS3100 Demo icon Windows desktop selecting StartProgramsDallas SemiconductorDS3100 Demo Kit. When main window appears, select correct serial port lower right corner. When communication been properly established between software hardware, field upper-left corner should indicate 3100 where revision device, revision device. demo software always starts demo mode (with DEMO MODE checkbox upper-left corner checked) case user wants look software without having hardware connected connect software with demo hardware, uncheck DEMO MODE box. software optionally initializes DS3100 device then reads state device ready use.
Command Line Options
demo software these command line options: <filepath> -p[port#] specifies alternate file sets serial (COM) port number example: "DS3100DK.exe mylog.mfg example: "DS3100DK.exe -p2" sets COM2
command line options shortcut, such DS3100 demo shortcut that installer adds desktop, right click shortcut select Properties. Shortcut tab, text Target textbox, space followed command line option.
DS3100DK
OVERVIEW SOFTWARE INTERFACE
Global Configuration
upper-left corner main window several global status configuration fields including device REV, status MASTSLV (MCR3:MASTSLV), software DEMO MODE check box, 1.544MHz 2.048MHz frequency selection (MCR3:SONSDH).
Input Clock Monitor, Divider, Selector
This occupying left-center section main window contains most frequently used configuration status associated with input clocks IC1-IC14. left, inputs configured either composite clock IC1A IC2A pins, respectively) CMOS pins, respectively). Similarly, configured LVDS PECL operation. Just right input clock numbers 1-14 software LEDs that indicate state each input reported input monitor. These LEDs absence other condition. When clock correct frequency applied input, associated turns yellow when activity detected and, about seconds later, turns green input clock frequency within range. input disqualified DPLLs because DPLL could lock turns magenta. middle box, FREQ MODE fields configure frequency lock mode (direct-lock, DIVN, LOCK8K) each input clock. bottom field configure DIVN divider used inputs configured DIVN mode. fields containing PRIORITY fields display information about either DPLL DPLL, depending which radio buttons selected bottom box. PRIORITY fields configure input clock priorities selected DPLL. field shows selected reference DPLL, while fields display three highest priority valid inputs DPLL. FREQ PHASE fields show real-time frequency phase reported DPLL. future releases DS3100DK software, More button will open secondary window with additional configuration status fields.
Table 4-1. Mapping Between Input Clock Software Fields DS3100 Register Fields
SOFTWARE FIELD Signal Format (CMOS Signal Format (CMOS Signal Format (LVDS PECL) Signal Format (LVDS PECL) DS3100 REGISTER FIELDS MCR5:IC1SF MCR5:IC2SF MCR5:IC5SF MCR5:IC6SF ISR1-ISR7 registers when HARD yellow when HARD green when HARD LOCK magenta when HARD LOCK ICR1-ICR14, FREQ[3:0] ICR1-ICR14, LOCK8K, DIVN IPR1-IPR7 PTAB1:SELREF PTAB1:REF1 PTAB2:REF2 PTAB3:REF3 FREQ1, FREQ2 FREQ3 registers concatenated PHASE1 PHASE2 register concatenated
Input Clock Status LEDs
FREQ MODE PRIORITY FREQ (ppm) PHASE (deg)
DS3100DK
DPLL
state DPLL (free-run, locked, holdover, etc.) shown STATE field. STATE CHG, SRFAIL PHMON fields buttons that represent latched status bits device. When button raised middle, corresponding latched status been DS3100. Pressing button clears latched status bit. STATE indicates state DPLL changed since last time button pressed. SRFAIL indicates selected reference failed since last time button pressed. PHMON indicates phase monitor limit (set PMLIM) been exceeded. state DPLL forced using combo left STATE field, selected reference forced using field. Below field field that configures DPLL revertive nonrevertive input reference switching. frequency DPLL displayed FREQ field (fixed 77.76MHz DS3100 DPLL). acquisition locked bandwidths fields, respectively, damping factor DAMP field. acquisition bandwidth only used AUTOBW checked. frequency DPLL's selected reference exceeds SOFT LIMIT setting DPLL FREQUENCY LIMITS window), SOFTLIM turns red. PALARM status PHASE MONITOR BUILDOUT fields advanced topics. Table DS3100 data sheet more details. future releases DS3100DK software, More button will open secondary window with additional configuration status fields.
Table 4-2. Mapping Between DPLL Software Fields DS3100 Register Fields
SOFTWARE FIELD STATE combo STATE status Revertive/Nonrevertive FREQ DAMP STATE SRFAIL PHMON PALARM SOFTLIM AUTOBW LIMINT PMLIM PMEN PMPBEN PBOEN PBOFRZ RECAL MANUAL DS3100 REGISTER FIELDS MCR1:T0STATE OPSTATE:T0STATE MCR2:T0FORCE MCR3:REVERT Fixed DPLL architecture T0ABW T0LBW T0CR2:DAMP MSR2:STATE MSR2:SRFAIL MSR3:PHMON TEST1:PALARM OPSTATE:T0SOFT MCR9:AUTOBW MCR9:LIMINT PHMON:PMLIM PHMON:PMEN PHMON:PMPBEN MCR10:PBOEN MCR10:PBOFRZ FSCR3:RECAL OFFSET1 OFFSET2
DS3100DK
DPLL
state DPLL (locked locked) shown STATE field. LOCK INPUT fields buttons that represent latched status bits device. When button raised middle, corresponding latched status been DS3100. Pressing button clears latched status bit. LOCK indicates state DPLL changed since last time button pressed. INPUT means DPLL valid inputs available. selected reference DPLL forced using field. frequency DPLL displayed FREQ field. When FREQ field changed, frequency option listed APLL combo automatically changes match. option APLL currently selected, frequencies options OC1-OC7 output clock combo boxes automatically change frequencies derived from APLL frequency. These changes match what happens inside DS3100 device. bandwidth DPLL field, while damping factor DAMP field. frequency DPLL's selected reference exceeds SOFT LIMIT setting DPLL FREQUENCY LIMITS window), SOFTLIM turns red. Digital feedback (vs. analog feedback through APLL) selected using DIGFB checkbox. LKT4T0 T4MT0 fields advanced topics. Table DS3100 data sheet more details. future releases DS3100DK software, More button will open secondary window with additional configuration status fields.
Table 4-3. Mapping Between DPLL Software Fields DS3100 Register Fields
SOFTWARE FIELD STATE FREQ DAMP LOCK INPUT SOFTLIM DIGFB LKT4T0 T4MT0 DS3100 REGISTER FIELDS OPSTATE:T4LOCK MCR4:T4FORCE T4CR1:T4FREQ T4BW T4CR2:DAMP MSR3:T4LOCK MSR3:T4NOIN OPSTATE:T4SOFT MCR4:T4DFB MCR4:LKT4T0 T0CR1:T4MT0
DS3100DK
APLL
APLL connected output Output Low-Frequency (see DS3100 data sheet details). frequency options listed APLL field APLL input frequencies. APLL output frequency always four times input frequency. difference between "77.76 Analog" "77.76 Digital" options whether feedback path DPLL includes feedback APLL. non-77.76 options APLL field frequencies from Low-Frequency DFS. When APLL setting changed, frequencies options OC1-OC7 output clock combo boxes automatically change frequencies derived from APLL frequency. These changes match what happens inside DS3100 device.
Table 4-4. Mapping Between APLL Software Fields DS3100 Register Fields
SOFTWARE FIELD APLL DS3100 REGISTER FIELDS T0CR1:T0FREQ
APLL
APLL connected output DPLL output DPLL (specifically low-frequency DFS; DS3100 data sheet details). frequency options listed APLL field APLL input frequencies. APLL output frequency always four times input frequency. When FREQ field changed DPLL box, frequency option listed APLL combo automatically changes match. option APLL currently selected, frequencies options OC1-OC7 output clock combo boxes automatically change frequencies derived from APLL frequency. These changes match what happens inside DS3100 device. Similarly, APLL option changed, frequencies options OC1-OC7 output clock combo boxes automatic change frequencies derived from APLL frequency.
Table 4-5. Mapping Between APLL Software Fields DS3100 Register Fields
SOFTWARE FIELD APLL DS3100 REGISTER FIELDS T0CR1:T4APT0, T0CR1:T0FT4
DS3100DK
Output Clocks
fields this configure DS3100's output clocks. 2K8K field specifies source path path) 2kHz 8kHz clock options output clocks OC1-OC7. Similarly DIG1 DIG2 fields configure Digital1 Digital2 frequency options OC1-OC7 (see DS3100 data sheet details). OC1-OC7 fields specify output frequencies outputs OC1-OC7. Note that when APLL setting changed, frequencies options OC1-OC7 fields automatically change frequencies derived from APLL frequency. Similarly, when APLL setting changed, frequencies options OC1-OC7 fields automatically change frequencies derived from APLL frequency. These changes match what happens inside DS3100 device. OC89 field specifies whether path path source output clocks OC9. 64kHz composite clock output. field configures output clock duty cycle, also whether output signal 8kHz BPVs optionally 400Hz absence-of-BPVs ITU-T G.703 Appendix options "8K" options list enable 8kHz BPVs 400Hz absence-ofBPVs. "400" options enable both 8kHz BPVs 400Hz absence-of-BPVs. dedicated 1.544MHz 2.048MHz output. When OC89 specifies that sourced from path, Auto Squelch checkbox specifies whether automatically squelched when valid input references. When OC89 indicates path, Auto Squelch available match DS3100 behavior. OC10 8kHz output that configured duty cycle clock frame pulse optionally inverted. OC11 2kHz output that similarly configured.
Table 4-6. Mapping Between Output Clock Software Fields DS3100 Register Fields
SOFTWARE FIELD 2K8K DIG1 DIG2 OC1-OC7 OC89 Auto Squelch OC10 OC11 DS3100 REGISTER FIELDS FSCR1:2K8KSRC MCR6:DIG1SS, MCR7:DIG1F MCR6:DIG2SS, MCR7:DIG2F, MCR7:DIG2AF OCR1-OCR4 MCR4:OC89 T4CR1:ASQUEL OCR4:OC8EN, T4CR1:OC8DUTY MCR8:OC8NO8, MCR8:OC8400 OCR4:OC9EN, T4CR1:OC9SON OCR4:OC10EN, FSCR1:8KPUL, FSCR1:8KINV OCR4:OC11EN, FSCR1:2KPUL, FSCR1:2KINV
DS3100DK
DPLL Frequency Limits, Phase Detectors, DPLL Lock Criteria
DPLL frequency limits specify hard soft limits DPLL frequency range. When selected reference DPLL exceeds soft limit, SOFTLIM that DPLL turns selected reference disqualified. FLLOL (frequency limit loss lock) checked DPLL Lock Criteria box, when selected reference DPLL exceeds hard limit DPLL will lose lock transitions Locked state, transitions state). remaining fields advanced topics. Table DS3100 data sheet more details.
Table 4-7. Mapping Between DPLL Software Fields DS3100 Register Fields
SOFTWARE FIELD HARD LIMIT SOFT LIMIT MCPDEN USEMCPD D180 COURSELIM FINELIM FLEN CLEN FLLOL NALOL DS3100 REGISTER FIELDS HARDLIM[9:0] DLIMIT1 DLIMIT2 DLIMIT3:SOFTLIM PHLIM2:MCPDEN PHLIM2:USEMCPD TEST1:D180 PHLIM2:COARSELIM PHLIM1:FINELIM PHLIM1:FLEN PHLIM2:CLEN DLIMIT3:FLLOL PHLIM1:NALOL
DS3100DK
BITS Receivers BITS Transmitters
Mode fields these boxes basic line mode each port (DS1 2048kHz, and-for receivers only-6312kHz). termination fields specify line termination receiver transmitter port. DS3100 supports either internal termination (inside device) external termination (resistors board). shipped from factory demo hardware does have external termination resistors populated, therefore only internal termination options should selected software. input clock (IC1-IC14) which each BITS receiver should connected specified CLOCK DEST fields. output clock which each BITS transmitter should connected specified CLOCK SOURCE fields. BITS Transmitters box, when transmitter mode, value transmitted specified fields below headings. mode, channel which transmit SSMs specified (for both transmitters) small combo next label. BITS Receivers box, when receiver mode, received values displayed fields below headings. mode, channel which look incoming SSMs specified (for both receivers) small combo next label. future releases DS3100DK software, headings RX1, RX2, TX1, will also buttons that open secondary windows with additional configuration status fields.
4.9.1
Note About Working with BITS Receivers Transmitters
When switching BITS transmitter receiver modes, termination must changed match: internal DS1, internal 2048kHz, internal 6312kHz. When switching BITS transmitter modes between E1/2048kHz modes, rate transmit clock source (typically OC9) must changed match: 1.544MHz 2.048MHz E1/2048kHz. Enabling analog loopback between BITS transmitter BITS receiver between BITS transmitter BITS receiver useful evaluating DS3100. During device initialization DS3100DK software enables analog loopback both BITS transmitter/receiver pairs setting registers B1BLCR4 (address 93h) B2BLCR4 (address 113h).
Table 4-8. Mapping Between BITS Software Fields DS3100 Register Fields
SOFTWARE FIELD BITS RECEIVERS Mode Termination Clock Dest Left-Hand Combo Only) Textboxes BITS TRANSMITTERS Mode Termination Clock Source Left-and Combo Only) Main Combos BMCR:TMODE, BTMMR, BTCR1:TB8ZS, BTCR3:TFM, BTCR4:THDB3, BTCR4:TCRC4, APPENDIX BITS MODE WRITE SEQUENCES exact write sequences. BLCR2:TION, BLCR2:TIMP BCCR1:TCLKS Indicates which BTSa4-BTSa8 ESF: BRBOC:RBOC BTSa4-BTSa8 BMCR:RMODE, BCCR3:MCLKFC, BRMMR, BRCR1:RB8ZS, BRCR1:RFM, BRCR3:RHDB3, BRCR3:RCRC4 APPENDIX BITS MODE WRITE SEQUENCES exact write sequences each mode BLCR3:RION, BLCR3:RIMP BCCR2:RCLKD BRMCR:SSMCH ESF: BTBOC:TBOC BRMSR, BRSSM:SSM DS3100 REGISTER FIELDS
DS3100DK
4.10
Composite Clock Receivers
fields buttons that represent latched status bits device. When button raised middle, corresponding latched status been DS3100. Pressing button clears latched status bit. buttons indicate deviation from expected one-BPV-in-eight pattern occurred since that button last pressed. buttons indicate pulses were detected input signal period (i.e., after missing pulses). future releases DS3100DK software, More button will open secondary window with additional configuration status fields.
Table 4-9. Mapping Between Software Fields DS3100 Register Fields
SOFTWARE FIELD DS3100 REGISTER FIELDS MSR3:AMI1 MSR3:LOS1 MSR3:AMI2 MSR3:LOS2
4.11
REFCLK Calibration
known frequency error local oscillator calibrated inside DS3100 setting value REFCLK box. Also significant edge REFCLK signal selected XOEDGE field.
Table 4-10. Mapping Between REFCLK Software Fields DS3100 Register Fields
SOFTWARE FIELD REFCLK slider/textbox XOEDGE DS3100 REGISTER FIELDS MCLKFREQ[15:0] MCLK1 MCLK2 MCR3:XOEDGE
4.12
Register View Window
When Register View button upper-right corner main window pressed, Register View window appears. this window DS3100's entire register viewed manually written needed. large grid that takes most window displays DS3100 register map. each register, hexadecimal address square brackets followed register name contents 2-digit format. DS3100's core register space 7Fh, BITS transceiver register space FFh, BITS transceiver register space 100h 17Fh. distinguish between BITS1 BITS2 registers, BITS1 register names start with "B1" BITS2 register names start with "B2." When register clicked main register grid, register description fields displayed bottom window. limited speed serial port, demo software does continually poll every register make real-time updates data displayed Register View screen. Register concern should manually read described below. Register View window supports following actions: Read register. Select register register click Read button. Read registers. Press Read button. Write register field. Select register, double-click field, enter value written. Write register. Double-click register name register array enter value written. Write multi-register field. Double-click register names register array enter value field. software will allow writes read-only registers fields, does allow writes registers that have read/write read-only fields.
DS3100DK
4.13
Configuration Scripts File
4.13.1 Configuration File
Every write command issued software DS3100DK board logged file DS3100DKLog.mfg located same directory software executable. This file viewed Notepad pressing File button upper-right corner main window. Command line option <filepath>" used cause software write different file than DS3100DKLog.mfg.
4.13.2 Configuration Scripts
part text Configuration File copied text file with .mfg file extension configuration script. Configuration scripts useful quickly configuring DS3100 without having remember required settings. types configuration scripts possible: full partial. full configuration script start with DS3100 power-on default state configure every aspect device bring desired state. make full configuration script, software, uncheck Demo Mode checkbox, configure device using software fields (including Register View writes needed), press File button, File->Save Notepad save copy entire file different file name. partial configuration file only affects subset DS3100 device settings. make partial configuration script, press File button view File, press Ctrl-End jump file, file carriage return comment line (starting with semicolon) delimit start configuration. Then save exit File. Next configure device using software fields (including Register View writes needed). Finally view file again, jump end, copy everything from delimiter made earlier file into .mfg file. configuration script, press Config Script button upper-right corner main window. script window, type path file press Browse button navigate file. Note that browser window does have Desktop Documents file hierarchy like Windows does. Both Desktop Documents <username> found under c:\Documents Settings\<username>. Note that when Demo Mode checkbox unchecked, during "Initializing DS3100" step, software runs configuration script startup.mfg located same directory software executable. Startup.mfg edited replaced needed change initial configuration device.
ADDITIONAL INFORMATION RESOURCES
DS3100 Information
more information about DS3100, refer DS3100 data sheet www.maxim-ic.com/DS3100.
DS3100DK Information
more information about DS3100DK including software downloads, refer DS3100DK Quick View page www.maxim-ic.com/DS3100DK.
Technical Support
additional technical support, e-mail your questions telecom.support@dalsemi.com.
DS3100DK
APPENDIX HARDWARE COMPONENTS
DESIGNATION DESCRIPTION SUPPLIER PART
C42, C59-C138, C140, C142, C143, C145, C147, C149, C151, C155, C163-C166, C168, C169 C13, C14, C16, C17, C18, C28, C34-C38, C51-C58, C139, C141, C153, C154 C39, C48, DS1-DS4 DS5-DS10 DS16 J6-J12, J20-J41 J55, J56, J85, J86, J89, J90, J117 J57, J58, J83,
0.1F ±20%, ceramic capacitors (0603)
0603YC104MAT
Ceramic capacitors (0805) POPULATE 470pF ±5%, ceramic capacitor (0805) ±20%, tantalum capacitor case) 4.7F ±10%, ceramic capacitors (1206) 6.8F ±10%, 6.3V ceramic capacitors (1206) 560pF ±5%, ceramic capacitor (0805) ±20%, ceramic capacitors (1206) 22pF ±10%, 100V ceramic capacitors (1206) ±10%, ceramic capacitor (1206) 0.47F ±10%, ceramic capacitors (0805) general-purpose silicon diode Schottky diode Green LEDs (SMD) LEDs (SMD) Green (SMD) 6-pin socket strip (single row, vertical) 2.1mm/5.5mm closed frame power jack, high current (right angle PCB, 24VDC 5-pin vertical connectors (50) socket (banana plug, horizontal) 5-pin vertical connector (50) POPULATE 10-pin terminal strip (dual row, vertical) Black horizontal banana plug socket right-angle connector (long case) 10-pin terminal strip (dual row, vertical) Type black connector (right angle) Bantam jack connectors (right angle) 5-pin connectors (50, right angle)
Panasonic Panasonic Panasonic Panasonic Panasonic Corp. Panasonic Panasonic Vishay General Semiconductor International Rectifier Panasonic Panasonic Panasonic Samtec Inc. Mouser Samtec Mouser Molex Switchcraft Trompeter
08055A471JAT ECS-T1CD686R ECJ-3YB1E475K ECJ-3YB0J685K ECJ-2VC1H561K ECJ-3YB1A106M 12061A220KAT2A ECJ-3YB1C105K ECJ-2YB1C474K 1N4001 10BQ040 LN1351C LN1251C LN1351C SS-106-TT-2-N PJ-002AH 413990-1 164-6219 413990-1 TSW-105-07-T-D 164-6218 747459-1 67068-0000 RTT34B02 CBJR220
DS3100DK
DESIGNATION JMP1-JMP5, JMP8, JMP9, JMP11, JMP12, JMP36, JMP37 JMP6, JMP7, JMP10, JMP62, JMP63 R11, R16-R18 R10, R12R14, R20, R25, R42, R46, R84, R91, R92, R95-R97, R110, R113, R115, R116, R120R123 R15, R22, R23, R24, R41, R43, R45, R47,R49, R51, R53, R55, R80, R81, R111, R112, R117, R118 R19, R21, R40, R26, R27, R48, R50, R29-R35, R59-R68 R36-R39, R94, R108 R54, R56, R57, R58, R74, R77, R89, R69, R70, R71, R75, R82, R85-R88 SW7, SW8, TP1-TP10, TP18- TP42, TP49-TP61, TP65-TP84 U9-U26 DESCRIPTION 2-pin vertical headers, 0.100" centers SUPPLIER Samtec PART TSW-102-07-T-S
3-pin vertical headers, 0.100" centers ±5%, 1/10W resistor (0805) Resistors (0603) POPULATE
Samtec Panasonic
TSW-103-07-T-S ERJ-6GEYJ103V
±5%, 1/16W resistors (0603)
Panasonic
ERJ-3GEYJ103V
±1%, 1/16W resistors (0603) 1.0k ±5%, 1/16W resistors (0603) ±5%, 1/16W resistors (0603) 33.2 ±1%, 1/16W resistors (0603) 51.1 ±1%, 1/16W resistors (0603) ±5%, 1/16W resistors (0603) ±5%, 1/8W resistors (1206) ±1%, 1/10W resistors (0805) 10.0 ±1%, 1/10W resistors (0805) 13.0 ±1%, 1/10W resistors (0805) 90.9 ±1%, 1/10W resistors (0805) ±1%, 1/10W resistor (0805) ±1%, 1/10W resistor (0805) ±5%, 1/10W resistors (0805) Resistors (0805) POPULATE 4-pin single-pole switch 6-pin, through-hole, DPDT slide switch 3-pin, through-hole, SPDT slide switches 16-pin transformers (1CT:1CT 1CT:2CT, 1500V) 12-pin dual transformer (64kbps, 1CT:2CT, 1500V) 64kbps interface transformer (1CT:1CT, 1500V, 6-pin DIP) plated hole test points STUFF High-frequency, surface-mount socket (1mm, 256-pin BGA) TinyLogic ultra-high-speed 2-input gates (5-pin SOT23)
CJ10-000F
Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Tyco Tyco Pulse Engineering Pulse Engineering Pulse Engineering Ironwood Electronics Fairchild Semiconductor
ERJ-3GEYJ102V ERJ-3GEYJ471V ERJ-3EKF33R2V ERJ-3EKF51R1V ERJ-3GEYJ331V ERJ-8GEYJ0R00V ERJ-6ENF1100V ERJ-6ENF10R0V ERJ-6ENF13R0V ERJ-6ENF90R9V ERJ-6ENF3570V ERJ-6ENF3010V ERJ-6GEY0R00V EVQPAE04M SSA22 SSA12 PE-68678 T7015 PE-65540 SG-BGA-6017 NC7SZ32M5
DS3100DK
DESIGNATION DESCRIPTION 3.3V linear regulator (16-pin TSSOP-EP) 1.8V linear regulator (16-pin TSSOP-EP) 3-line 8-line decoder/demultiplexer (16-pin Dual RS-232 transmitter/receiver (16-pin, 300-mil High-speed microcontroller (44-pin TQFP, +70°C) Microprocessor voltage monitor (3.08V reset threshold) (4-pin SOT143) Microprocessor voltage monitor (4.38V reset threshold) (4-pin SOT143) Single-chip UART bridge (28-pin QFN) 3.3V, 12.8MHz OCXO (5-pin) through-hole POPULATE 3.3V, 12.8MHz TCXO (4-pin SMD) 3.3V, 12.8MHz OCXO (4-pin SMD) POPULATE Low-profile 11.0592MHz crystal SUPPLIER Maxim Maxim Texas Instruments Dallas Semiconductor Dallas Semiconductor Maxim Maxim Silicon Laboratories Vectron Vectron Vectron Pletronics PART MAX1793EUE-33 MAX1793EUE-18 SN74HC138NSR DS232AS DS87C520-ECL MAX811TEUS-T MAX812MEUS-T CP2101 MC853X4-035W C22601A1-0028 C4400A1-0044 LP49-33-11.0592M
DS3100DK
APPENDIX BITS MODE WRITE SEQUENCES
BITS Transmitter
address 04h, TMODE[1:0]=00 address 21h, write address 21h, write address 27h, write address 29h, write address 21h, write address 21h, write SF/D4 address 04h, TMODE[1:0]=00 address 21h, write address 21h, write address 27h, write address 29h, write address 21h, write address 21h, write address 04h, TMODE[1:0]=01 address 21h, write address 21h, write address 29h, write address 2Ah, write address 21h, write address 21h, write address 60h, write address 61h, write 2048kHz address 04h, TMODE[1:0]=10 address 21h, write address 21h, write
BITS Receiver
address 04h, RMODE[1:0]=00 address 0Ah, write address 20h, write address 20h, write address 22h, write address 20h, write address 20h, write SF/D4 address 04h, RMODE[1:0]=00 address 0Ah, write address 20h, write address 20h, write address 22h, write address 20h, write address 20h, write address 04h, RMODE[1:0]=01 address 20h, write address 20h, write address 24h, write address 20h, write address 20h, write 2048 address 04h, RMODE[1:0]=10 address 20h, write address 20h, write 6312 address 04h, RMODE[1:0]=11 address 20h, write address 20h, write
SCHEMATICS DOCUMENT REVISION HISTORY
REVISION DATE 091806 110206 DESCRIPTION Initial DS3100DK data sheet release. Updated document describe software v0.7 features: (page Features section; (page Section 3.1; (page Section 4.12; (page added Section 4.13, 4.13.1, 4.13.2; updated table captions.
DS3100DK schematics featured following pages.
Maxim/Dallas Semiconductor cannot assume responsibility circuitry other than circuitry entirely embodied Maxim/Dallas Semiconductor product. circuit patent licenses implied. Maxim/Dallas Semiconductor reserves right change circuitry specifications without notice time.
Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600
2006 Maxim Integrated Products
Maxim logo registered trademark Maxim Integrated Products, Inc. Dallas logo registered trademark Dallas Semiconductor Corporation.
TP29 TP32 TP36 TP38 TP40 TP42 TP31 TP34 TP37 TP39 TP41 TP61
RESREF JTRST JTCLK JTDI JTMS JTDO GPIO1 GPIO2 GPIO3 GPIO4
INTREQ
JTDI
JTMS
JTDO
JTCLK
GPIO1
GPIO2
GPIO3
RESREF
JTRST*
IC1A
GPIO4
TST_RA1
TST_RA2
TST_RB1
TST_RB2
TST_RC1
TST_RC2
TST_TA1
TST_TA2
TST_TB1
TST_TB2
TST_TC1
OC6POS OC6NEG
TST_TC2
DS10
IC5POS
.1UF
IC2A
IC5NEG
IC6POS
IC6NEG
OC7POS OC7NEG OC8POS
DS3100_U1
OC8NEG
IC11
IC10
IC13 AD<0>_SDO AD<1>_SDI AD<2>_SCLK AD<3> AD<4> AD<5> AD<6>_CPHA AD<7>_CPOL
OC11
OC6POS OC6NEG OC7POS OC7NEG OC8POS OC8NEG OC10 OC11
R98DNP
IC1A IC2A IC5POS IC5NEG IC6POS IC6NEG IC10B12 IC11 IC12C12 IC13B13 IC14A14
IC14
IC12
CONTROL
OC10
SYNC2K 0L_SMT0603_1PCT CJ10-000F SYNC2K
SONSDH
A<0>
A<1>
SPDT
A<2>
A<3>
SRCSW
A<4>
A<5>
SPDT
IFSEL<0> IFSEL<1> IFSEL<2> REFCLK RST* HIZ* MASTSLV SONSDH SRCSW SRFAIL WR_RW* RD_DS* RDY* INTREQ
A<6>
A<7>
INTEL
MASTSLV
A<8>
SPDT
REFCLK PORNOT
IFSEL0 IFSEL1 IFSEL2
TP28
IFSEL0 IFSEL11 IFSEL2
MASTSLV SONSDH SRCSW SRFAIL CS_3100 INTREQ
TP1TP2
13:21:44 2006
TITLE: DATE:
DS3100DK01B0
ENGINEER:
110705
PAGE:
C163.1UF
C164.1UF
C165.1UF
TP10
TRINGA TRINGB THZE TCLK
MCLK
RCLK
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19 VDD20 VDD21 VDD22 VDD23 VDD24
DVDD
AVDD_PLL1 AVDD_PLL2 AVDD_PLL3 AVDD_PLL4
RSER1
TSER
RSER
TTIPA1 TTIPA1 TRINGA1 TRINGA1 THZE1 TCLK1 TOUT1 TIN1 TSER1
DUT33
VDD_ICDIFF VDD_OC6 VDD_OC7
MCLK1 RCLK1 ROUT1
TOUT
ROUT
RVDD_P1 RVDD_P2 TVDD_P1 TVDD_P2
RRING1
RRING
C166.1UF
TTIPB
1AVDD_PLL1 1AVDD_PLL2 1AVDD_PLL3 1AVDD_PLL4
RTIP1
TTIPA
DS3100_U1
RTIP
PORT
DUT18
DUT33
AVDD_PLL1 AVDD_PLL2 AVDD_PLL3 AVDD_PLL4
DS3100_U1
RCLK1 TIN1 ROUT1 RSER1 TSER1
CONN_6P_U
TTIPA TTIPB TRINGA TRINGB THZE TCLK TOUT
VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO9 VDDIO10 VDDIO11 VDDIO12 VDDIO13 VDDIO14 VDDIO15 VDDIO16 VDDIO17 VDDIO18 VDDIO19 VDDIO20 VDDIO21 VDDIO22 VDDIO23 VDDIO24 VDDIO25 VDDIO26 VDDIO27 VDDIO28
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28
RTIP2L16
DS3100_U1
RTIP
PORT
AVSS_PLL1 AVSS_PLL2 AVSS_PLL3 AVSS_PLL4
RVSS_P1 RVSS_P2 TVSS_P1 TVSS_P2
VSS_ICDIFF VSS_OC6 VSS_OC7
DVSS
TP18
MCLK
RCLK
MCLK2T10 RCLK2R10 ROUT2P10
TSER
ROUT
RSER2T11
RSER
TTIPA2 TTIPA2 TRINGA2 TRINGA2 THZE2 TCLK2 TOUT2 TIN2 TSER2
VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56
RRING2
RRING
RCLK2 TIN2 ROUT2 RSER2 TSER2
13:21:51 2006
TITLE: DATE:
DS3100DK01B0
CONN_6P_U ENGINEER:
110705
PAGE:
SIGNAL TRACKS WITH RESPECT PLANE 12.8MHZ_3.3V
51.1
SUPPLY_V
OSC33
RF_OUT
.1UF
OSC_MC853X4
51.1
12.8MHZ_3.3V
OSC_TCXO
33.2
RF_OUT
.1UF
REFCLK
51.1
12.8MHZ_3.3V
OSC_OCXO
51.1
12.8MHZ
R102
.1UF
RF_OUT
FOUT
1R100
VREF VOSC VCCD
R101
GNDA
51.1
OSC33
GNDOSC
GNDD
C11DNP
C12DNP
C15DNP
C19DNP
C21DNP
DS4026_U
51.1
51.1
13:21:45 2006
TITLE: DATE:
DS3100DK01B0
ENGINEER:
110705
PAGE:
INPUT CLOCKS
SIGNAL TRACKS WITH RESPECT PLANE
PLACE TESTPOINTS CENTER
IC10
51.1
TP49
IC5POS
51.1
JMP36
51.1
IC11
TP50
TP53 TP54
51.1
IC5NEG
IC12
PLACE TESTPOINTS CENTER IC6POS
51.1
51.1
JMP37
51.1
TP51 TP52 IC13
TP55 TP56
51.1
IC6NEG
IC14
51.1
SYNC2K
51.1
13:21:49 2006
TITLE: DATE:
DS3100DK01B0
ENGINEER:
110705
PAGE:
INPUT CLOCKS
OC10
NC7SZ32
NC7SZ32
VERT
VERT
NC7SZ32
NC7SZ32
OC11
NC7SZ32
NC7SZ32
VERT
VERT
NC7SZ32
NC7SZ32
OC6POS
I105
VERT I114 TP60 I113 TP59
NC7SZ32
NC7SZ32
I107
OC6NEG
VERT OC7POS
NC7SZ32
I109
I115 TP57 I116 TP58 I111 OC7NEG
NC7SZ32
VERT
NC7SZ32
NC7SZ32
PLACE TESTPOINTS CENTER
10:14:03 2005 VERT
TITLE: DATE:
NC7SZ32
DS3100DK01B0
ENGINEER:
092205
PAGE:
NC7SZ32
OUTPUT CLOCKS
1.0K
1.0K
R52470
JMP1
JMP3
GPIO1
GPIO3
SRFAIL
JMP5
R48470
R26470
NC7SZ32
NC7SZ32
NC7SZ32
1.0K
1.0K
JMP2
GPIO2
JMP4
GPIO4
R50470
R27470
NC7SZ32
NC7SZ32
10:14:03 2005
TITLE: DATE:
GPIO
ENGINEER:
DS3100DK01B0
PAGE:
092205
RTIP1
560PF
TTIPA1
0L_SMT1206_5PCT ERJ-8GEYJ0R00V
TRINGA1
CONN_BANTAM
CONN_BANTAM
RRING1
JMP11
RTIP2
TTIPA2
0L_SMT1206_5PCT ERJ-8GEYJ0R00V
560PF
CONN_BANTAM
TRINGA2
CONN_BANTAM
RRING2
JMP12
13:21:42 2006
TITLE: DATE:
BITS TRANSCEIVER
ENGINEER:
DS3100DK01B0
PAGE:
110705
IC1A
OC8POS
JMP8
.47UF
90.9
330PF
.01UF
JMP7
JMP10
J117
CONN_BANTAM
90.9
R770.0
CONN_BANTAM
OC8NEG
JMP9
.47UF
IC2A
330PF
CONN_BANTAM
JMP6
13:21:43 2006
TITLE: DATE:
COMPOSITE CLOCK
ENGINEER:
DS3100DK01B0
PAGE:
110705
V5_0
RS232
10UF
DS232A
VPOS
10UF
10UF
10UF
VNEG
10UF
C1POS
C2POS
C1NEG
C2NEG
(SCLK) (SDIO) SLAVE
RX232 TX232 GREEN
R108
R1IN
R1OUT
R2IN
R2OUT
T1IN
T1OUT
T2IN
T2OUT
DS16
V5_0
CONN_10P
NC7SZ32
JMP62 USB_TXD
P1_0 P1_1 P1_2 P1_3 P1_4 P1_5 P1_6 P1_7 P3_0 P3_1 P3_2 P3_3 P3_4 P3_5 P3_6 P3_7 XTAL1 XTAL2 GND<2-0> PSEN P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0
USB_RXD JMP63
RXD0
TXD0
G2B*
V5_0
R110
G2A*
TX232 RX232 RXD0 TXD0 INTREQ
74AHC138
DPDT
CONN_DB9P
CS_3100 SLAVE
SLAVE
11.0592MHZ
22PF
DS87C520_TQFP
22PF
10:14:03 2005
TITLE: DATE:
DS3100DK01B0
ENGINEER:
092205
PAGE:
R115
R113
4.7UF
.1UF
USBDP VBUS RST*
RTS*
R117 R118
USB_TXD USB_RXD
CTS*
USBDM
CP2101_U1
REGIN SUSPEND_LOW*
DCD* SUSPEND_HIGH NC10
JTCLK JTDO JTMS JTRST JTDI
DATDAT+
DSR*
TP84 TP83
R120
DTR*
R121 R122 R123
CONN_10P
3.08V
4.38V
NC11
RESET
R116
V5_0
RESET*
MAX811_U
MAX812_U
R111
PORNOT
R112
10:14:03 2005
TITLE: DATE:
DS3100DK01B0
ENGINEER:
092205
PAGE:
V5_0 V5_0
JMP13
OUT3 OUT2 OUT1
68UF
DUT33
CONN_BANANA_2P
RST* SHDN* OUT4
4.7UF 6.8UF
2.1MM/5.5MM
V5_0
OUT2 OUT3 OUT4 RST* SHDN* OUT1
CONN_BANANA_2P
4.7UF
6.8UF
V5_0
V5_0
OSC33
OUT2
4.7UF
DUT33
OUT4 RST*
DUT18
SHDN*
NC7SZ32
6.8UF
OUT3
MAX1793_U2
JMP14 OSC33
V5_0
MAX1793_U2
OUT1
JMP15
DUT18
MAX1793_U2
13:21:47 2006
TITLE: DATE:
DS3100DK01B0
ENGINEER:
110705
PAGE:
TP67 TP66
.1UF C106
.1UF C105
.1UF C104
TP73 TP71 TP72 TP70
.1UF C126
.1UF C125
.1UF C124
TP78 TP76 TP77 TP75
.1UF
.1UF
.1UF
TP82 TP80 TP81
ENGINEER: TITLE:
10UF
10UF
10UF
10UF
10UF
10UF
DUT18
DUT33
.1UF
.1UF
10UF
.1UF
10UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
I112 I111 I113 TP65
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF C102
.1UF C101
.1UF C100
.1UF
TP68 TP69
.1UF C110
.1UF C109
.1UF C108
.1UF C103
.1UF C114
.1UF C113
.1UF C112
.1UF C107
.1UF C111
.1UF C118
.1UF C117
.1UF C116
C115 .1UF
.1UF C122
.1UF C121
.1UF C120
.1UF C119
TP74
.1UF C130
.1UF C129
.1UF C128
.1UF C123
.1UF C134
.1UF C133
.1UF C132
.1UF C127
.1UF C131
.1UF C136
C138 .1UF
C137 .1UF
.1UF C135
TP79
.1UF
C153
C139
10UF C154
10UF C141
V5_0
OSC33
10UF C155
.1UF C168
10UF C143
.1UF C145
V5_0
.1UF C169
.1UF C147
.1UF
.1UF C149
.1UF C151
.1UF C140
.1UF C142
PAGE:
.1UF
DS3100DK01B0
DATE:
10:14:03 2005
092205
REVISION HISTORY 050206 012106 RELEASE 011306 010406 CHANGED DESIGNATORS MATCH REMOVED CAPS, LEDS SWITCHES FROM MICRO, FROM 112105 MOVED MEMORY MAP,OTHER MISCELLANEOUS 111905 110705 RELEASE REVIEW TRANSFORMER ISSUES,ADDED POWER JACK,FIXED CSM/CSS LOGIC,ADDED
ADDED BUFFER 1.8V ADDED RESISTORS SDIO,SCLK,SCS ADDED INTEL CONNECTIONS MADE INTEL MODE DEFAULT ADDED 330PF CAPS COMPOSITE CLOCK INPUT FIXED COMPOSITE CLOCK TERMINATION CHANGED FROM MOVED P1.1 REVERSED LOGIC CHANGED COMPOSITE CLOCK .01UF ADDED SHORTED JUMPERS REGULATORS ACCESS MOVED 1000 ADDED DS4026 TCXO SUPPORTING COMPONENTS
10:14:03 2005
TITLE: DATE:
DS3100DK01B0
ENGINEER:
092205
PAGE:

DS3100DK easy-to-use demo evaluation DS3100 Stratum 3/3E timing card s

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