22-BIT PROGRAMMABLE PULSE GENERATOR (SERIES 3D7622 SERIAL INTERFACE)

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22-BIT PROGRAMMABLE PULSE GENERATOR (SERIES 3D7622 SERIAL INTERFACE)

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3D7622
22-BIT PROGRAMMABLE PULSE GENERATOR (SERIES 3D7622 SERIAL INTERFACE)
All-silicon, low-power CMOS technology TTL/CMOS compatible inputs outputs Vapor phase, wave solderable Programmable serial interface Increment range: 0.25ns through 50.0ns Pulse width tolerance: (See Table Supply current: typical Temperature stability: ±1.5% (-40C 85C) stability: ±0.5% (4.75V 5.25V)
data delay devices, inc.
PACKAGE PINOUT
TRIG OUTB
3D7622D-xx SOIC
mechanical dimensions, click here. package marking details, click here.
FUNCTIONAL DESCRIPTION
3D7622 device versatile 22-bit programmable monolithic pulse generator. rising-edge trigger input (TRIG) initiates pulse, which presented output pins (OUT,OUTB). pulse width, programmed serial interface, varied over 4,194,303 equal steps according formula: tinh addr tinc where addr programmed address, tinc pulse width increment (equal device dash number), tinh inherent (address zero) pulse width. device also offers reset input (RES), which used terminate pulse before programmed time expired. all-CMOS 3D7622 integrated circuit been designed reliable, economic alternative hybrid pulse generators. offered standard 14-pin SOIC.
DESCRIPTIONS
TRIG OUTB Trigger Input Reset Input Pulse Output Complementary Pulse Output Address Enable Input Serial Clock Input Serial Data Input Serial Data Output Volts Ground Internal Connection
TABLE PART NUMBER SPECIFICATIONS
PART NUMBER
3D7622D-0.25 3D7622D-0.4 3D7622D-0.5 3D7622D-1 3D7622D-2 3D7622D-2.5 3D7622D-4 3D7622D-5 3D7622D-10 3D7622D-20 3D7622D-25 3D7622D-40 3D7622D-50 Pulse Width Step (ns) 0.25 0.12 0.40 0.20 0.50 0.25 1.00 0.50 2.00 1.00 2.50 1.25 4.00 2.00 5.00 2.50 10.0 5.00 20.0 10.0 20.0 10.0 40.0 20.0 50.0 25.0 Minimum P.W. (ns) 10.0 10.0 10.0 10.0 10.0 10.0 10.0 15.0 24.0 42.0 15.0 15.0 15.0 Maximum Pulse Width 1.05 1.68 2.10 4.19 8.39 10.5 16.8 21.0 41.9 83.9
NOTES: increment between 0.25 shown also available standard device. Some restrictions apply dash numbers greater than application notes more details. 2006 Data Delay Devices
#06007
5/8/2006
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
3D7622
APPLICATION NOTES
GENERAL INFORMATION
Figure illustrates main functional blocks 3D7622. Since 3D7622 CMOS design, unused input pins must returned well-defined logic levels, Ground. pulse generator architecture comprised number delay cells, which controlled bits address, oscillator counter, which controlled bits address. Each device individually trimmed maximum accuracy linearity throughout address range. change pulse width from address setting next called increment, LSB. nominally equal device dash number. minimum pulse width, achieved setting address zero, called inherent pulse width. dash numbers larger than bits invalid, address loaded must therefore multiple (ie, 128, 192, etc). When used this manner, device essentially 16-bit generator, with effective increment equal times dash number. best performance, essential that power supply adequately bypassed filtered. addition, power should impedance construction possible. Power planes preferred. Also, signal traces should kept short possible. inherent width, tinc nominal increment. very similar INL, simpler calculate. most dash numbers, relative error less than every address (see Table absolute error defined follows: eabs (tinh addr tinc) where tinh nominal inherent delay. absolute error limited whichever greater, every address. inherent pulse width error deviation inherent width from nominal value. limited whichever greater.
PULSE WIDTH STABILITY
characteristics CMOS integrated circuits strongly dependent power supply temperature. 3D7622 utilizes novel compensation circuitry minimize performance variations induced fluctuations power supply and/or temperature. With regard stability, output pulse width 3D7622 given address, addr, split into components: inherent pulse width (tinh) relative pulse width (tPW tinh). These components exhibit very different stability coefficients, both which must considered very critical applications. thermal coefficient relative pulse width limited ±250 PPM/C, which equivalent variation, over -40C operating range, ±1.5% from room-temperature pulse width. This holds dash numbers. thermal coefficient inherent pulse width nominally +10ps/C dash numbers less than +15ps/C other dash numbers. power supply sensitivity relative pulse width ±0.5% over 4.75V 5.25V operating range, with respect pulse width nominal 5.0V power supply. This holds dash numbers. sensitivity inherent pulse width nominally -1ps/mV dash numbers. should also noted that also adversely affected thermal supply variations, particularly MSL/LSB crossovers (ie, 128, etc).
PULSE WIDTH ACCURACY
There number ways characterizing pulse width accuracy programmable pulse generator. first differential nonlinearity (DNL), also referred increment error. defined deviation increment given address from nominal value. most dash numbers, within every address (see Table Pulse Width Step). integrated nonlinearity (INL) determined first constructing least-squares best straight line through pulse-width-versusaddress data. then deviation given width from this line. dash numbers, within every address. relative error defined follows: erel (tPW tinh) addr tinc where addr address, measured width this address, tinh measured
#06007
5/8/2006
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
3D7622
APPLICATION NOTES (CONT'D)
TRIGGER RESET TIMING
Figure shows timing diagram device when reset input (RES) used. this case, pulse triggered rising edge TRIG signal ends time determined address loaded into device. While pulse active, additional triggers occurring ignored. Once pulse ended, after short recovery time, next trigger recognized. Figure shows timing case where reset issued before pulse ended. Again, there short recovery time required before next trigger occur. shown figure, most address information next pulse loaded while current pulse active. only falling-edge that device adjusts pulse width setting. other words, device controller does need wait current pulse before beginning address update sequence. This save considerable amount time certain applications. data shifted into serial data input (SI), previous contents 22-bit input register shifted serial output (SO) MSB-to-LSB order. This allows cascading multiple devices connecting preceding device succeeding device, illustrated Figure total number serial data bits cascade configuration must times number units, each group bits must transmitted MSB-to-LSB order.
ADDRESS UPDATE
While observing data setup (tDS) data hold (tDH) requirements, timing data loaded MSBto-LSB order rising edge clock (SC) while enable (AE) high, shown Figure falling edge activates pulse width value, which reflected output upon next trigger.
TRIGGER RESET
INPUT LOGIC
DELAY LINE
OSCILLATOR/ COUNTER
OUTPUT LOGIC
OUTB PULSE
ADDR ENABLE
22-BIT LATCH 22-BIT INPUT REGISTER
SERIAL SERIAL
SERIAL
Figure Functional block diagram
#06007
5/8/2006
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
3D7622
APPLICATION NOTES (CONT'D)
TRIG
OUTB
tRTO
Figure Timing Diagram (RES=0)
TRIG
tRTR
OUTB
Figure Timing Diagram (with reset)
TRIG
Figure Address Update
3D3622
3D3622
3D3622
FROM SERIAL SOURCE
NEXT DEVICE
Figure Cascading Multiple Devices
#06007
5/8/2006
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
3D7622
DEVICE SPECIFICATIONS
TABLE ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage Input Voltage Input Current Storage Temperature Lead Temperature SYMBOL TSTRG TLEAD -0.3 -0.3 VDD+0.3 UNITS NOTES
TABLE ELECTRICAL CHARACTERISTICS
(-40C 85C, 4.75V 5.25V) PARAMETER Static Supply Current* High Level Input Voltage Level Input Voltage High Level Input Current Level Input Current High Level Output Current Level Output Current Output Rise Fall Time SYMBOL -4.0 12.0 UNITS NOTES
-35.0 15.0
4.75V 2.4V 4.75V 0.4V
*IDD(Dynamic) where: Average capacitance load/output (pf) Trigger frequency (GHz)
Input Capacitance typical Output Load Capacitance (CLD)
TABLE ELECTRICAL CHARACTERISTICS
(-40C 85C, 4.75V 5.25V) PARAMETER Trigger Width Trigger Inherent Delay Output Pulse Width Re-trigger Time Reset Width Reset Output Reset Next Trigger High First Clock Edge High Serial Output Valid Serial Clock Width Data Setup Clock Data Hold from Clock Clock Serial Output Last Clock Edge Output Serial Output High-Z Trigger SYMBOL tRTO tRTR UNITS REFER Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
#06007
5/8/2006
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
3D7622
TYPICAL APPLICATIONS
TRIG OUTB
FOUT
SCLK SDAT
3D7622
FOUT (tPW tNOR)
tNOR
FOUT
Figure Programmable Oscillator
TRIG
OUTB
SETB RESB
D-FF
3D7622 R-Edge Delay
TRIG
OUTB
SETB RESB
SCLK SDAT
3D7622 F-Edge Delay
D-FF
tPWR
tPWF
Figure Programmable Delay Line
#06007
5/8/2006
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
3D7622
SILICON DEVICE AUTOMATED TESTING
TEST CONDITIONS
INPUT: Ambient Temperature: 25oC Supply Voltage (Vcc): 5.0V 0.1V Input Pulse: High 3.0V 0.1V 0.0V 0.1V Source Impedance: Max. Rise/Fall Time: Max. (measured between 0.6V 2.4V Pulse Width: PWIN 20ns Period: PERIN Prog'd Pulse Width OUTPUT: Rload: Cload: Threshold: 1.5V (Rising Falling)
Device Under Test
Digital Scope
NOTE: above conditions test only restrict operation device.
COMPUTER SYSTEM
PRINTER
PULSE GENERATOR TRIG TRIG DEVICE UNDER TEST (DUT) TRIG DIGITAL SCOPE/ TIME INTERVAL COUNTER
Figure Test Setup
PERIN tRISE INPUT SIGNAL
tFALL
OUTPUT SIGNAL
Figure Timing Diagram
#06007
5/8/2006
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013

22-BIT PROGRAMMABLE PULSE GENERATOR (SERIES 3D7622 SERIAL INTERFACE)

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