Powerful Instructions (Most Executed Single Clock Cycle) Power Idle Po

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Powerful Instructions (Most Executed Single Clock Cycle) Power Idle Po

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High-performance, Low-power secureAVREnhanced RISC Architecture
Powerful Instructions (Most Executed Single Clock Cycle) Power Idle Power-down Modes Bond Locations Conforming 7816-2 Protection 6000V Operating Ranges: 5.5V Compliant with GSM, 3GPP 2000 Specifications; Industry Compatible Available Wafers, Modules, Industry-standard Packages
Memory
Bytes Program Memory Bytes EEPROM, Including Bytes 384-byte Bit-addressable Area
64-byte Program Erase Program Erase Typically More than 500,000 Write/Erase Cycles Temperature 25oC Years Data Retention Bytes Bytes Dedicated Atmel's Crypto Library
Secure Microcontroller Smart Cards AT90SC 9618RCT Summary
Peripherals
7816 Controller
kbps Compliant with Protocols Port Programmable Internal Oscillator AdvXand Internal Clock) 16-bit Timers Random Number Generator (RNG) 2-level, 7-vector Interrupt Controller Hardware Triple Resistant Checksum Accelerator Engine (Compliant with ISO/IEC 3309) 32-Bit Cryptographic Accelerator (AdvX) Public Operations RSA, DSA, ECC, Diffie-Hellman
Security
Dedicated Hardware Protection Against SPA/DPA Attacks Advanced Protection Against Physical Attack, Including Active Shield Environmental Protection Systems Voltage Monitor Frequency Monitor Temperature Monitor Light Protection Secure Memory Management/Access Protection (Supervisor Mode)
Development Tools
Voyager Emulation Platform (ATV4) Support Software Development Embedded Workbench® V3.20 Debugger Atmel's Studio® Version 4.07
Above
Software Libraries Application Notes
6512AS-SMIC-28Feb05
Note: This summary document. complete document will available under NDA. more information, please contact your local Atmel sales office.
Description
AT90SC9618RCT low-power, high-performance, 8/16-bit microcontroller with program memory, EEPROM data memory crypto-accelerator, based secureAVR enhanced RISC architecture. executing powerful instructions single clock cycle, AT90SC9618RCT achieves throughputs close MIPS MHz. Harvard architecture includes general purpose working registers directly connected ALU, allowing independent registers accessed single instruction executed clock cycle. AT90SC9618RCT uses secureAVR that allows linear addressing bytes code bytes data well number functional security features. AT90SC9618RCT includes bytes Atmel's high density, volatile memory. crypto engine featured AT90SC series AdvX, 32-bit accelerator dedicated perform fast encryption authentication functions. Additional security features include power frequency protection logic, logical scrambling program data addresses, Power Analysis countermeasures memory accesses controlled supervisor mode. Figure shows AT90SC9618RCT secureAVR Enhanced RISC Architecture. Figure AT90SC9618RCT secureAVR Enhanced RISC Architecture
Data 8-bit EEPROM User Memory ATMEL Program Memory Instruction Register Instruction Decoder Control Lines Status Register General Purpose Registers
Access Control
Secure Control
AdvX CryptoCoprocessor Access Control
Data Memory Interrupt Unit
7816 Controller 7816 Port Timer Reset Circuit Counter measures Checksum Accelerator
IN/OUT0
AT90SC9618RCT
6512AS-SMIC-28Feb05
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6512AS-SMIC-28Feb05

Powerful Instructions (Most Executed Single Clock Cycle) Power Idle Po

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