Powerful Instructions (Most Executed Single Clock Cycle) Power Idle Po

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Powerful Instructions (Most Executed Single Clock Cycle) Power Idle Po

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High-performance, Low-power secureAVREnhanced RISC Architecture
Powerful Instructions (Most Executed Single Clock Cycle) Power Idle Power-down Modes Bond Locations Conforming 7816-2 Protection 4000V Operating Ranges: 1.62 5.5V Compliant with GSM, 3GPP 2000 Specifications; Industry Compatible Available Wafers, Modules, Industry-standard Packages
Memory
288K Bytes Program Memory 144K Bytes EEPROM, Including Bytes 384-byte Bit-addressable Area
128-byte Program Erase Program Erase Typically More than 500,000 Write/Erase Cycles Temperature 25oC Years Data Retention EEPROM Erase Only Mode Write EEPROM With Without Autoerase Bit-write Mode (Optional) Full Partial Page Erase Mode (Optional) Block Erase Mode (Optional) Bytes
Secure Microcontroller Smart Cards AT90SC 288144RT Summary
Peripherals
7816 Controller
625kbps Compliant with Protocols Port Programmable Internal Oscillator ROM) 16-bit Timers Random Number Generator (RNG) 2-level, 7-vector Interrupt Controller Hardware Triple (DPA Resistant) Checksum Accelerator Engine (Compliant with ISO/IEC 3309)
Security
Dedicated Hardware Protection Against SPA/DPA Attacks Protection Against Physical Attack Environmental Protection Systems Voltage Monitor Frequency Monitor Light Protection Secure Memory Management/Access Protection (Supervisor Mode)
Development Tools
Voyager Emulation Platform (ATV2 Standard) Support Software Development Embedded Workbench® V3.20c Debugger Atmel's Studio® Version 4.07
Above
Software Libraries Application Notes
6509AS-SMIC-30Mar05
Note: This summary document. complete document will available under NDA. more information, please contact your local Atmel sales office.
Description
AT90SC288144RT low-power, high-performance, 8/16-bit microcontroller with flexible program memory, EEPROM data memory, based secureAVR enhanced RISC architecture. executing powerful instructions single clock cycle, AT90SC288144RT achieves throughputs close MIPS MHz. Harvard architecture includes general-purpose working registers directly connected ALU, allowing independent registers accessed single instruction executed clock cycle. AT90SC288144RT uses secureAVR that allows linear addressing bytes code bytes data well number functional security features. ability EEPROM code space allows parts program memory reprogrammed in-system. This technology combined with versatile 8/16-bit monolithic chip provides highly flexible cost-effective solution many smart card applications. AT90SC288144RT benefits advanced EEPROM functions Mode), also configured offer compatibility with modes from previous product generations. Additional security features include power frequency protection logic, logical scrambling program data addresses, Power Analysis countermeasures memory accesses controlled supervisor mode. block diagram AT90SC288144RT shown Figure Figure AT90SC288144RT secureAVR Enhanced RISC Architecture
Data 8-bit EEPROM User Memory Program Memory Instruction Register Instruction Decoder Control Lines Counter measures Checksum Accelerator General Purpose Registers
Access Control
Data Memory Interrupt Unit Access Control 7816 Controller 7816 Port Timer
Secure Control
IN/OUT0
Reset Circuit
Status Register
AT90SC288144RT
6509AS-SMIC-30Mar05
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6509AS-SMIC-30Mar05

Powerful Instructions (Most Executed Single Clock Cycle) Power Idle Po

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