Powerful Instructions (Most Executed Single Clock Cycle) Power Idle Po

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Powerful Instructions (Most Executed Single Clock Cycle) Power Idle Po

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High-performance, Low-power secureAVREnhanced RISC Architecture
Powerful Instructions (Most Executed Single Clock Cycle) Power Idle Power-down Modes Bond Locations Conforming 7816-2 Protection 6000V Operating Ranges: 5.5V Compliant with GSM, 3GPP 2000 Specifications; Industry Compatible Available Wafers, Modules, Industry-standard Packages
Memory
128K Bytes Program Memory Bytes EEPROM, Including Bytes 384-byte Bit-addressable Area
128-byte Program Erase 1.25ms Program 1.25ms Erase Typically More than 500,000 Write/Erase Cycles Temperature 25oC Years Data Retention EEPROM Erase Only Mode Write EEPROM With Without Autoerase Bytes Bytes Dedicated Atmel's Crypto-library
Secure Microcontroller Smart Cards AT90SC 12836RCT Summary
Peripherals
Port ISO7816 Controller
kbps Compliant with Protocols Programmable Internal Oscillator Cryptographic Accelerator 16-bit Timers Random Number Generator (RNG) 2-level, 8-vector Interrupt Controller 32-bit Cryptographic Accelerator Public Operations Including RSA, DSA, ECC, Diffie-Hellman Hardware Triple Resistant Checksum Accelerator Engine (Compliant with ISO/IEC 3309)
Security
Dedicated Hardware Protection Against SPA/DPA Attacks Advanced Protection Against Physical Attack, Including Active Shield Environmental Protection Systems Voltage Monitor Frequency Monitor Light Protection Temperature Monitor Secure Memory Management/Access Protection (Supervisor Mode)
Development Tools
Voyager Emulation Platform (ATV2 Standard) Support Software Development Systems EWAVR® V3.10 Debugger Atmel's Studio® Version 4.07 Above Software Libraries Application Notes
6508AS-SMIC-17Jun04
Note: This summary document. complete document will available under NDA. more information, please contact your local Atmel sales office.
Description AT90SC12836RCT power, high performance, 8/16-bit microcontroller based secureAVR enhanced RISC architecture, with program memory EEPROM data memory. executing powerful instructions single clock cycle, AT90SC12836RCT achieves throughputs close MIPS MHz. Harvard architecture includes general-purpose working registers directly connected ALU, allowing independent registers accessed single instruction executed clock cycle. AT90SC12836RCT uses secureAVRthis allows linear addressing bytes code bytes data well number functional security features. AT90SC12836RCT includes bytes Atmel's high density, volatile memory. crypto engine featured AT90SC series AdvXTM, 32-bit accelerator dedicated perform fast encryption authentication functions. Additional security features include power frequency protection logic, logical scrambling data addresses, Power Analysis countermeasures memory accesses controlled supervisor mode. Figure shows AT90SC12836RCT block diagram. Figure AT90SC12836RCT secureAVR Enhanced RISC Architecture
Data 8-bit EEPROM User Memory ATMEL Program Memory Instruction Register Instruction Decoder Control Lines Status Register Access Control Access Control General Purpose Registers AdvX CryptoAccelerator Data Memory Interrupt Unit 7816 Controller 7816 Port Timer DES/ Triple Counter Measures Checksum Accelerator Reset Circuit IN/OUT0 Secure Control
AT90SC12836RCT
6508AS-SMIC-17Jun04
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Disclaimer: Atmel Corporation makes warranty products, other than those expressly contained Company's standard warranty which detailed Atmel's Terms Conditions located Company's site. Company assumes responsibility errors which appear this document, reserves right change devices specifications detailed herein time without notice, does make commitment update information contained herein. licenses patents other intellectual property Atmel granted Company connection with sale Atmel products, expressly implication. Atmel's products authorized critical components life support devices systems.
ATMEL AVRstudio registered trademarks Atmel; secureAVR
AdvX
trademarks Atmel.
EWAVR registered trademark Systems Other terms product names trademark others.
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6508AS-SMIC-17Jun04

Powerful Instructions (Most Executed Single Clock Cycle) Power Idle Po

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