AND52 CMOS AND52 5-input gate with drive strength. Truth Tab
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Austria Mikro Systeme International
AND52
CMOS
AND52 5-input gate with drive strength. Truth Table
Capacitance
(pF)
AND52
0.054 0.053 0.059 0.057 0.058
Area
0.95 mils
Power
4.05 with Input Slope [ns] Output Load [pF] with Output Load [pF] Typical Process
Delay [ns] tpd. f(SL, Output Slope [ns] op_sl. f(L) Characteristics 25°C
3.3V
Characteristics
Characteristics Symbol tpdar tpdaf tpdbr tpdbf tpdcr tpdcf tpddr tpddf tpder tpdef op_slar op_slaf op_slbr op_slbf op_slcr op_slcf op_sldr op_sldf op_sler op_slef
Delay Delay Delay Delay Delay Output Slope Output Slope Output Slope Output Slope Output Slope
0.55 0.61 0.60 0.70 0.65 0.79 0.68 0.89 0.68 0.97 0.98 0.71 1.00 0.75 0.97 0.78 0.98 0.81 0.98 0.85
1.91 1.73 2.02 1.84 2.05 1.93 2.01 2.03 2.07 2.08 5.22 3.62 5.30 3.55 5.21 3.57 5.18 3.63 5.27 3.80
2.64 2.28 2.65 2.37 2.69 2.50 2.71 2.61 2.74 2.64 7.31 5.26 7.46 5.06 7.30 5.11 7.30 5.12 7.37 5.06
0.60 0.98 0.64 1.07 0.65 1.17 0.62 1.24 0.59 1.33 0.93 0.71 0.93 0.75 0.96 0.78 0.97 0.81 0.96 0.82
1.96 2.10 2.01 2.18 2.00 2.30 1.98 2.41 1.94 2.49 5.18 3.68 5.27 3.53 5.23 3.61 5.22 3.63 5.22 3.72
2.65 2.64 2.71 2.72 2.69 2.83 2.67 2.93 2.63 3.02 7.47 5.25 7.31 5.05 7.45 5.01 7.46 5.07 7.43 5.05
Sept. 1996
Rev.
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