10-bit analog-to-digital converter MSPS maximum conversion rate less c
|
|
|
Top Searches for this datasheet
High Performance 10-Bit Display Interface AD9981
10-bit analog-to-digital converter MSPS maximum conversion rate less clock jitter MSPS Automated offset adjustment input Power-down dedicated serial register 4:4:4, 4:2:2, output format modes Variable output drive strength Odd/even field detection External clock input Regenerated Hsync output Programmable output high impedance control Hsyncs Vsyncs counter Pb-free package
AUTO OFFSET
AD9981
OUPUT DATA FORMATTER
PR/REDIN1 PR/REDIN0
CLAMP
10-BIT
REDOUT
AUTO OFFSET
Y/GREENIN1 Y/GREENIN0
CLAMP
10-BIT
GREENOUT
AUTO OFFSET
PB/BLUEIN1 PB/BLUEIN0
CLAMP
10-BIT
BLUEOUT
HSYNC1 HSYNC2
DATACK SYNC PROCESSING SOGOUT FIELD HSOUT VSOUT/A0
VSYNC1 VSYNC2
APPLICATIONS
Advanced Plasma display panels LCDTV HDTV graphics processing monitors projectors Scan converters
SOGIN1 SOGIN2 EXTCLK/COAST CLAMP FILT
POWER MANAGEMENT
REFHI SERIAL REGISTER REFLO
04739-001
VOLTAGE REFS
REFCM
Figure
GENERAL DESCRIPTION
AD9981 complete, 10-bit, MSPS, monolithic analog interface optimized capturing YPbPr video graphics signals. MSPS encode rate capability fullpower analog bandwidth supports HDTV video modes graphics resolutions (1024 Hz). AD9981 includes triple with internal reference, PLL, programmable gain, offset, clamp controls. user provides only power supplies analog input. Three-state CMOS outputs powered from AD9981's on-chip generates sample clock from three-level sync (for YPbPr video) horizontal sync (for graphics). Sample clock output frequencies range from MHz. clock jitter less typical MSPS. With internal Coast generation, maintains output frequency absence sync input. 32-step sampling clock phase adjustment provided. Output data, sync, clock phase relationships maintained. auto-offset feature enabled automatically restore signal reference levels automatically calibrate offset differences between three channels. AD9981 also offers full sync processing composite sync sync-ongreen applications. clamp signal generated internally provided user through CLAMP input pin. Fabricated advanced CMOS process, AD9981 provided space-saving, 80-pin, Pb-free, LQFP surface mount plastic package. specified over +70°C temperature range.
Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 2005 Analog Devices, Inc. rights reserved.
AD9981 TABLE CONTENTS
Analog Interface Specifications Absolute Maximum Ratings. Explanation Test Levels. Caution. Configuration Function Descriptions. Design Guide. General Description. Digital Inputs Input Signal Handling. Hsync Vsync Inputs. Serial Control Port Output Signal Handling. Clamping Gain Offset Control. Timing Diagrams. Hsync Timing Coast Timing. Output Formatter Two-Wire Serial Register Map. Detailed 2-Wire Serial Control Register Descriptions Chip Identification Divider Control Clock Generator Control Phase Adjust. Input Gain Input Offset Hsync Controls Vsync Controls Coast Clamp Controls. Control Input Power Control. Output Control Two-Wire Serial Control Port. Data Transfer Serial Interface. Layout Recommendations Outline Dimensions Ordering Guide
REVISION HISTORY
1/05-Initial Version: Revision
Rev. Page
AD9981 ANALOG INTERFACE SPECIFICATIONS
DAVDD clock maximum conversion rate full temperature range 70°C. Table Electrical Characteristics
AD9981KSTZ-801 Parameter RESOLUTION Number Bits Size ACCURACY Differential Nonlinearity MSPS Conversion Rate Differential Nonlinearity MSPS Conversion Rate Integral Nonlinearity MSPS Conversion Rate Integral Nonlinearity MSPS Conversion Rate Missing Codes ANALOG INPUT Input Voltage Range Minimum Maximum Gain Tempco Input Bias Current Input Full-Scale Matching Offset Adjustment Range SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate Clock Data Skew tSKEW tBUFF tSTAH tDHO tDAL tDAH tDSU tSTASU tSTOSU Maximum Clock Rate Minimum Clock Rate Jitter Sampling Phase Tempco DIGITAL INPUTS3 Input Voltage, High (VIH) Input Voltage, (VIL) Input Current, High (IIH) Input Current, (IIL) Input Capacitance Temp Test Level 0.098 AD9981KSTZ-952 0.098 Unit Bits full scale
25°C Full 25°C Full 25°C Full 25°C Full 25°C
±1.4 ±1.4
±3.75 ±5.0
Guaranteed
2.75 1.75 ±1.4 ±3.75 ±1.4 ±5.0 ±2.7 ±4.75 ±3.7 ±8.6 Guaranteed
Full Full 25°C 25°C Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 25°C Full Full Full Full Full Full 25°C
-0.5
ppm/°C MSPS MSPS ps/°C
-0.5
Rev. Page
AD9981
AD9981KSTZ-801 Parameter DIGITAL OUTPUTS Output Voltage, High (VOH) Output Voltage, (VOL) Duty Cycle, DATACK Output Coding POWER SUPPLY Supply Voltage Supply Voltage Supply Voltage DAVD Supply Voltage Supply Current (VD) Supply Current (VDD)4 IPVD Supply Current (PVD) IDAVD Supply Current (DAVD) Total Power Dissipation Power-Down Supply Current Power-Down Dissipation DYNAMIC PERFORMANCE Analog Bandwidth, Full Power Crosstalk THERMAL CHARACTERISTICS Junction-to-Case Thermal Resistance Junction-to-Ambient Thermal Resistance Temp Full Full Full Test Level Binary 3.13 3.47 3.47 3.13 Binary 3.47 3.47 AD9981KSTZ-952 Unit
Full Full Full Full 25°C 25°C 25°C 25°C Full Full Full 25°C Full
1070
1114
°C/W °C/W
Output drive strength used parameters. Output drive strength used parameters. Digital inputs are: HSYNC0, HSYNC1, VSYNC0, VSYNC1, SDA, SCL, EXTCLK, CLAMP, PWRDN, COAST DATACK load data load
Rev. Page
AD9981 ABSOLUTE MAXIMUM RATINGS
Table
Parameter DAVDD Analog Inputs REFHI REFCM REFLO Digital Inputs Digital Output Current Operating Temperature Storage Temperature Maximum Junction Temperature Rating 1.98 1.98 -25°C +85°C -65°C +150°C 150°C
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only functional operation device these other conditions outside those indicated operation sections this specification implied. Exposure absolute maximum ratings extended periods affect device reliability.
EXPLANATION TEST LEVELS Test Level
100% production tested.
100% production tested 25°C sample tested specified temperatures. III. Sample tested only. Parameter guaranteed design characterization testing. Parameter typical value only. 100% production tested 25°C; guaranteed design characterization testing.
CAUTION
(electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although this product features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
Rev. Page
AD9981 CONFIGURATION FUNCTION DESCRIPTIONS
EXTCLK/COAST (3.3V) (1.8V) (1.8V) (1.8V) BLUE BLUE BLUE
CCLAMP
HSYNC0
HSYNC1
VSYNC0
VSYNC1
(3.3V) BAIN0 BAIN1 (3.3V) GAIN0 SOGIN0 (3.3V)
FILT
BLUE BLUE BLUE BLUE BLUE BLUE BLUE (3.3V) GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN DAVDD (1.8)
04739-002
AD9981
VIEW (Not Scale)
GAIN1 SOGIN1 (3.3V) RAIN0 RAIN1 PWRDN REFLO REFCM REFHI
FIELD
(3.3V)
VSOUT/A0
(3.3V)
SOGOUT
HSOUT
DATACK
Figure View (Pins Down)
Table Complete Pinout List
Type Inputs Mnemonic RAIN0 RAIN1 GAIN0 GAIN1 BAIN0 BAIN1 HSYNC0 HSYNC1 VSYNC0 VSYNC1 SOGIN0 SOGIN1 EXTCK CLAMP COAST PWRDN [9:0] GREEN [9:0] BLUE [9:0] DATACK Function Channel Analog Input Converter Channel Analog Input Converter Channel Analog Input Converter Channel Analog Input Converter Channel Analog Input Converter Channel Analog Input Converter Horizontal Sync Input Channel Horizontal Sync Input Channel Vertical Sync Input Channel Vertical Sync Input Channel Input Sync-on-Green Channel Input Sync-on-Green Channel External Clock Input External Clamp Input Signal External Coast Signal Input Power-Down Control Outputs Converter Outputs Converter Outputs Converter Data Output Clock
Rev. Page
Outputs
Value CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
AD9981
Type Mnemonic HSOUT VSOUT SOGOUT FIELD FILT REFLO REFCM REFHI DAVDD Function Hsync Output Clock (Phase-Aligned with DATACK) Vsync Output Clock Sync-on-Green Slicer Output Odd/Even Field Output Connection External Filter Components Internal Connection External Capacitor Input Amplifier Connection External Capacitor Input Amplifier Connection External Capacitor Input Amplifier Analog Power Supply Output Power Supply Power Supply Digital Logic Power Supply Ground Value CMOS CMOS CMOS 3.3V CMOS
References
Power Supply
Control
Serial Port Data Serial Port Data Clock (100 maximum) Serial Port Address Input
CMOS CMOS CMOS
EXTCLK COAST share same pin. VSOUT share same pin.
Rev. Page
AD9981
Table Function Descriptions
INPUTS RAIN0 GAIN0 BAIN0 RAIN1 GAIN1 BAIN1 Description Analog Input Channel Analog Input Green Channel Analog Input Blue Channel Analog Input Channel Analog Input Green Channel Analog Input Blue Channel High impedance inputs that accept red, green, blue channel graphics signals, respectively. three channels identical used colors, colors assigned convenient reference. They accommodate input signals ranging from full scale. Signals should ac-coupled these pins support clamp operation. Horizontal Sync Input Channel Horizontal Sync Input Channel These inputs receive logic signal that establishes horizontal timing reference provides frequency reference pixel clock generation. logic sense this automatically determined chip manually controlled Serial Register 0x12, Bits [5:4] (Hsync polarity). Only leading edge Hsync used PLL; trailing edge used clamp timing. When Hsync polarity falling edge Hsync used. When Hsync Polarity rising edge active. input includes Schmitt trigger noise immunity. Vertical Sync Input Channel Vertical Sync Input Channel These inputs vertical sync provide timing information generation field (odd/even) internal Coast generation. logic sense this automatically determined chip manually controlled Serial Register 0x14, Bits [5:4] (Vsync polarity). Sync-on-Green Input Channel Sync-on-Green Input Channel These inputs provided assist with processing signals with embedded sync, typically green channel. connected high speed comparator with internally generated threshold. threshold level programmed steps voltage between above negative peak input signal. default voltage threshold When connected ac-coupled graphics signal with embedded sync, produces noninverting digital output SOGOUT. This usually composite sync signal, containing both vertical horizontal sync information that must separated before passing horizontal sync signal Hsync processing. When used, this input should left unconnected. more details this function should configured, refer Sync-on-Green section. External Clamp Input (Optional). This logic input used define time during which input signal clamped ground midscale. should exercised when reference level known present analog input channels, typically during back porch graphics signal. CLAMP enabled setting control clamp function (Register 0x18, default When disabled, this ignored clamp timing determined internally counting delay duration from trailing edge Hsync input. logic sense this automatically determined chip controlled clamp polarity Register 0x1B, Bits [7:6]. When used, this left unconnected (there internal pull-down resistor) clamp function programmed Coast Input Clock Generator (Optional). This input used cause pixel clock generator stop synchronizing with Hsync continue producing clock current frequency phase. This useful when processing signals from sources that fail produce Hsync pulses during vertical interval. Coast signal generally required PC-generated signals. logic sense this determined automatically controlled Coast polarity (Register 0x18, Bits [7:6]). When used EXTCLK used, this grounded Coast polarity programmed Input Coast polarity defaults power-up. This shared with EXTCLK function, which does affect Coast functionality. more details EXTCLK, description this section. External Clock. This allows insertion external clock source rather than internally generated, locked clock. EXTCLK enabled programming Register 0x03, This shared with Coast function, which does affect EXTCLK functionality. more details Coast, above description this section. Power-Down Control This used along with Register 0x1E, manual power-down control. manual power-down control selected (Register 0x1E, this used, recommended polarity (Register 0x1E, active high hardwire this ground with resistor.
HSYNC0 HSYNC1
VSYNC0 VSYNC1
SOGIN0 SOGIN1
CLAMP
EXTCLK/COAST
EXTCLK/COAST
PWRDN
Rev. Page
AD9981
REFLO REFCM REFHI FILT Description Input Amplifier Reference. REFLO REFHI connected together through capacitor; REFCM connected through capacitor ground. These used stability input (programmable gain amplifier) circuitry. Figure External Filter Connection. proper operation, pixel clock generator requires external filter. Connect filter shown Figure this pin. optimal performance, minimize noise parasitics this node. more information, Layout Recommendations section. Horizontal Sync Output. reconstructed phase-aligned version Hsync input. Both polarity duration this output programmed serial registers. maintaining alignment with DATACK Data Output, data timing with respect Hsync always determined. Vertical Sync Output. shared with serial port address. This either separated Vsync from composite signal direct pass through Vsync signal. polarity this output controlled serial bit. placement duration modes graphics transmitter duration Register 0x14 Register 0x15. This shared with function, which does affect Vsync Output functionality. more details description Serial Control Port section. Sync-On-Green Slicer Output. This outputs four possible signals (controlled Register 0x1D, Bits [1:0]): SOG, Hsync, regenerated Hsync from filter, filtered Hsync. sync processing block diagram (see Figure view this connected. Other than slicing SOG, output from this gets other additional processing AD9981. Vsync separation performed sync separator. Odd/Even Field Interlaced Video. This output will identify whether current field interlaced signal) even. Serial Port Data I/O. Serial Port Data Clock. Serial Port Address Input shared with VSOUT. This selects serial port device address, allowing Analog Devices parts same serial bus. high impedance external pull-up resistor enables this read power-up high impedance, external pull-down resistor enables this read power-up interfere with VSOUT functionality. more details VSOUT, Data Outputs section this table. Data Output, Channel. Data Output, Green Channel. Data Output, Blue Channel. main data outputs. MSB. delay from pixel sampling time output fixed. When sampling time changed adjusting phase register, output timing shifted well. DATACK HSOUT outputs also moved, timing relationship among signals maintained.
OUTPUTS HSOUT
VSOUT/A0
SOGOUT
FIELD SERIAL PORT VSOUT/A0
DATA OUTPUTS [9:0] GREEN [9:0] BLUE [9:0]
DATA CLOCK OUTPUT DATACK
Data Clock Output. This main clock output signal used strobe output data HSOUT into external logic. Four possible output clocks selected with Register 0x20, Bits [7:6]. Three these related pixel clock (pixel clock, phase-shifted pixel clock frequency pixel clock). They produced either internal clock generator EXTCLK synchronous with pixel sampling clock. fourth option data clock output internally generated clock. sampling time internal pixel clock changed adjusting phase register (Register 0x04). When this changed, pixel related DATACK timing also shifted. Data, DATACK, HSOUT outputs moved that timing relationship among signals maintained.
Rev. Page
AD9981
POWER SUPPLY (3.3 (1.8 V-3.3 Description Main Power Supply. These pins supply power main elements circuit. They should quiet filtered possible. Digital Output Power Supply. large number output pins switching high speed MHz) generate power supply transients (noise). These supply pins identified separately from pins, special care taken minimize output noise transferred into sensitive analog circuitry. AD9981 interfacing with lower voltage logic, connected lower supply voltage compatibility. Clock Generator Power Supply. most sensitive portion AD9981 clock generation circuitry. These pins provide power clock help user design optimal performance. designer should provide quiet, noise-free power these pins. Digital Input Power Supply. This supplies power digital logic. Ground. ground return circuitry on-chip. recommended that AD9981 assembled single solid ground plane, with careful attention ground current paths.
(1.8
DAVDD (1.8
Rev. Page
AD9981 DESIGN GUIDE
GENERAL DESCRIPTION
AD9981 fully integrated solution capturing analog YPbPr signals digitizing them display advanced TVs, flat panel monitors, projectors, other types digital displays. Implemented high-performance CMOS process, interface capture signals with pixel rates MHz. AD9981 includes necessary input buffering, signal restoration (clamping), offset gain (brightness contrast) adjustment, pixel clock generation, sampling phase control, output data formatting. controls programmable two-wire serial interface (I2C®). Full integration these sensitive analog functions makes system design straightforward less sensitive physical electrical environment. With typical power dissipation less than operating temperature range 70°C, device requires special environmental considerations. slightly providing high quality signal over wider range conditions. Using Fair-Rite #2508051217Z0-High Speed, Signal Chip Bead Inductor circuit shown Figure gives good results most applications.
INPUT 47nF RAIN GAIN BAIN
Figure Analog Input Interface Circuit
HSYNC VSYNC INPUTS
interface also accepts Hsync Vsync signals, which used generate pixel clock, clamp timing, Coast field information. These either sync signal directly from graphics source, preprocessed CMOS level signal. Hsync input includes Schmitt trigger buffer immunity noise signals with long rise times. typical PC-based graphic systems, sync signals simply TTL-level drivers feeding unshielded wires monitor cable. such, termination required.
DIGITAL INPUTS
digital inputs AD9981 operate CMOS levels. following digital inputs tolerant (Applying them will cause damage.): HSYNC0, HSYNC1, VSYNC0, VSYNC1, SOGIN0, SOGIN1, SDA, CLAMP.
SERIAL CONTROL PORT
serial control port designed logic; however, tolerant logic signals.
INPUT SIGNAL HANDLING
AD9981 high-impedance analog input pins red, green, blue channels. They accommodate signals ranging from p-p. Signals typically brought onto interface board with DVI-I connector, 15-pin connector, connectors. AD9981 should located close possible input connector. Signals should routed using matched-impedance traces (normally input pins. input pins signal should resistively terminated signal ground return) capacitively coupled AD9981 inputs through capacitors. These capacitors form part restoration circuit. ideal world perfectly matched impedances, best performance obtained with widest possible signal bandwidth. wide bandwidth inputs AD9981 (200 MHz) continuously track input signal moves from pixel level next digitize pixel during long, flat pixel time. many systems, however, there mismatches, reflections, noise, which result excessive ringing distortion input waveform. This makes more difficult establish sampling phase that provides good image quality. been shown that small inductor series with input effective rolling input bandwidth
OUTPUT SIGNAL HANDLING
digital outputs designed operate from (VDD).
CLAMPING
Clamping
properly digitize incoming signal, offset input must adjusted range on-board ADCs. Most graphics systems produce signals with black ground white approximately 0.75 However, sync signals embedded graphics, sync often ground black then white approximately Some common line amplifier boxes emitterfollower buffers split signals increase drive capability. This introduces offset signal, which must removed proper capture AD9981. clamping identify portion (time) signal when graphic system known producing black. offset then introduced that results producing black output (Code 0x00) when known black input present. offset then remains place when other signal levels processed, entire signal shifted eliminate offset errors.
Rev. Page
04739-003
AD9981
most graphics systems, black transmitted between active video lines. With displays, when electron beam completed writing horizontal line screen right side), beam deflected quickly left side screen (called horizontal retrace) black signal provided prevent beam from disturbing image. systems with embedded sync, blacker-than-black signal (Hsync) produced briefly signal that time begin retrace. Because input black level this time, important avoid clamping during Hsync. Fortunately, there virtually always period following Hsync, called `back porch', where good black reference provided. This time when clamping should done. clamp timing established simply exercising CLAMP appropriate time with clamp source (Register 0x18, polarity this signal clamp polarity (Register 0x1B, Bits [7:6]). simpler method clamp timing employs AD9981 internal clamp timing generator. clamp placement register (Register 0x19) programmed with number pixel periods that should pass after trailing edge Hsync before clamping starts. second register, clamp duration, (Register 0x1A) sets duration clamp. These both 8-bit values, providing considerable flexibility clamp generation. clamp timing referenced trailing edge Hsync because, though Hsync duration vary widely, back porch (black reference) always follows Hsync. good starting point establishing clamping clamp placement 0x04 (providing pixel periods graphics signal stabilize after sync) clamp duration 0x28 (giving clamp pixel periods reestablish black reference). Clamping accomplished placing appropriate charge external input coupling capacitor. value this capacitor affects performance clamp. small, there will significant amplitude change during horizontal line time (between clamping intervals). capacitor large, then will take excessively long clamp recover from large change incoming signal offset. recommended value results recovering from step error within lines with clamp duration pixel periods signal. Clamping midscale rather than ground accomplished setting clamp select bits serial register. Each three converters selection that they independently clamped either midscale ground. These bits located Register 0x18, Bits [3:1]. midscale reference voltage internally generated each converter.
GAIN OFFSET CONTROL
AD9981 contains three programmable gain amplifiers (PGAs), each three analog inputs. range sufficient accommodate input signals with inputs ranging from full scale. gain three 9-bit registers (red gain [0x05, 0x06], green gain [0x07, 0x08], blue gain [0x09, 0x0A]). each these registers, gain setting corresponds highest gain, while gain setting corresponds lowest gain. Note that increasing gain setting results image with less contrast. offset control shifts analog input, resulting change brightness. Three 11-bit registers (red offset [0x0B, 0x0C], green offset [0x0D, 0x0E], blue offset [0x0F, 0x10]) provide independent settings each channel. Note that function offset register depends whether auto-offset enabled (Register 0x1B, manual offset used, nine bits offset registers (for channel Register 0x0B, Bits [6:0] plus Register 0x0C, Bits [7:6]) control absolute offset added channel. offset control provides ±255 LSBs adjustment range, with offset corresponding output code.
Automatic Offset
addition manual offset adjustment mode, AD9981 also includes circuitry automatically calibrate offset each channel. monitoring output each during back porch input signals, AD9981 self-adjust eliminate offset errors channels offset errors present incoming graphics video signals. activate auto-offset mode, Register 0x1B, Next, target code registers (0x0B through 0x10) must programmed. values programmed into target code registers should output code desired from AD9981 during back porch reference time. example, signals, three registers would normally programmed Code while YPbPr signals green channel normally Code blue channels 512. target code registers have bits channel twos complement format. This allows value between -1024 +1023 programmed. Although value this range programmed, AD9981's offset range able reach every value. Intended target code values range from (but limited -160 +160 when ground clamping, +350 +670 when midscale clamping. Note that target code valid.
YPbPr Clamping
YPbPr graphic signals slightly different from signals that reference level (black level signals) color difference signals midpoint video signal rather than bottom. three inputs composed luminance color difference signals. color difference signals necessary clamp midscale range range (512) rather than bottom range (0), while channel clamped ground.
Rev. Page
AD9981
Negative target codes included order duplicate feature that present with manual offset adjustment. benefit that being mimicked ability easily adjust brightness display. setting target code value that does correspond ideal range, result image that either brighter darker. target code higher than ideal results brighter image, while target code lower than ideal results darker image. ability program target code gives large degree freedom flexibility. While most cases channels either 512, flexibility select other values allows possibility inserting intentional skews between channels. also allows range skewed that voltages outside normal range digitized. example, setting target code allows sync tip, which normally below black level, digitized evaluated. internal logic auto-offset circuit requires data clock cycles perform function. This operation executed immediately after clamping pulse. Therefore, important clamping pulse signal least data clock cycles before active video. This true whether using AD9981's internal clamp circuit external clamp signal. autooffset function programmed continuously one-time basis (see auto-offset hold, Register 0x2C, continuous mode, update frequency programmed (Register 0x1B, Bits [4:3]). Continuous operation with updates every Hsyncs recommended. guideline basic auto-offset operation shown Table Table Table Auto-Offset Register Settings
Register 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x18, Bits [3:1] 0x1B, [5:3] Value 0x00 0x80 0x00 0x80 0x00 0x80 Comments Sets target Must written Sets green target Must written Sets blue target Must written Sets red, green, blue channels ground clamp Selects update rate enables auto-offset.
Sync-on-Green
sync-on-green input operates steps. First, sets baseline clamp level incoming video signal with negative peak detector. Second, sets sync trigger level programmable (Register 0x1D, Bits [7:3]) level (typically above negative peak. sync-on-green input must ac-coupled green analog input through capacitor. value capacitor must ±20%. sync-on-green used, this connection required. sync-on-green signal always negative polarity.
47nF RAIN 47nF BAIN 47nF GAIN
04739-004
Figure Typical Input Configuration
Reference Bypassing
REFLO REFHI connected each other capacitor. REFCM connected ground capacitor. These references used input circuitry.
REFHI 10µF REFLO 10µF REFCM
04739-014
Figure Input Amplifier Reference Capacitors
Clock Generation
used generate pixel clock. Hsync input provides reference frequency PLL. voltagecontrolled oscillator (VCO) generates much higher pixel clock frequency. pixel clock divided divide value (Register 0x01 Register 0x02) phase-compared with Hsync input. error used shift frequency maintain lock between signals. stability this clock very important element providing clearest most stable image. During each pixel time, there period when signal slewing from pixel amplitude settling value. Then there time when input voltage stable, before signal must slew value (see Figure ratio slewing time stable time function bandwidth graphics bandwidth transmission system (cable termination). also function overall pixel rate. Clearly, dynamic characteristics system remain fixed, then slewing settling time likewise fixed. This time must subtracted from total pixel period, leaving stable period. higher pixel frequencies, total cycle time shorter stable pixel time also becomes shorter.
Table PbPr Auto-Offset Register Settings
Register 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x18 Bits [3:1] 0x1B, [5:3] Value 0x40 0x00 0x00 0x80 0x40 0x00 Comments Sets (red) target Must written Sets (green) target Must written Sets (blue) target Must written Sets midscale clamp ground clamp Selects update rate enables auto-offset.
Rev. Page
AD9981
PIXEL CLOCK INVALID SAMPLE TIMES
range register sets this operating range. frequency ranges four regions shown Table Table Frequency Ranges
Pixel Clock Range (MHz) 10-21 21-42 42-84 84-95 KVCO Gain (MHz/V)
Figure Pixel Sampling Times
04739-005
jitter clock reduces precision with which sampling time determined must also subtracted from stable pixel time. Considerable care been taken design AD9981's clock generation circuit minimize jitter. clock jitter AD9981 less total pixel time operating modes, making reduction valid sampling time jitter negligible. characteristics determined loop filter design, charge pump current, range setting. loop filter design illustrated Figure Recommended settings range charge pump current VESA standard display modes listed Table
1.5k
04739-006
3-Bit Charge Pump Current Register. This register varies current that drives low-pass loop filter. possible current values listed Table
Table Charge Pump Current/Control Bits
Current (µA) 1500
80nF
FILT
Figure Loop Filter Detail
Four programmable registers provided optimize performance PLL. These registers 12-Bit Divisor Register. input Hsync frequencies accommodate Hsync long product Hsync divisor falls within operating range VCO. multiplies frequency Hsync signal, producing pixel clock frequencies range MHz. divisor register controls exact multiplication factor. This register value between 4095 long output frequency within range. 2-Bit Range Register. improve noise performance AD9981, operating frequency range divided into four overlapping regions.
5-Bit Phase Adjust Register. phase generated sampling clock shifted locate optimum sampling point within clock cycle. phase adjust register provides phase-shift steps 11.25° each. Hsync signal with identical phase shift available through HSOUT pin. Phase adjust still available external pixel clock used. COAST internal Coast used allow continue same frequency absence incoming Hsync signal during disturbances Hsync (such from equalization pulses). This used during vertical sync period other time that Hsync signal unavailable. polarity Coast signal through Coast polarity register (Register 0x18, Bits [6:5]). Also, polarity Hsync signal through Hsync polarity register (Register 0x12, Bits [5:4]). both Hsync Coast, value active high. internal Coast function driven Vsync signal, which typically time when Hsync signals disrupted with extra equalization pulses.
Rev. Page
AD9981
Table Recommended Range Charge Pump Current Settings Standard Display Formats Refresh Rate Horizontal Frequency Pixel Rate (kHz) (MHz) Divider Standard Resolution (Hz)
31.500 37.700 37.500 43.300 35.100 37.900 48.100 46.900 53.700 48.400 56.500 60.000 64.000 68.300 15.750 31.470 15.625 31.250 45.000 33.750 33.750 25.175 31.500 31.500 36.000 36.000 40.000 50.000 49.500 56.250 65.000 75.000 78.750 85.500 94.500 13.510 27.000 13.500 27.000 74.250 74.250 74.250 1024 1056 1040 1056 1048 1344 1328 1312 1336 1376 1650 2200 2200
VCORNGE
Current
SVGA
1024
480i 480p 576i 576p 720p 1035i 1080i
Rev. Page
AD9981
CHANNEL SELECT
CHANNEL
Preliminary Technical Data
HSYNC SELECT
HSYNC0 ACTIVITY DETECT HSYNC1 ACTIVITY DETECT SOGIN0 ACTIVITY DETECT SOGIN1 ACTIVITY DETECT POLARITY DETECT POLARITY DETECT
HSYNC
PULSE FILTER FILTERED, RECONSTRUCTED HSYNC
CHANNEL
SOGOUT
SYNC SLICER
POLARITY
SOGOUT
CHANNEL
VSYNC0 ACTIVITY DETECT VSYNC1 ACTIVITY DETECT POLARITY DETECT POLARITY DETECT
SYNC PROCESSOR POLARITY VSYNC VSYNCOUT
HSYNC/VSYNC HSYNC COAST COAST COAST
COUNT R26,
POLARITY CLOCK GENERATOR POLARITY
VSYNCOUT
DATACK
04739-013
AD9981
Figure Sync Processing Block Diagram
Sync Processing
inputs sync processing section AD9981 combinations digital Hsyncs Vsyncs, analog sync-ongreen, sync-on-Y signals, optional external Coast signal. From these signals generates precise, jitter-free less MHz) clock from PLL; odd-/even-field signal; Hsync Vsync signals; count Hsyncs Vsync; programmable output. main sync processing blocks sync slicer, sync separator, Hsync filter, Hsync regenerator, Vsync filter, Coast generator. sync slicer extracts sync signal from green graphics luminance video signal that connected SOGIN input outputs digital composite sync. sync separator's task extract Vsync from composite sync signal, which come from either sync slicer Hsync input. Hsync filter used eliminate extraneous pulses from Hsync SOGIN inputs, outputting clean, low-jitter signal that appropriate mode detection clock generation. Hsync regenerator used recreate clean, although
jitter, Hsync signal that used mode detection counting Hsyncs Vsync. Vsync filter used eliminate spurious Vsyncs, maintain stable timing relationship between Vsync Hsync output signals, generate odd/even field output. Coast generator creates robust Coast signal that allows maintain frequency absence Hsync pulses.
Sync Slicer
purpose sync slicer extract sync signal from green graphics luminance video signal that connected SOGIN input. sync signal extracted step process. First, input clamped negative peak, (typically below black level). Next, signal goes comparator with variable trigger level (set Register 0x1D, Bits [7:3]), nominally 0.128 above clamped level. sync slicer output digital composite sync signal containing both Hsync Vsync information (see Figure
Rev. Page
AD9981
NEGATIVE PULSE WIDTH SAMPLE CLOCKS 700mV MAXIMUM INPUT -300mV -300mV
SOGOUT OUTPUT CONNECTED HSYNCIN
VSYNCOUT FROM SYNC SEPARATOR
Figure Sync Slicer Sync Separator Output
Sync Separator
part sync processing, sync separator's task extract Vsync from composite sync signal. works idea that Vsync signal stays active much longer time than Hsync signal. using digital low-pass filter digital comparator, rejects pulses with small durations (such Hsyncs equalization pulses) only passes pulses with large durations, such Vsync (see Figure threshold digital comparator programmable maximum flexibility. program threshold duration, write value Register 0x11. resulting pulse width digital comparator threshold pulse less than rejected, while pulse greater than passes through. There things keep mind when using sync separator. First, resulting clean Vsync output delayed from original Vsync duration equal digital comparator threshold ns). Second, there some variability multiplier value. maximum variability over operating conditions ±20% (160 ns). Since normal Vsync Hsync pulse widths differ factor about more, variability issue.
counting Hsyncs Vsync. Hsync regenerator high degree tolerance extraneous missing pulses Hsync input, appropriate creating pixel clock jitter. Hsync regenerator runs automatically requires setup operate. Hsync filter requires setting filter window. filter window sets periodic window time around regenerated Hsync leading edge where valid Hsyncs allowed occur. general idea that extraneous pulses sync input occur outside this filter window thus filtered out. order filter window timing, program value into Register 0x23. resulting filter window time times around regenerated Hsync leading edge. Just sync separator threshold multiplier, allow ±20% variance multiplier account operating conditions range). second output from Hsync filter status (0x25, that tells whether extraneous pulses were present incoming sync signal not. Many times extraneous pulses included copy protection purposes, this status used detect that. filtered Hsync (rather than Hsync/SOGIN signal) pixel clock generation controlled Register 0x20, regenerated Hsync (rather than Hsync/ SOGIN signal) sync processing controlled Register 0x20, filtered Hsync regenerated Hsync recommended. Figure illustration filtered Hsync.
Hsync Filter Regenerator
Hsync filter used eliminate extraneous pulses from Hsync SOGIN inputs, outputting clean, low-jitter signal that appropriate mode detection clock generation. Hsync regenerator used recreate clean, although jitter, Hsync signal that used mode detection
Rev. Page
04739-015
COMPOSITE SYNC HSYNCIN
AD9981
HSYNCIN
Preliminary Technical Data
FILTER WINDOW
HSYNCOUT
VSYNC EQUALIZATION PULSES
EXPECTED EDGE
FILTER WINDOW
Figure Sync Processing Filter
Vsync Filter Odd/Even Fields
Vsync filter used eliminate spurious Vsyncs, maintain stable timing relationship between Vsync Hsync output signals, generate odd/even field output. filter works examining placement Vsync with respect Hsync necessary shifting time slightly. goal keep Vsync Hsync leading edges from switching same time, thus eliminating confusion when first line frame occurs. Register 0x14, enables Vsync filter. Vsync filter recommended cases, including interlaced video, required when using Hsyncs Vsync counter. Figure illustrates even/odd field determination situations.
SYNC SEPARATOR THRESHOLD
FIELD QUADRANT HSYNCIN VSYNCIN VSYNCOUT FIELD
FIELD
FIELD
04739-016
FIELD
FIELD
Figure
Rev. Page
04739-017
AD9981
SYNC SEPARATOR THRESHOLD
FIELD QUADRANT HSYNCIN VSYNCIN VSYNCOUT FIELD
FIELD
FIELD
FIELD
With manual power-down control, polarity powerdown must (0x1E, regardless whether used. unused, recommended polarity active high hardwire ground with resistor. power-down mode, there several circuits that continue operate normal. serial register sync detect circuits maintain power that AD9981 woken from power-down state. bandgap circuit maintains power because needed sync detection. sync-on-green SOGOUT functions continue operate because SOGOUT output needed when sync detection performed secondary chip. these circuits require minimal power operate. Typical standby power AD9981 about There options that selected when powerdown. These controlled Bits Register 0x1E. first controls whether SOGOUT high impedance not. most cases, user will place SOGOUT high impedance during normal operation. option SOGOUT high impedance included mainly allow factory testing modes. second option keeps AD9981 powered while placing only outputs high impedance. This option useful when data outputs from chips connected user wants switch instantaneously between two.
EVEN FIELD
Figure Vsync Filter-Odd/Even
Power Management
meet display requirements standby power, AD9981 includes power-down mode. power-down state controlled manually (via Register 0x1E, completely automatically chip. automatic control selected (0x1E, AD9981's decision based status sync detect bits (Register 0x24, Bits either Hsync sync-on-green input detected input, chip powers else powers down. manual control, AD9981 allows flexibility control through both dedicated register bit. dedicated allows hardware watchdog circuit control power-down, while register allows power-down controlled software. Table Power-Down Control Mode Descriptions
Inputs Mode Power-Up Power-Down Power-Up Power-Down Auto Power-Down Control1 Power-Down2
04739-018
Sync Detect3
Powered-On Comments Everything Only serial bus, sync activity detect, SOG, bandgap reference Everything Only serial bus, sync activity detect, SOG, bandgap reference
Auto power-down control Register 0x1E, Power-down controlled OR'ing with Register 0x1E, polarity Register 0x1E, Sync detect determined OR'ing Register 0x24, Bits
Rev. Page
AD9981
TIMING DIAGRAMS
following timing diagrams show operation AD9981.The output data clock signal created that rising edge always occurs between data transitions used
tPER tDCYCLE
DATACK
Preliminary Technical Data
latch output data externally. There pipeline AD9981, which must flushed before valid data becomes available. This means data sets presented before valid data available.
tSKEW
04739-007
DATA HSOUT
Figure Output Timing
DATAIN
HSIN
DATACLK CLOCK CYCLE DELAY DATAOUT CLOCK CYCLE DELAY HSOUT
04739-008
Figure 4:4:4 Timing Mode
DATAIN
HSIN
DATACLK CLOCK CYCLE DELAY YOUT CB/CROUT CLOCK CYCLE DELAY HSOUT
04739-009
PIXEL AFTER HSOUT CORRESONDS BLUE INPUT. EVEN NUMBER PIXEL DELAY BETWEEN HSOUT DATAOUT AD9980).
Figure 4:2:2 Timing Mode
Rev. Page
AD9981
DATAIN
HSIN
DATACLK CLOCK CYCLE DELAY CLOCK CYCLE DELAY HSOUT
NOTES OUTPUT DATACLK DELAYED CLOCK PERIOD REGISTERS. PROJECT DOCUMENT VALUES (FALLING EDGE) (RISING EDGE). 4:2:2 MODE: TIMING IDENTICAL, VALUES CHANGE. GENERAL NOTES DATA DELAY VARY CLOCK CYCLE, DEPENDING PHASE SETTING. ADCs SAMPLE INPUT FALLING EDGE DATACLK. HSYNC SHOWN ACTIVE HIGH (EDGE SHOWN LEADING EDGE).
04739-010
Figure Timing Mode
HSYNC TIMING
Hsync processed AD9981 eliminate ambiguity timing leading edge with respect phasedelayed pixel clock data. Hsync input used reference generate pixel sampling clock. sampling phase adjusted with respect Hsync through full 360° steps phase adjust register optimize pixel sampling time). Display systems Hsync align memory display write cycles, important have stable timing relationship between Hsync output (HSOUT) data clock (DATACK). Three things happen Hsync AD9981. First, polarity Hsync input determined thus known output polarity. known output polarity programmed either active high active (Register 0x12, Second, HSOUT aligned with DATACK data outputs. Third, duration HSOUT pixel clocks) Register 0x13. HSOUT sync signal that should used drive rest display system.
Coast input provided eliminate this problem. asynchronous input that disables input holds clock current frequency. free several lines without significant frequency drift. Coast generated internally AD9981 (see Register 0x18) provided externally graphics controller. When internal Coast selected (Register 0x18, Register 0x14, Bits [7:6] select source), Vsync used basis determining position Coast. internal Coast signal enabled programmed number Hsync periods before periodic Vsync signal (Precoast Register 0x16) dropped programmed number Hsync periods after Vsync (Postcoast Register 0x17). recommended that Vsync filter enabled when using internal Coast function allow AD9981 determine precisely number Hsyncs/Vsync their location. many applications where disruptions occur Coast used, values Precoast Postcoast sufficient avoid most extraneous pulses.
COAST TIMING
most computer systems, Hsync signal provided continuously dedicated wire. these systems, Coast input function unnecessary should used. some systems, however, Hsync disturbed during Vsync. some cases, Hsync pulses disap-pear. other systems, such those that employ composite sync (Csync) signals embedded sync-on-green, Hsync include equalization pulses other distortions during Vsync. avoid upsetting clock generator during Vsync, important ignore these distortions. pixel clock sees extraneous pulses, attempts lock frequency will have changed frequency Vsync period. then takes lines correct Hsync timing recover beginning frame, resulting tearing image display.
OUTPUT FORMATTER
output formatter capable generating several output formats presented data output pins. output formats assignments each format listed Table Also, there several clock options output clock. user select pixel clock, phase-shifted pixel clock, pixel clock, fixed frequency clock test purposes. output clock also inverted. Data output available YCbCr either 4:2:2 4:4:4 selected, secondary channel available. This secondary channel always 4:2:2 allows flexibility having second channel with same video data that utilized another display storage device. Depending choice output modes, primary output pins, pins pins.
Rev. Page
AD9981
Mode Descriptions
4:4:4-All channels come with their data bits same time. Data aligned negative edge clock easy capture. This normal 30-bit output mode 4:4:4 YCbCr. 4:2:2-Red green channels contain 4:2:2 formatted data pins) with data green channel data channel. Data aligned negative edge clock. blue channel contains secondary channel with formatted 4:2:2 data. data edges aligned both edges pixel clock, clock necessary capture data.
Preliminary Technical Data
4:4:4 DDR-This mode puts full 4:4:4 data bits green channels, thus saving pins. first half (RGB [14:0]) 30-bit data sent rising edge second half (RGB [29:15]) sent falling edge. 4:2:2 data sent blue channel, 4:2:2 mode. [29:0] [9:0] [9:0] [9:0], [29:15] [9:0] [9:5] [14:0] [4:0] [9:0]
Table Output Formats
Port 4:4:4 4:2:21 4:4:4 Red/Cr [4:0] [9:0] [9:0] [9:5] Green Green/Y Blue Blue/Cb
4:2:2 4:2:2 Cb,Cr 4:2:2
4:2:2 modes, first item list first pixel after Hsync. Arrows table indicate clock edge. Rising edge clock falling edge
Rev. Page
AD9981 TWO-WIRE SERIAL REGISTER
AD9981 initialized controlled registers, which determine operating modes. external controller employed write read control registers through two-wire serial interface port. Table Control Register
Hexadecimal Address 0x00 0x01 Read Write Read Only Default Value 0110 1001
Bits
Register Name Chip Revision
0x02 0x03
1101 **** 01** **** **00 1*** **** *0** 1000 0*** *100 0000
VCO/CPMP
0x04 0x05
Phase Adjust Gain MSBs
0x06
00** ****
Gain LSBs
0x07
*100 0000
Green Gain MSBs Green Gain LSBs
0x08
00** ****
0x09
*100 0000
Blue Gain MSBs
0x0A
00** ****
Blue Gain LSBs
0x0B
0100 0000
Offset MSBs
0x0C 0x0D
000* **** 0100 0000
Offset LSBs Green Offset MSBs Green Offset LSBs Blue Offset MSBs
0x0E
000* ****
0x0F
0100 0000
0x10
000* ****
Blue Offset LSBs
Description 8-bit register that represents silicon revision level. This register bits [11:4] divider. Larger values mean operates faster rate. This register should loaded first whenever change needed. (This will give more time lock.)1 Bits [7:4] LSBs Divider Word. Links make 12-bit register. Bits [7:6] Range. Selects frequency range. (See description). Bits [5:3] Charge Pump Current. Varies current that drives low-pass filter. (See description). External Clock Enable. Clock Phase Adjustment. Larger values mean more delay. T/32). 7-Bit Channel Gain Control. Controls input range (contrast) each respective channel. Bigger values give less contrast. Linked with Register 0x05 form 9-bit gain that controls input range (contrast) channel. lower value corresponds higher gain. 7-Bit Green Channel Gain Control. Controls input range (contrast) each respective channel. Bigger values give less contrast. Linked Register 0x07 form 9-bit green gain that controls input range (contrast) green channel. lower value corresponds higher gain. 7-Bit Blue Channel Gain Control. Controls input range (contrast) each respective channel. Bigger values give less contrast. Linked Register 0x09 form 9-bit blue gain that controls input range (contrast) blue channel. lower value corresponds higher gain. 8-Bit MSBs Channel Offset Control. Controls offset (brightness) each respective channel. Bigger values decrease brightness. Linked Register 0x0B form 11-bit offset that controls offset (brightness) channel auto-offset mode. 8-Bit MSBs Green Channel Offset Control. Controls offset (brightness) each respective channel. Bigger values decrease brightness. Linked Register 0x0D form 11-bit green offset that controls offset (brightness) green channel autooffset mode. 8-Bit MSBs Channel Offset Control. Controls offset (brightness) each respective channel. Bigger values decrease brightness. Linked Register 0x0F form 11-bit blue offset which controls offset (brightness) blue channel autooffset mode.
Rev. Page
AD9981
Hexadecimal Address 0x11 0x12 Read Write Read Only Bits Default Value 0010 0000 0*** **** Register Name Sync Separator Threshold Hsync Control
Preliminary Technical Data
Description This register sets threshold sync separator's digital comparator. Active Hsync Override. chip determines active Hsync source. active Hsync Source 0x12, Selects source Hsync sync processing. This used only 0x12, both syncs active. Hsync from Hsync input pin. Hsync from SOG. Hsync Polarity Override. chip selects Hsync input polarity. polarity input Hsync controlled 0x12, This applies both Hsync0 Hsync1. Hsync input polarity: this used only 0x12, Active input Hsync. Active high input Hsync. Sets polarity Hsync output signal. Active Hsync output. Active high Hsync output. Sets number pixel clocks that Hsync active. Active Vsync Override. chip determines active Vsync source. active Vsync source 0x14, Selects source Vsync sync processing. This used only 0x14, Vsync from VSYNC input pin. Vsync from sync separator. Vsync Polarity Override. chip selects input Vsync polarity. polarity input Vsync 0x14, This applies both Vsync0 Vsync1. Vsync input polarity: this used only 0x14, Active input Vsync. Active high input Vsync. Sets polarity output Vsync signal. Active output Vsync. Active high output Vsync. Vsync filter disabled. Vsync filter enabled. This needs enabled when using Hsync Vsync counter. Enables Vsync duration block. This designed used with Vsync filter. Vsync output duration unchanged. Vsync output duration Register 0x15. Sets number Hsyncs that Vsync active. This only used 0x14, number Hsync periods Coast prior Vsync. number Hsync periods Coast after Vsync. Coast Source. Selects source Coast signal. Using internal Coast generated from Vsync. Using external Coast signal from external Coast pin.
*0** ****
**0* ****
***1 ****
**** 1***
0x13 0x14
0010 0000 0*** ****
Hsync Duration Vsync Control
*0** ****
**0* ****
***1 ****
**** 1***
**** *0**
**** **0*
0x15 0x16 0x17 0x18
0000 1010 0000 0000 0000 0000 0*** ****
Vsync Duration Precoast Postcoast Coast Clamp Control
Rev. Page
AD9981
Hexadecimal Address Read Write Read Only Bits Default Value *0** **** Register Name Description Coast Polarity Override. chip selects external Coast polarity. polarity external Coast signal 0x18, Coast Input Polarity. This used only 0x18, Active external Coast. Active high external Coast. Clamp Source Select. internal clamp generated from Hsync. external clamp signal. Clamp. Clamp channel ground. Clamp channel midscale. Green Clamp. Clamp green channel ground. Clamp green channel midscale. Blue Clamp. Clamp blue channel ground. Clamp blue channel midscale. Must proper operation. Places clamp signal integer clock periods after trailing edge Hsync signal. Number clock periods that clamp signal actively clamping. External clamp polarity override. chip selects clamp polarity. polarity clamp signal 0x1B, External Clamp Input Polarity. This used only 0x1B, Active external clamp. Active high external clamp. Auto-offset disabled. Auto-offset enabled (offsets become desired clamp code). This selects often auto-offset circuit operates. every clamp; clamps; every clamps; every Vsync. Must written default (011) proper operation. Must 0xFF proper operation. slicer threshold. Sets voltage level slicer's comparator. SOGOUT Polarity. Sets polarity signal SOGOUT pin. Active SOGOUT. Active high SOGOUT. SOGOUT Select. from sync slicer (SOG0 SOG1). Hsync (Hsync0 Hsync1). Regenerated sync from sync filter. Filtered sync from sync filter. Channel Select Override. chip determines which input channels use. input channel selection determined 0x1E, Channel Select. Input channel select: this used only 0x1E, syncs present both channels. Channel syncs data selected. Channel syncs data selected.
**1* ****
***0 ****
**** 0***
**** *0**
**** **0*
0x19 0x1A 0x1B
**** ***0 0000 1000 0010 0000 0*** ****
Clamp Placement Clamp Duration Clamp Offset
*1** ****
**0* ****
***1 1*** **** *011 1111 1111 0111 1*** **** *0**
0x1C 0x1D
TestReg0 Control
**** **00
0x1E
****
Power
*0** ****
Rev. Page
AD9981
Hexadecimal Address Read Write Read Only Bits Default Value **1* **** Register Name
Preliminary Technical Data
Description Programmable Bandwidth. analog input bandwidth. High analog input bandwidth. Power-Down Control Select. Manual power-down control. Auto power-down control. Power-Down. Normal operation. Power-down. Power-Down Polarity. Active low. Active high. Power-Down Fast Switching Control. Normal power-down operation. chip stays powered outputs high impedance mode. SOGOUT High Impedance Control. SOGOUT operates normal during power-down. SOGOUT high impedance during power-down. Output Mode. 4:4:4 output mode. 4:2:2 output mode. 4:4:4-DDR output mode. Primary Output Enable. Primary output high impedance state. Primary output enabled. Secondary Output Enable. Secondary output high impedance state. Secondary output enabled. Output Drive Strength. output drive strength. Medium output drive strength. Medium high output drive strength. High output drive strength. Applies outputs except VSOUT. Output Clock Invert. Noninverted pixel clock. Inverted pixel clock. Applies clocks output DATACK. Output Clock Select. Pixel clock. phase shifted pixel clock. pixel clock. internal clock. Output High Impedance. Normal outputs. outputs except SOGOUT high impedance mode. High Impedance. Normal output. SOGOUT high impedance mode. Field Output Polarity. Sets polarity field output signal. Active even field, active high field. Active field, active high even field. Sync Filter Enable. uses Hsync/SOG. uses filtered Hsync/SOG.
***1 ****
**** 0***
**** *0**
**** **0*
**** ***0
0x1F
100* ****
Output Select
***1 ****
**** 0***
**** *10*
**** ***0
0x20
0*** ****
Output Select
*0** ****
**0* ****
***0 ****
**** 1***
Rev. Page
AD9981
Hexadecimal Address Read Write Read Only Bits Default Value **** *0** Register Name Description Sync Processing Input Select. Selects sync source sync processor. Sync processing uses Hsync/SOGIN. Sync processing uses regenerated Hsync from sync filter. Must proper operation. Must default proper operation. Must default proper operation. Sets window time around regenerated Hsync leading edge steps) that sync pulses allowed pass through. Hsync0 Detection Bit. Hsync0 active. Hsync0 active. Hsync1 Detection Bit. Hsync active. Hsync active. Vsync Detection Bit. Vsync0 active. Vsync0 active. Vsync1 Detection Bit. Vsync1 active. Vsync1 active. SOG0 Detection SOG0 active. SOG0 active. SOG1 Detection SOG1 active. SOG1 active. Coast Detection Bit. External Coast active. External Coast active. Clamp Detection Bit. External clamp active. External clamp active. Hsync Polarity. Hsync0 polarity active low. Hsync0 polarity active high. Hsync1 Polarity. Hsync1 polarity active low. Hsync1 polarity active high. Vsync0 Polarity. Vsync0 polarity active low. Vsync0 polarity active high. Vsync1 Polarity. Vsync1 polarity active low. Vsync1 polarity active high. Coast Polarity. External Coast polarity active low. External Coast polarity active high. Clamp Polarity. External clamp polarity active low. External clamp polarity active high. Extraneous Pulses Detected. equalization pulses detected Hsync. Extraneous pulses detected Hsync.
0x21 0x22 0x23
0010 0000 0011 0010 0000 1010
Sync Filter Window Width Sync Detect
0x24
_*** ****
*_** ****
**_* ****
***_ ****
**** _***
**** *_**
**** **_*
**** ***_
0x25
_*** ****
Sync Polarity Detect
*_** ****
**_* ****
***_ ****
**** _***
**** *_**
**** **_*
Rev. Page
AD9981
Hexadecimal Address 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C Read Write Read Only Bits 1011 1111 0000 0010 Default Value Register Name Hsyncs Vsync MSBs Hsyncs Vsync LSBs TestReg1 TestReg2 TestReg3 TestReg4 Offset Hold
Preliminary Technical Data
Description MSBs Hsyncs Vsync count. LSBs Hsyncs Vsync count. Must written 0xBF proper operation. Must written 0x02 proper operation. Read only bits future use. Read only bits future use. Must written default proper operation. Auto-Offset Hold. Disables auto-offset holds feedback result. time update. Continuous update. Must written default proper operation. Must written 0xE8 proper operation. Must written 0xE0 proper operation.
000* **** ***0 ****
0x2D 0x2E
**** 0000 1111 0000 1111 0000
TestReg5 TestReg6
Functions with more than eight control bits, such divide ratio, gain, offset, only updated when LSBs written (for example, Register 0x02 divide ratio).
Rev. Page
AD9981 DETAILED 2-WIRE SERIAL CONTROL REGISTER DESCRIPTIONS
CHIP IDENTIFICATION
0x00 Chip Revision 8-bit register that represents silicon revision.
CLOCK GENERATOR CONTROL
0x03 Range Select bits that establish operating range clock generator. VCORNGE must correspond desired operating frequency (incoming pixel rate). gives best jitter performance high frequencies. this reason, order output pixel rates still good jitter performance, actually operates higher frequency then divides down clock rate afterwards. Table pixel rates each range setting. output divisor automatically selected with range setting. power-up default value Table Ranges
Range Pixel Rates
DIVIDER CONTROL
0x01 Divide Ratio MSBs eight MSBs 12-bit divide ratio PLLDIV. derives pixel clock from incoming Hsync signal. pixel clock frequency then divided integer value, such that output phase-locked Hsync. This PLLDIV value determines number pixel times (pixels plus horizontal blanking overhead) line. This typically more than number active pixels display. 12-bit value divider supports divide ratios from 4095 long output frequency within range. higher value loaded this register, higher resulting clock frequency with respect fixed Hsync frequency. VESA established some standard timing specifications, which will assist determining value PLLDIV function horizontal vertical display resolution frame rate (see Table However, many computer systems conform precisely recommendations these numbers should used only guide. display system manufacturer should provide automatic manual means optimizing PLLDIV. incorrectly PLLDIV usually produces more vertical noise bars display. greater error, greater number bars produced. power-up default value PLLDIV 1693. PLLDIVM 0x69, PLLDIVL 0xDX. AD9981 updates full divide ratio only when LSBs written. Writing this register itself does trigger update. 0x02 Divide Ratio LSBs
0x03
Charge Pump Current
Three bits that establish current driving loop filter clock generator. current must correspond with desired operating frequency. power-up default value current 001. Table Charge Pump Currents
Current 1500
0x03
External Clock Enable
This determines source pixel clock. Table External Clock Select Settings
EXTCLK Function Internally generated clock Externally provided clock signal
four LSBs 12-bit divide ratio PLLDIV. power-up default value PLLDIV 1693. PLLDIVM 0x69, PLLDIVL 0xDX.
Logic enables internal that generates pixel clock from externally provided Hsync. Logic enables external EXTCLK input pin. this mode, Divide Ratio (PLLDIV) ignored. clock phase adjust (PHASE) still functional. power-up default value EXTCLK
Rev. Page
AD9981
PHASE ADJUST
0x04 Phase adjustment generate clock. 5-bit value that adjusts sampling phase steps across pixel time. Each step represents 11.25° shift sampling phase. power default
Preliminary Technical Data
INPUT OFFSET
0x0B Channel Offset MSBs 8-Bit Channel Offset Control. Along with LSBs following register, there bits offset control channel. offset control shifts analog input, resulting change brightness. Note that function offset register depends whether auto-offset enabled (Register 0x1B, auto-offset disabled, bits offset registers (Bits [6:0] offset register plus Bits [7:6] following register) control absolute offset added channel (for channel, Register 0x0B, Bits[6:0] plus Register 0x0C, Bits [7:6]) control absolute offset added channel. offset control provides ±255 LSBs adjustment range, with offset corresponding output code. auto-offset enabled, 11-bit offset (comprised bits register Bits [7:5] following register) determines clamp target code. 11-bit offset consists sign plus bits. register programmed DDR, then output code equal clamp period. Note that incrementing offset register setting adds offset, regardless auto-offset setting. Values written this register updated until register (Register 0x0C) also been written. 0x0C Channel Offset LSBs
INPUT GAIN
0x05 Channel Gain Adjust MSBs 7-Bit Channel Gain Control. AD9981 accommodate input signals with full-scale range between p-p. Setting gain corresponds input range gain establishes input range Note that increasing gain results picture having less contrast (the input signal uses fewer available converter codes). Values written this register will updated until register (R0x06) also been written. power-up default 1000000. 0x06 Channel Gain Adjust LSBs
LSBs Channel Gain Control. Along with MSBs gain control previous register, there bits gain control. Default power value 0x07 Green Channel Gain Adjust MSBs 7-Bit Green Channel Gain Control. channel gain adjust above. Register update requires writing 0x00 Register 0x08. 0x08 Green Channel Gain Adjust LSBs
2-Bit LSBs Green Channel Gain Control. Along with MSBs gain control previous register, there bits gain control. Default powerup value 0x09 Blue Channel Gain Adjust MSBs
LSBs channel offset control combine with bits previous register make bits offset control. 0x0D Green Channel Offset MSBs
7-Bit Blue Channel Gain Control. channel gain adjust above. Register update requires writing 0x00 Register 0x0A. 0x0A Blue Channel Gain Adjust LSBs
8-Bit Green Channel Offset Control. channel offset (0x0B). Update this register occurs only when Register 0x0E also written. 0x0E Green Channel Offset LSBs
2-Bit LSBs Blue Channel Gain Control. Along with MSBs gain control previous register, there bits gain control. Default powerup value
LSBs green channel offset control combine with bits previous register make bits offset control. 0x0F Blue Channel Offset MSBs
8-Bit Blue Channel Offset Control. channel offset (0x0B). Update this register occurs only when Register 0x10 also written.
Rev. Page
AD9981
0x10 Blue Channel Offset LSBs Table Hsync Input Polarity Override Settings
Override Result Hsync Polarity Determined Chip Hsync Polarity Determined User Register 0x12,
LSBs blue channel offset control combine with bits previous register make bits offset control.
HSYNC CONTROLS
0x11 Sync Separator Threshold This register sets threshold sync separator's digital comparator. value written this register multiplied threshold value. Therefore, value written, digital comparator threshold pulses less than rejected sync separator. There some variability multiplier value. maximum variability over operating conditions ±20% (160 ns). Since normal Vsync Hsync pulse widths differ factor about more, variability issue. powerup default value DDR. 0x12 Hsync Source Override
0x12
Input Hsync Polarity
Register 0x12 value this specifies polarity input Hsync. Setting this indicates active Hsync; setting this indicates active high Hsync. Power-up default Table Hsync Input Polarity Settings
Hsync Polarity Result Hsync Input Polarity Negative Hsync Input Polarity Positive
0x12
Hsync Output Polarity
This sets polarity Hsync output. Setting this sets Hsync output active low. Setting this sets Hsync output active high. Power-up default setting Table Hsync Output Polarity Settings
Hsync Output Polarity Result Hsync Output Polarity Negative Hsync Output Polarity Positive
This active Hsync override. Setting this allows chip determine active Hsync source. Setting uses Register 0x12 determine active Hsync source. Power-up default value Table 16.Active Hsync Source Override
Override Result Hsync Source determined chip Hsync Source determined user Register 0x12,
0x13
Hsync Duration
0x12
Hsync Source
This selects source Hsync sync processing-only Register 0x12 both syncs active. Setting this specifies Hsync from input pin. Setting selects Hsync from SOG. Power-up default Table Active Hsync Select Settings
Select Result Hsync Input Hsync from
8-bit register that sets duration Hsync output pulse. leading edge Hsync output triggered internally-generated, phase-adjusted feedback clock. AD9981 then counts number pixel clocks equal value this register. This triggers trailing edge Hsync output, which also phase-adjusted.
VSYNC CONTROLS
0x14 Vsync Source Override This active Vsync override. Setting this allows chip determine active Vsync source, setting uses Register 0x14 determine active Vsync source. Power-up default value Table Active Vsync Source Override
Override Result Vsync source determined chip Vsync source determined user Register 0x14,
0x12
Hsync Input Polarity Override
This determines whether chip selects Hsync input polarity specified. Setting this allows chip automatically select polarity input Hsync; setting indicates that Register 0x12 specifies polarity. Power-up default
Rev. Page
AD9981
0x14 Vsync Source
Vsync Filter
Preliminary Technical Data
Table Vsync Filter Enable
Result Vsync filter disabled Vsync filter enabled
This selects source Vsync sync processing only Register 0x14 Setting specifies Vsync from input pin; setting selects Vsync from sync separator. Power-up default Table Active Vsync Select Settings
Select Result Vsync input Vsync from sync separator
0x14
Vsync Duration Enable
This enables Vsync duration block, which designed used with Vsync filter. Setting leaves Vsync output duration unchanged. Setting sets Vsync output duration based Register 0x15. Power-up duration Table Vsync Duration Enable
Vsync Duration Result Vsync output duration unchanged Vsync output duration Register 0x15
0x14
Vsync Input Polarity Override
This sets whether chip selects Vsync input polarity specified. Setting this allows chip automatically select polarity input Vsync. Setting this indicates that Register 0x14 specifies polarity. Power-up default Table Vsync Input Polarity Override Settings
Override Result Vsync polarity determined chip Vsync polarity determined user Register 0x14,
0x15
Vsync Duration
This used output duration Vsync, designed used with Vsync filter. This valid only Register 0x14, Power-up default DDR.
COAST CLAMP CONTROLS
0x16 Precoast This register allows internally generated Coast signal applied prior Vsync signal. This necessary cases where pre-equalization pulses present. step size this control Hsync period. Precoast work correctly, necessary Vsync filter (0x14, sync processing filter (Register 0x20, both either enabled disabled. power-up default 0x17 Postcoast
0x14
Input Vsync Polarity
Register 0x14 value this specifies polarity input Vsync. Setting this indicates active Vsync; setting this indicates active high Vsync. Power-up default Table Vsync Input Polarity Settings
Override Result Vsync input polarity negative Vsync input polarity positive
0x14
Vsync Output Polarity This register allows internally generated Coast signal applied following Vsync signal. This necessary cases where postequalization pulses present. step size this control Hsync period. Postcoast work correctly, necessary Vsync filter (0x14, sync processing filter (0x20, both either enabled disabled. power-up default 0x18 Coast Source
This sets polarity Hsync output. Setting this sets Hsync output active low. Setting this sets Hsync output active high. Power-up default Table Vsync Output Polarity Settings
Vsync Output Polarity Result Vsync output polarity negative Vsync output polarity positive
0x14
Vsync Filter Enable
This enables Vsync filter allowing precise placement Vsync with respect Hsync facilitating correct operation Hsyncs/ Vsync count.
This used select active Coast source. choices COAST input vsync. Vsync selected, additional decision using VSYNC input output from sync separator needs made (Register 0x14, Bits 6]).
Rev. Page
AD9981
Table Coast Source Selection Settings
Select Result Vsync (internal Coast) COAST input
Table Green Clamp Select Settings
Clamp Result Clamp ground Clamp midscale
0x18
Coast Polarity Override
0x18
Blue Clamp Select
This register used override internal circuitry that determines polarity Coast signal going into PLL. power-up default setting Table Coast Polarity Override Settings
Override Result Coast polarity determined chip Coast polarity determined user Clamp
This determines whether blue channel clamped ground midscale. power-up default setting Table Blue Clamp Select Settings
Result Clamp ground Clamp midscale
0x18
Input Coast Polarity
0x19
Clamp Placement
This register sets input Coast polarity when Register 0x18 power-up default setting Table Coast Polarity Settings
Coast Polarity Result Coast polarity negative Coast polarity positive
0x18
Clamp Source
This determines source clamp timing. enables clamp timing circuitry controlled clamp placement clamp duration. clamp position duration counted from leading edge Hsync. enables external clamp input pin. three channels clamped when clamp signal active. polarity clamp determined clamp polarity bit. power-up default setting Table Clamp Source Selection Settings
Clamp Source Result Internally generated clamp Externally provided clamp signal
8-bit register that sets position internally generated clamp. When EXTCLMP (Register 0x18, clamp signal generated internally, position established clamp placement register (Register 0x19) duration clamp duration register (Register 0x1A). Clamping started clamp placement count(Register 0x19) pixel periods after trailing edge Hsync. clamp placement programmed value between 255. value supported. clamp should placed during time that input signal presents stable black-level reference, usually back porch period between Hsync image. When EXTCLMP this register ignored. Power-up default setting 0x1A Clamp Duration
0x18
Clamp Select
This determines whether channel clamped ground midscale. power-up default setting Table Clamp Select Settings
Clamp Result Clamp ground Clamp midscale
8-bit register that sets duration internally generated clamp. When EXTCLMP (Register 0x18, clamp signal generated internally position established clamp placement register (and duration clamp duration register). Clamping begins clamp placement count (Register 0x19) pixel periods after trailing edge Hsync. clamp duration programmed value between 255. value supported. best results, clamp duration should include majority black reference signal time that follows Hsync signal trailing edge. Insufficient clamping time produce brightness changes screen, slow recovery from large changes average picture level (APL), brightness. When EXTCLMP this register ignored. Power-up default setting DDR.
0x18
Green Clamp Select
This determines whether green channel clamped ground midscale. power-up default setting
Rev. Page
AD9981
0x1B Clamp Polarity Override 0x1D This used override internal circuitry that determines polarity clamp signal. power-up default setting Table Clamp Polarity Override Settings
Override Result Clamp Polarity Determined Chip Clamp Polarity Determined User Register 0x1B,
Preliminary Technical Data
Output Polarity This sets polarity SOGout signal. power-up default setting Table SOGOUT Polarity Settings
SOGOUT Result Active Active high
0x1D
Output Select
0x1B
Input Clamp Polarity
This indicates polarity clamp signal only Register 0x1B power-up default setting Table Clamp Polarity Override Settings
CLMPOL Result Active Active high
These register bits control what output SOGOUT pin. Options from slicer (this unprocessed signal produced from sync slicer), Hsync, regenerated sync from sync filter which generate missing syncs either coasting drop-out, finally filtered sync which excludes extraneous syncs occurring within sync filter window. powerup default setting Table SOGOUT Polarity Settings
SOGOUT Select Function from sync slicer (SOG0 SOG1) Hsync (HSYNC0 HSYNC1) Regenerated Sync from sync filter Filtered sync from sync filter
0x1B
Auto-Offset Enable
This selects between auto-offset mode manual offset mode (auto-offset disabled). section auto-offset operation. power-up default setting Table Auto-Offset Settings
Auto-Offset Result Auto-offset disabled Auto-offset enabled (manual offset mode)
INPUT POWER CONTROL
0x1E Channel Select Override This provides override automatic input channel selection. Power-up default setting Table Channel Source Override
Override Result Channel input source determined chip Channel input source determined user Register 0x1E,
0x1B
Auto-Offset Update Frequency
These bits control often auto-offset circuit updated enabled). Updating every Hsyncs recommended. power-up default setting Table Auto-Offset Update Mode
Clamp Update Result Update offset every clamp period Update offset every clamp periods Update offset every clamp periods Update offset every Vsync periods
0x1E
Channel Select
0x1B
Must written proper operation.
This selects active input channel Register 0x1E, This selects between Channel data syncs Channel data syncs. Power-up default setting Table Channel Select
Channel Select Result Channel data syncs selected Channel data syncs selected
CONTROL
0x1D Comparator Threshold This register allows comparator threshold slicer adjusted. This register adjusts steps with minimum setting equaling maximum setting equaling power-up default setting corresponds threshold value
0x1E
Programmable Bandwidth
This selects between high input bandwidth. useful limiting noise lower frequency inputs. power-up default setting analog input bandwidth ~100 MHz; high analog input bandwidth ~200 MHz.
Rev. Page
AD9981
Table Input Bandwidth Select
Input Bandwidth Result analog input bandwidth High analog input bandwidth
0x1E
Power-Down Fast Switching Control
0x1E
Power-Down Control Select
This determines whether power-down controlled manually automatically chip. automatic control selected (Register 0x1E, AD9981's decision based status sync detect bits (Register 0x24, Bits either Hsync sync-on-green input detected input, chip powers powers down. manual control, AD9981 allows flexibility control through both dedicated register bit. dedicated allows hardware watchdog circuit control power-down, while register allows power-down controlled software. With manual power-down control, polarity powerdown must (0x1E, whether used not. unused, recommended polarity active high hardwire ground with resistor. Table Auto Power-Down Select
Power-Down Select Result Manual power-down control (User determines power-down) Auto power-down control (Chip determines power-down)
This controls special fast switching mode. With this AD9981 stay active during powerdown only outputs high impedance. This option useful when data outputs from chips connected user wants switch instantaneously between two. Table Power-Down Fast Switching Control
Fast Switching Control Result Normal power-down operation chip stays powered outputs high impedance mode
0x1E
SOGOUT High Impedance Control
This controls whether SOGOUT output high impedance not, when power-down mode. most cases, SOGOUT high impedance during normal operation. usually needed sync detection graphics controller. option SOGOUT high impedance included mainly allow factory testing modes. Table SOGOUT High Impedance Control
SOGOUT Control Result SOGOUT output operates normal during power-down. SOGOUT output high impedance during power-down.
0x1E
Power-Down
OUTPUT CONTROL
0x1F Output Mode These bits choose between three options output mode. 4:4:4 mode, standard. 4:2:2 mode, YCbCr standard, which allows reduction number output pins from 4:4:4 output mode, data mode, changes every clock edge. power-up default setting 100. Table Output Mode
Output Mode Result 4:4:4 mode 4:2:2 YCbCr mode 4:4:4 mode
This used manually place chip powerdown mode. only used manual power-down control selected (see above). Both state this register power-down (Pin used control manual power-down. (See Power Management section more details power-down.) Table Power-Down Settings
Power-Down Select Result Normal operation Power-down
0x1E
Power-Down Polarity
This defines polarity power-down (Pin 17). only used manual power-down control selected (see above). Table Power-Down Polarity
Select Result Power-down active Power-down active high
0x1F
Primary Output Enable
This places primary output active high impedance mode. power-up default setting Table Primary Output Enable
Select Result Primary output high impedance mode Primary output enabled
Rev. Page
AD9981
0x1F Secondary Output Enable 0x20 This places secondary output active high impedance mode. secondary output designated when using either 4:2:2 4:4:4 (DDR). these modes, data blue output channel secondary output while output data green channels primary output. Secondary output always YCbCr data mode. Output Formatter section Table power-up default setting Table Secondary Output Enable
Select Result Secondary output high impedance mode Secondary output enabled
Preliminary Technical Data
Output High Impedance This puts outputs (except SOGOUT) high impedance state. power-up default setting Table Output High Impedance
Select Result Normal outputs outputs (except SOGOUT) high impedance mode
0x20
High Impedance
This allows SOGOUT placed high impedance mode. power-up default setting Table SOGOUT High Impedance
Select Result Normal output SOGOUT high impedance mode
0x1F
Output Drive Strength
These bits select drive strength high-speed digital outputs (except VSOUT, field). Higher drive strength results faster rise/fall times general makes easier capture data. Lower drive strength results slower rise/fall times helps reduce digitally generated power supply noise. power-up default setting Table Output Drive Strength
Output Drive Result output drive strength Medium output drive strength Medium high output drive strength High output drive strength
0x20
Field Output Polarity
This sets polarity field output bit. power-up default setting Table Field Output Polarity
Select Result Active even field; active high field Active field; active high even field
SYNC PROCESSING
0x20 Sync Filter
0x1F
Output Clock Invert
This allows inversion output clock. power-up default setting Table Output Clock Invert
Select Result Noninverted pixel clock Inverted pixel clock
This selects which signal uses. select between either Hsync filtered versions. filtering Hsync eliminate nearly extraneous transitions which have traditionally caused disruption. power-up default setting Table Sync Filter Enable
Select Result uses Hsync inputs uses filtered Hsync inputs
0x20
Output Clock Select
0x20
Sync Processing Input Source
These bits allow selection optional output clocks such fixed clock, clock, phaseshifted clock, normal pixel clock. power-up default setting Table Output Clock Select
Select Result Pixel clock phase-shifted pixel clock pixel clock internal clock
This selects whether sync processor uses sync regenerated sync following functions: Coast, count, field detection Vsync duration counts. Using regenerated sync recommended. Table Filter Enable
Select Result Sync processing uses Hsync Sync processing uses internally regenerated Hsync
Rev. Page
AD9981
0x21 0x22 0x23 Must default Must default Sync Filter Window Width activity detected. sync processing block diagram shows where this function implemented. Vsync1 active. Vsync1 active. Table Vsync1 Detection Results
Detect Result activity detected Activity detected
This 8-bit register sets window time regenerated Hsync leading edge steps) that sync pulses allowed pass through. Therefore with default value window width ±250 goal window width that extraneous pulses rejected. (see Sync Processing section). sync separator threshold, multiplier value somewhat variable. maximum variability over operating conditions ±20% ns).
0x24
SOG0 Detection
This used indicate when activity detected SOG0 input pin. held high low, activity detected. sync processing block diagram shows where this function implemented. SOG0 active. SOG0 active. Table SOG0 Detection Results
Detect Result activity detected Activity detected
DETECTION STATUS
0x24 Hsync0 Detection
This used indicate when activity detected HSYNC0 input pin. Hsync held high low, activity detected. sync processing block diagram shows where this function implemented. Hsync0 active. Hsync0 active. Table Hsync0 Detection Results
Detect Result activity detected Activity detected
0x24
SOG1 Detection
This used indicate when activity detected SOG1 input pin. held high low, activity detected. sync processing block diagram shows where this function implemented. SOG1 active. SOG1 active. Table SOG1 Detection Results
Detect Result activity detected Activity detected
0x24
Hsync1 Detection
This used indicate when activity detected HSYNC1 input pin. HSYNC held high low, activity detected. sync processing block diagram shows where this function implemented. HSYNC1 active. HSYNC1 active. Table Hsync1 Detection Results
Detect Result activity detected Activity detected
0x24
COAST Detection
This detects activity EXTCLK/EXTCOAST pin. indicates that signals active, doesn't indicate which one. signal detected. Table Coast Detection Result
Detect Result activity detected Activity detected
0x24
Vsync0 Detection
This used indicate when activity detected VSYNC0 input pin. Vsync held high low, activity detected. sync processing block diagram shows where this function implemented. Vsync0 active. Vsync0 active. Table Vsync0 Detection Results
Detect Result activity detected Activity detected
0x24
Clamp Detection
This used indicate when activity detected external CLAMP pin. external clamp held high low, activity detected. Table Clamp Detection Results
Detect Result activity detected Activity detected
0x24
VSYNC1 Detection
This used indicate when activity detected VSYNC1 input pin. Vsync held high low,
Rev. Page
AD9981
POLARITY STATUS
0x25 Hsync0 Polarity
Detect
Preliminary Technical Data
Table Equalization Pulse Detect
Result equalization pulses detected during active Hsync Equalization pulses detected during active Hsync
Indicates polarity HSYNC0 input. Table Detected Hsync0 Polarity Results
Detect Result Hsync polarity negative Hsync polarity positive
HSYNC COUNT
0x26 Hsyncs/Vsync
0x25
Hsync1 Polarity
Indicates polarity HSYNC1 input. Table Detected Hsync1 Polarity Results
Detect Result Hsync polarity negative Hsync polarity positive
eight MSBs 12-bit counter that reports number Hsyncs/Vsync active input. This useful determining mode setting divide ratio. 0x27 Hsyncs/Vsync LSBs
0x25
Vsync0 Polarity
four LSBs 12-bit counter that reports number Hsyncs/Vsync active input.
Indicates polarity Vsync0 input. Table Detected Vsync0 Polarity Results
Detect Result Vsync polarity negative Vsync polarity positive
Test Registers
0x28 Test Register
Must written 0xBF proper operation. 0x29 Test Register
0x25
Vsync1 Polarity 0x2A
Must written 0x00 proper operation. Test Register
Indicates polarity Vsync1 input. Table Detected Vsync1 Polarity Results
Detect Result Vsync polarity negative Vsync polarity positive
Read-only bits future use. 0x2B Test Register
0x25
Coast Polarity 0x2C
Read-only bits future use. Test Register
Indicates polarity external Coast signal. Table Detected Coast Polarity Results
Detect Result Coast polarity negative Coast polarity positive
Must written 0x00 proper operation. 0x2C Auto-Offset Hold
0x25
Clamp Polarity
Indicates polarity clamp signal. Table Detected Clamp Polarity Results
Detect Result Clamp polarity negative Clamp polarity positive
0x25
Extraneous Pulses Detection
second output from Hsync filter, this status tells whether extraneous pulses present incoming sync signal. Often extraneous pulses used copy protection, this status used this purpose.
controlling whether auto-offset function runs continuously runs once holds result. Continuous updates recommended because allows AD9981 compensate drift-over time, temperature, one-time updates preferred, these should performed every time part powered when there mode change. one-time update, first auto-offset must enabled (0x1B, Next, this (auto-offset hold) must auto-offset function operate settle final value. Auto-offset hold should then hold offset values that auto circuitry calculates. AD9981's auto-offset circuit's maxi-mum settle time updates. example, update frequency once every Hsyncs, then maximum settling time would Hsyncs Hsyncs).
Rev. Page
AD9981
Table Auto-Offset Hold
Select Result Disables auto-offset updates holds current auto-offset values Allows auto-offset update continuously
0x2C 0x2D
Must written proper operation. Test Register
Read/write bits future use. Must written 0xE8 proper operation. 0x2E Test Register
Read/write bits future use. Must written 0xE0 proper operation.
Rev. Page
AD9981 TWO-WIRE SERIAL CONTROL PORT
two-wire serial interface control interface provided. AD9981 devices connected two-wire serial interface, with each device having unique address. two-wire serial interface comprises clock (SCL) bidirectional data (SDA) pin. analog flat panel interface acts slave receiving transmitting data over serial interface. When serial interface active, logic levels pulled high external pull-up resistors. Data received transmitted line must stable duration positive-going pulse. Data must change only when low. changes state while high, serial interface interprets that action start stop sequence. following five components serial operation: Start signal Slave address byte Base register address byte Data byte read write Stop signal
(MSB)
Preliminary Technical Data
Table Serial Port Addresses
DATA TRANSFER SERIAL INTERFACE
each byte data read written, first sequence. AD9981 does acknowledge master device during write sequence, remains high master generate stop signal. master device does acknowledge AD9981 during read sequence, AD9981 interprets this end-of-data. remains high master generate stop signal. Writing data specific control registers AD9981 requires that 8-bit address control register interest written after slave address been established. This control register address base address subsequent write operations. base address auto-increments each byte data written after data byte intended base address. more bytes transferred than there available addresses, address will increment remain maximum value 0x2E. base address higher than 0x2E will produce acknowledge signal. Data read from control registers AD9981 similar manner. Reading requires data transfer operations: base address must written with slave address byte sequential read operation. Reading (the R/W\ slave address byte high) begins previously established base address. address read register auto-increments after each byte transferred. terminate read/write sequence AD9981, stop signal must sent. stop signal comprises low-to-high transition while high. repeated start signal occurs when master device driving serial interface generates start signal without first generating stop signal terminate current communication. This used change mode communication (read, write) between slave master without releasing serial interface lines.
When serial interface inactive (SCL high), communications initiated sending start signal. start signal high-to-low transition while high. This signal alerts slaved devices that data transfer sequence coming. first eight bits data transferred after start signal comprise 7-bit slave address (the first seven bits) single R/W\ (the eighth bit). R/W\ indicates direction data transfer, read from write slave device. transmitted slave address matches address device (set state Serial address [SA0] input Table 70), AD9981 acknowledges match bringing pulse. addresses match, AD9981 does acknowledge
tBUFF tSTAH
tDHO tDAL
tDSU
tSTASU
tSTOSU
tDAH
Figure Serial Port Read/Write Timing
Rev. Page
04739-011
AD9981
Serial Interface Read/Write Examples
Write following control register: Start signal Slave address byte (R/W\bit low) Base address byte Data byte base address Stop signal Read from control register: Start signal Slave address byte (R/W\bit low) Base address byte Start signal Slave address byte (R/W\ high) Data byte from base address Stop signal
Write four consecutive control registers: Start signal Slave address byte (R/W\bit low) Base address byte Data byte base address Data byte (base address Data byte (base address Data byte (base address Stop signal
Read from four consecutive control registers: Start signal Slave address byte (R/W\bit low) Base address byte Start signal Slave address byte (R/W\bit high) Data byte from base address Data byte from (base address Data byte from (base address Data byte from (base address Stop signal
04739-012
Figure Serial Interface-Typical Byte Transfer
Rev. Page
AD9981
LAYOUT RECOMMENDATIONS
AD9981 high-precision, high-speed analog device. achieve maximum performance from part, important have well laid-out board. Analog Interface Inputs section provides guide designing board using AD9981. bypass capacitors should physically located between power plane power pin. Current should flow from power plane capacitor power pin. make power connection between capacitor power pin. Placing underneath capacitor pads, down power plane, generally best approach. particularly important maintain noise good stability (the clock generator supply). Abrupt changes result similarly abrupt changes sampling clock phase frequency. This avoided careful attention regulation, filtering, bypassing. highly desirable provide separate regulated supplies each analog circuitry groups PVD). Some graphic controllers substantially different levels power when active (during active picture time) when idle (during horizontal vertical sync periods). This result measurable change voltage supplied analog supply regulator, which turn produce changes regulated analog supply voltage. This mitigated regulating analog supply, least PVD, from different, cleaner, power source (for example, from supply). also recommended single ground plane entire board. Experience repeatedly shown that noise performance same better with single ground plane. Using multiple ground planes detrimental because each separate ground plane smaller long ground loops result. some cases, using separate ground planes unavoidable. those cases, recommended least place single ground plane under AD9981. location split should receiver digital outputs. this case even more important place components wisely because current loops will much longer (current takes path least resistance). example current loop power plane AD9981 digital output trace digital data receiver digital ground plane analog ground plane.
Analog Interface Inputs
Using following layout techniques graphics inputs extremely important: Minimize trace length running into graphics inputs. This accomplished placing AD9981 close possible graphics connector. Long input trace lengths undesirable because they pick noise from board other external sources. Place termination resistors (see Figure close possible AD9981 chip. additional trace length between termination resistors input AD9981 increases magnitude reflections, which corrupts graphics signal. matched impedance traces. Trace impedances other than also increases chance reflections. AD9981 very high input bandwidth, (200 MHz). While this desirable acquiring high resolution graphics signal with fast edges, also means that captures high frequency noise present. Therefore, important reduce amount noise that gets coupled inputs. Avoid running digital traces near analog inputs. high bandwidth AD9981, sometimes low-pass filtering analog inputs help reduce noise. (For many applications, filtering unnecessary.) Experiments have shown that placing ferrite bead series prior termination resistor helpful filtering excess noise. Specifically, Fair-Rite #2508051217Z0 used, application could work best with different bead value. Alternatively, placing resistor between termination resistor input coupling capacitor beneficial.
Place loop filter components close FILT possible. place digital other high frequency traces near these components. values suggested data sheet with tolerances less.
Power Supply Bypassing
recommended bypass each power supply with capacitor. exception where more supply pins adjacent each other. these groupings powers/grounds, only necessary have bypass capacitor. fundamental idea have bypass capacitor within about each power pin. Also, avoid placing capacitor opposite side board from AD9981, since that interposes resistive vias path.
Outputs (Both Data Clocks)
minimize trace length that digital outputs have drive. Longer traces have higher capacitance require more instantaneous current drive, which creates more internal digital noise. Shorter traces reduce possibility reflections.
Rev. Page
AD9981
Adding series resistor value suppress reflections, reduce EMI, reduce current spikes inside AD9981. series resistors used, place them close AD9981 pins possible, (although vias extra length output trace resistors closer). possible, limit capacitance that each digital output drives less than This easily accomplished keeping traces short connecting outputs only device. Loading outputs with excessive capacitance increases current transients inside AD9981 creates more digital noise power supplies.
Digital Inputs
Digital inputs AD9981 (HSYNC0, HSYNC1, VSYNC0, VSYNC1, SOGIN0, SOGIN1, SDA, CLAMP) were designed work with signals, tolerant signals. Therefore, extra components need added using logic. noise that gets onto Hsync input trace adds jitter system. Therefore, minimize trace length digital other high frequency traces near
REFERENCE Bypass
AD9981 three reference voltages that must bypassed proper operation input PGA. REFLO REFHI connected each other through capacitor. REFCM connected ground through capacitor. These references used input circuitry assure greatest stability. Place them close AD9981 possible. Make ground connection short possible.
Rev. Page
AD9981 OUTLINE DIMENSIONS
0.75 0.60 0.45 SEATING PLANE 1.60
16.00
VIEW (PINS DOWN)
14.00
1.45 1.40 1.35
0.15 0.05
SEATING PLANE
0.20 0.09 3.5° 0.10 COPLANARITY
VIEW
0.65
VIEW
ROTATED
COMPLIANT JEDEC STANDARDS MS-026-BEC
0.38 0.32 0.22
Figure 80-Lead Profile Quad Flat Pack [LQFP] (ST-80-2) Dimensions shown millimeters
ORDERING GUIDE
Model AD9981KSTZ-801 AD9981KSTZ-951 AD9981/PCB Temperature Range +70°C +70°C Package Description 80-lead LQFP 80-lead LQFP Evaluation Package Option ST-80-2 ST-80-2
Pb-free part.
Purchase licensed components Analog Devices sublicensed Associated Companies conveys license purchaser under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips.
2005 Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective owners. D04739-0-1/05
Rev. Page
Other recent searches
WDLT-0404-72 - WDLT-0404-72 WDLT-0404-72 Datasheet
WDLT-0406-72 - WDLT-0406-72 WDLT-0406-72 Datasheet
WDLT-0412-72 - WDLT-0412-72 WDLT-0412-72 Datasheet
WDLT-0604-72 - WDLT-0604-72 WDLT-0604-72 Datasheet
WDLT-0606-72 - WDLT-0606-72 WDLT-0606-72 Datasheet
WDLT-0608-72 - WDLT-0608-72 WDLT-0608-72 Datasheet
WDLT-0612-72 - WDLT-0612-72 WDLT-0612-72 Datasheet
WDLT-0616-72 - WDLT-0616-72 WDLT-0616-72 Datasheet
WDLT-0804-72 - WDLT-0804-72 WDLT-0804-72 Datasheet
WDLT-0808-72 - WDLT-0808-72 WDLT-0808-72 Datasheet
WDLT-0812-72 - WDLT-0812-72 WDLT-0812-72 Datasheet
WDLT-0816-72 - WDLT-0816-72 WDLT-0816-72 Datasheet
WDLT-1204-72 - WDLT-1204-72 WDLT-1204-72 Datasheet
WDLT-1208-72 - WDLT-1208-72 WDLT-1208-72 Datasheet
WDLT-1212-72 - WDLT-1212-72 WDLT-1212-72 Datasheet
WDLT-1216-72 - WDLT-1216-72 WDLT-1216-72 Datasheet
WDLT-1608-72 - WDLT-1608-72 WDLT-1608-72 Datasheet
WDLT-1612-72 - WDLT-1612-72 WDLT-1612-72 Datasheet
WDLT-1616-72 - WDLT-1616-72 WDLT-1616-72 Datasheet
SN74AHC125Q - SN74AHC125Q SN74AHC125Q Datasheet
MA128 - MA128 MA128 Datasheet
KCSC56-104 - KCSC56-104 KCSC56-104 Datasheet
ICS664-01 - ICS664-01 ICS664-01 Datasheet
ICS661 - ICS661 ICS661 Datasheet
CLM6T-RKB - CLM6T-RKB CLM6T-RKB Datasheet
1N5139 - 1N5139 1N5139 Datasheet
1N5148 - 1N5148 1N5148 Datasheet
1N5139A - 1N5139A 1N5139A Datasheet
1N5148A - 1N5148A 1N5148A Datasheet
1N5140 - 1N5140 1N5140 Datasheet
1N5140A - 1N5140A 1N5140A Datasheet
1N5141 - 1N5141 1N5141 Datasheet
1N5141A - 1N5141A 1N5141A Datasheet
1N5142 - 1N5142 1N5142 Datasheet
1N5142A - 1N5142A 1N5142A Datasheet
1N5143 - 1N5143 1N5143 Datasheet
1N5143A - 1N5143A 1N5143A Datasheet
1N5144 - 1N5144 1N5144 Datasheet
1N5144A - 1N5144A 1N5144A Datasheet
1N5145 - 1N5145 1N5145 Datasheet
1N5145A - 1N5145A 1N5145A Datasheet
1N5146 - 1N5146 1N5146 Datasheet
1N5146A - 1N5146A 1N5146A Datasheet
1N5147 - 1N5147 1N5147 Datasheet
1N5147A - 1N5147A 1N5147A Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
