Gb/s 3.3V QuadPortDSE Family QuadPortdatapath switching element (

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Gb/s 3.3V QuadPortDSE Family QuadPortdatapath switching element (

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CY7C0430BV CY7C04312BV CY7C04314BV
Gb/s 3.3V QuadPortDSE Family
QuadPortdatapath switching element (DSE) family allows four independent ports access data path management switching High-bandwidth data throughput Gb/s 133-MHz[1] port speed 18-bit-wide interface ports High-speed clock data access (max.) Synchronous pipelined devices 1-Mb, switch arrays 64K/32K/16K device options 0.25-micron CMOS optimum speed/power IEEE 1149.1 JTAG boundary scan Width depth expansion capabilities BIST (Built-In Self-Test) controller Dual Chip Enables ports easy depth expansion Separate upper-byte lower-byte controls ports Simple array partitioning (CY7C0430BV only) Internal mask register controls counter wrap-around Counter-Interrupt flags indicate wrap-around Counter mask registers readback address 272-ball package (27-mm 27-mm 1.27-mm ball pitch) Commercial industrial temperature ranges 3.3V operating power Active (maximum) Standby (maximum
QuadPort Family Applications
PORT
PORT
PORT
PORT
BUFFERED SWITCH
PORT
PORT
PORT
PORT
REDUNDANT DATA MIRROR
Note: fMAX2 commercial industrial MHz.
Cypress Semiconductor Corporation Document 38-06027 Rev.
3901 North First Street
Jose
95134 408-943-2600 Revised 2002
CY7C0430BV CY7C04312BV CY7C04314BV
PORT
PORT
PORT
PORT
DATA PATH AGGREGATOR Processor
Pre-processed DATA Path
QuadPort Family
Processed DATA Path
Processor
DATA PATH MANAGER PARALLEL PACKET PROCESSING
Queue PORT PORT
Queue PORT PORT
DATA CLASSIFICATION ENGINE
Functional Description
CY7C043XXBV family Gb/s, true four-ported Datapath Switching Elements with port speeds MHz[1]. members family include 1-Mb (64K (32K x18), (16K options. four ports clocked independent frequencies from another. Simultaneous reads allowed accesses same address location; however, simultaneous reading writing same address allowed. port write certain location while other ports reading that location simultaneously, timing spec port port delay (tCCS) met. result writing same location more than port same time undefined. Data registered decreased cycle time. Clock data valid tCD2 Each port contains burst counter input Document 38-06027 Rev.
address register. After externally loading counter with initial address counter will self-increment address internally (more details follow). internal write pulse width independent duration input signal. internal write pulse self-timed allow shortest possible cycle times. HIGH clock cycle will power down internal circuitry reduce static power consumption. cycle required with chip enables asserted reactivate outputs. CY7C0430BV (64K device) only member family which contains burst contains simple array partitioning. Counter enable inputs provided stall operation address input utilize internal address generated internal counter fast interleaved memory Page
CY7C0430BV CY7C04312BV CY7C04314BV
applications. port's burst counter loaded with external address when port's Counter Load (CNTLD) asserted LOW. When port's Counter Increment (CNTINC) asserted, address counter will increment each subsequent LOW-to- HIGH transition that port's clock signal. This will read/write word from/into each successive address location until CNTINC deasserted. counter address entire switch array will loop back start. Counter Reset (CNTRST) used reset burst counter. counter-mask register used control counter wrap. counter mask register operations described more details following sections. counter mask register values read back bidirectional address lines activating MKRD CNTRD, respectively. features included QuadPort family include: readback burst-counter internal address value address lines, counter-mask registers control counter wrap-around, readback mask register value address lines, interrupt flags message passing, BIST, JTAG boundary scan, asynchronous Master Reset.
Level Logic Block Diagram
Port Operation-control Logic Blocks[2]
MRST UBP1 LBP1 R/WP1 OEP1 CE0P1 CE1P1 CLKP1 Reset Logic
Port-1 Control Logic
CLKBIST BIST JTAG Controller
I/O0P1- I/O17P1 CLKP1 A0P1-A15P1 MKLDP1
Port
Port Logic Blocks[3]
CNTRSTP1 INTP1 CNTINTP1
CNTLDP1 CNTINCP1 CNTRDP1 MKRDP1
Port Counter/ Mask Reg/ Address Decode
Port
Port
16K/32K/64K QuadPort Array
Port
Port
Port Logic Blocks[3]
Port Logic Blocks[3]
Notes: Port Control Logic Block detailed page Port Port Port Logic Blocks similar Port Logic Blocks. Counter functionality applies only CY7C0430BV (64K device option. These pins either CY7C04312BV CY7C04314BV.
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Port Operation-Control Logic Block Diagram
(Address Readback independent CEs) R/WP1
UBP1
CE0P1 CE1P1 LBP1 OEP1
I/O9P1-I/O17P1 I/O0P1-I/O8P1
Port-1 Control
Addr. Read
Port Readback Register MRST A0P1-A15P1 CNTRDP1[4] MKRDP1[4] MKLDP1[4] CNTINCP1[4] CNTLDP1[4] CNTRSTP1[4] CLKP1 MRST CNTINTP1[4]
Priority Decision Logic
Port Mask Register Port Address Decode
Port Counter/ Address Register LBP1 UBP1 R/WP1 CE0P1 CE1P1 OEP1 CLKP1 MRST
16K/32K/64K QuadPort Array
Port Interrupt Logic INTP1
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Configuration
272-ball Grid Array (BGA) View
Notes:
I/O17
I/O15
I/O13
I/O11
I/O9
I/O16
I/O14
I/O12
I/O10
I/O10
I/O12
I/O14
I/O16
I/O9
I/O11
I/O13
I/O15
I/O17
VDD1
I/O16
I/O14
I/O12
I/O10
I/O17
I/O13
I/O11
I/O11
I/O13
I/O17
I/O10
I/O12
I/O14
I/O16
VDD1
P1[9]
P1[8]
I/O15
VSS2
VSS2
I/O9
I/O9
VSS2
VSS2
I/O15
P4[8]
P4[9]
VSS1
VDD2
VSS2
VSS2
VDD2
VDD2
VSS2
VSS2
VDD2
VSS1
MKRD
CNTRD P1[6]
CNTRD
MKRD
CNTINT P1[7]
CNTINT P4[7]
VSS1
CNTINC P1[6]
CNTINC P4[6]
VSS1
MKLD
CNTLD P1[6]
CNTLD P4[6]
MKLD P4[6]
VDD1
GND[5]
GND[5]
GND[5]
GND[5]
VDD1
CNTRST P1[6]
GND[5]
GND[5]
GND[5]
GND[5]
CNTRST P4[6]
CNTRST P2[6]
GND[5]
GND[5]
GND[5]
GND[5]
CNTRST P3[6]
VDD1
GND[5]
GND[5]
GND[5]
GND[5]
VDD1
MKLD
CNTLD P2[6]
CNTLD P3[6]
MKLD P3[6]
VSS1
CNTINC P2[6]
CNTINC P3[6]
VSS1
CNTINT P2[7]
CNTINT P3[7]
MKRD
CNTRD P2[6]
CNTRD P3[6]
MKRD P3[6]
VSS1
VDD2
VSS2
VSS2
VDD2
VDD2
VSS2
VSS2
VDD2
VSS1
P2[9]
P2[8]
I/O6
VSS2
VSS2
I/O0
I/O0
VSS2
VSS2
I/O6
P3[8]
P3[9]
VDD1
I/O7
I/O5
I/O3
I/O1
I/O8
I/O4
I/O2
MRST
CLKBIST
I/O2
I/O4
I/O8
I/O1
I/O3
I/O5
I/O7
VDD1
I/O8
I/O6
I/O4
I/O2
I/O0
1/O7
I/O5
I/O3
I/O1
I/O1
I/O3
I/O5
I/O7
I/O0
I/O2
I/O4
I/O6
I/O8
Central Leads thermal dissipation only. They connected device VSS. CY7C04312BV CY7C04314BV devices. CY7C04312BV CY7C04314BV devices. CY7C04312BV CY7C04314BV devices. CY7C04314BV devices.
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Selection Guide
CY7C04312BV -133 fMAX2 Access Time (Clock Data) Operating Current Standby Current ISB1 (All ports Level) Standby Current ISB3 (All ports CMOS Level) 133[1] CY7C04312BV -100 Unit
Definitions
Port A0P1-A15P1 I/O0P1-I/O17P1 CLKP1 LBP1 Port A0P2-A15P2 I/O0P2-I/O17P2 CLKP2 LBP2 Port A0P3-A15P3 I/O0P3-I/O17P3 CLKP3 LBP3 Port A0P4-A15P4 I/O0P4-I/O17P4 CLKP4 LBP4 Description Address Input/Output. Data Input/Output. Clock Input. This input free running strobed. Maximum clock input rate fMAX. Lower Byte Select Input. Asserting this signal enables read write operations lower byte. read operations both signals must asserted drive output data lower byte data pins. Upper Byte Select Input. Same function upper byte. Chip Enable Input. select port, both must asserted their active states (CE0 VIH). Output Enable Input. This signal must asserted enable data lines during read operations. asynchronous input. Read/Write Enable Input. This signal asserted write dual port memory array. read operations, assert this HIGH. Master Reset Input. This signal Ports. MRST asynchronous input. Asserting MRST performs reset functions described text. MRST operation required power-up. CNTRSTP2[6] CNTRSTP3[6] CNTRSTP4[6] Counter Reset Input. Asserting this signal resets burst address counter respective port zero. CNTRST second MRST priority with respect counter mask register operations. Mask Register Load Input. Asserting this signal loads mask register with external address available address lines. MKLD operation higher priority over CNTLD operation. Counter Load Input. Asserting this signal loads burst counter with external address present address pins. Counter Increment Input. Asserting this signal increments burst address counter respective port each rising edge CLK.
UBP1 CE0P1,CE1P1
UBP2 CE0P2,CE1P2
UBP3 CE0P3,CE1P3
UBP4 CE0P4,CE1P4
OEP1
OEP2
OEP3
OEP4
R/WP1
R/WP2
R/WP3
R/WP4
MRST
CNTRSTP1[6]
MKLDP1[6]
MKLDP2[6]
MKLDP3[6]
MKLDP4[6]
CNTLDP1[6]
CNTLDP2[6]
CNTLDP3[6]
CNTLDP4[6]
CNTINCP1[6]
CNTINCP2[6]
CNTINCP3[6]
CNTINCP4[6]
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Definitions (continued)
Port CNTRDP1[6] Port CNTRDP2[6] Port CNTRDP3
Port CNTRDP4[6]
Description Counter Readback Input. When asserted LOW, internal address value counter will read back address lines. During CNTRD operation, both CNTLD CNTINC must HIGH. Counter readback operation higher priority over mask register readback operation. Counter readback operation independent port chip enables. address readback operation occurs with chip enables active (CE0 LOW, HIGH), data lines (I/Os) will three-stated. readback timing will valid after no-operation cycle plus tCD2 from rising edge next cycle. Mask Register Readback Input. When asserted LOW, value mask register will readback address lines. During mask register readback operation, counter MKLD inputs must HIGH (see Counter Mask Register Operations truth table). Mask register readback operation independent port chip enables. address readback operation occurs with chip enables active (CE0 LOW, HIGH), data lines (I/Os) will three-stated. readback will valid after no-operation cycle plus tCD2 from rising edge next cycle. Counter Interrupt Flag Output. Flag asserted clock cycle when counter wraps around location zero. Interrupt Flag Output. Interrupt permits communications between four ports. upper four memory locations used message passing. Example operation: INTP4 asserted when another port writes mailbox location Port Flag cleared when Port reads contents mailbox. same operation applicable ports JTAG Test Mode Select Input. controls advance JTAG state machine. State machine transitions occur rising edge TCK. JTAG Test Clock Input. This port external clock connected JTAG TAP. JTAG Test Data Input. This only data input. inputs will shift data serially selected register. JTAG Test Data Output. This only data output. transitions occur falling edge TCK. normally three-stated except when captured data shifted JTAG TAP. BIST Clock Input. Thermal Ground Heat Dissipation. Ground Input. Power Input. Address Lines Ground Input. Address Lines Power Input. Data Lines Ground Input. Data Lines Power Input.
MKRDP1[6]
MKRDP2[6]
MKRDP3[6]
MKRDP4[6]
CNTINTP1[7]
CNTINTP2[7]
CNTINTP3[7]
CNTINTP4[7]
INTP1
INTP2
INTP3
INTP4
CLKBIST VSS1 VDD1 VSS2 VDD2
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Maximum Ratings
(Above which useful life impaired. user guidelines, tested.) Storage Temperature -65°C 150°C Ambient Temperature with Power Applied.-55°C 125°C Supply Voltage Ground Potential -0.5V 4.6V Voltage Applied Outputs High-Z State .-0.5V 0.5V Input Voltage.-0.5V 0.5V Output Current into Outputs (LOW). Static Discharge Voltage 2200V Latch-up Current.
Operating Range
Range Commercial Industrial Ambient Temperature +70°C -40°C +85°C 3.3V 3.3V
Electrical Characteristics Over Operating Range
CY7C043XXBV -133 Parameter ISB1 Description Output HIGH Voltage (VCC Min., -4.0 Output Voltage (VCC Min., +4.0 Input HIGH Voltage Input Voltage Output Leakage Current Operating Current (VCC Max., IOUT Outputs Disabled, VIL, fmax Standby Current (four ports toggling Levels,0 active) CE1-4 VIH, fMAX Standby Current (four ports toggling Levels, active) VIL, fMAX Standby Current (four ports CMOS Level, active) CE1-4 VIH, Standby Current (four ports CMOS Level, active toggling) VIL, fMAX Min. Typ. Max. Min. -100 Typ. Max. Unit
ISB2
ISB3 ISB4
JTAG Electrical Characteristics Over Operating Range
Parameter VOH1 VOL1 Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input Leakage Current -100 Test Conditions -4.0 Min. Max. Unit
Capacitance
Parameter (All Pins) COUT (All Pins) (CLK Pins) COUT (CLK Pins) Description Input Capacitance Output Capacitance Input Capacitance Output Capacitance Test Conditions 25°C, MHz, 3.3V Max. Unit
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Test Load
[10] 1.5V OUTPUT 1.5V
OUTPUT
Normal Load
OUTPUT 3.3V 1.5V 3.0V
Three-State Delay
Load
Note: Test conditions:
Input Pulses
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Switching Characteristics Over Industrial Operating Range
[11]
CY7C04312BV -133 Parameter fMAX2[12] tCYC2[12] tCH2 tCL2 tSCLD tHCLD tSCINC tHCINC tSCRST tHCRST tSCRD tHCRD tSMLD tHMLD tSMRD tHMRD tOLZ[13] tOHZ tCD2 tCA2 tCM2 tCKHZ[14] tCKLZ[14]
[13]
-100 Max. Min. Max. Unit
Description Maximum Frequency Clock Cycle Time Clock HIGH Time Clock Time Clock Rise Time Clock Fall Time Address Set-up Time Address Hold Time Chip Enable Set-up Time Chip Enable Hold Time Set-up Time Hold Time Input Data Set-up Time Input Data Hold Time Byte Set-up Time Byte Hold Time CNTLD Set-up Time CNTLD Hold Time CNTINC Set-up Time CNTINC Hold Time CNTRST Set-up Time CNTRST Hold Time CNTRD Set-up Time CNTRD Hold Time MKLD Set-up Time MKLD Hold Time MKRD Set-up Time MKRD Hold Time Output Enable Data Valid Low-Z High-Z Clock Data Valid Clock Counter Address Readback Valid Clock Mask Register Readback Valid Data Output Hold After Clock HIGH Clock HIGH Output High-Z Clock HIGH Output Low-Z
Min.
Notes: data simultaneously written read same address location tCCS violated, data read from address, well subsequent data remaining address undefined. fMAX2 commercial MHz. tCYC2 Min. commercial This parameter guaranteed design, production tested. Valid both address data outputs.
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Switching Characteristics Over Industrial Operating Range (continued)[11]
CY7C04312BV -133 Parameter tSINT tRINT tSCINT tRCINT tRSR tROF tCCS[11] Description Clock Time Clock Reset Time Clock CNTINT Time Clock CNTINT Reset Time Master Reset Pulse Width Master Reset Recovery Time Master Reset Output Flags Reset Time Clock Clock Set-up Time (time required after write before read same address location) Min. Max. Min. -100 Max. Unit
Master Reset Timing
Port Port Delays
JTAG Timing Switching Waveforms
CY7C043XXBV -133/-100 Parameter fJTAG tTCYC tTMSS tTMSH tTDIS tTDIH tTDOV tTDOX fBIST Description Maximum JTAG Controller Frequency Clock Cycle Time Clock High Time Clock Time Set-up Clock Rise Hold After Clock Rise Set-up Clock Rise Hold after Clock Rise Clock Valid Clock Invalid Maximum CLKBIST Frequency CLKBIST High Time CLKBIST Time Min. Max. Unit
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Test Clock tTCYC tTMSH Test Mode Select tTMSS
tTDIS Test Data-In
tTDIH
Test Data-Out tTDOX tTDOV
Switching Waveforms
Master Reset[15]
tCH2 tCYC2 tCL2
MRST ADDRESS/ DATA LINES OTHER INPUTS TMS[16] CNTINT tRSF
tRSR INACTIVE
ACTIVE
Notes: set-up time required input control signals. Reset test port without resetting device, must held five clock cycles.
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Switching Waveforms (continued)
Read Cycle[17,
tCYC2 tCH2 tCL2
ADDRESS DATAOUT Latency An+1 tCD2 tCKLZ
Notes: asynchronously controlled; other inputs (excluding MRST) synchronous rising clock edge. CNTLD VIL, MKLD VIH, CNTINC MRST CNTRST VIH. output disabled (high-impedance state) following next rising edge clock. Addresses have accessed sequentially. Note indicates that address constantly loaded rising edge CLK. Numbers reference only. internal signal. VIH.
An+2 Qn+1 tOHZ
An+3
Qn+2 tOLZ
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Switching Waveforms (continued)
Bank Select Read[22,
tCH2 ADDRESS(B1) CE(B1) tCD2 DATAOUT(B1) ADDRESS (B2) CE(B2) DATAOUT(B2) tCKLZ tCD2 tCKLZ tCKHZ tCD2 tCD2 tCKLZ tCKHZ tCD2 tCKHZ tCYC2 tCL2
Read-to-Write-to-Read VIL)[24,
tCH2 tCYC2 tCL2
ADDRESS DATAIN tCD2 An+1 An+2
An+2
An+3
An+4
tCKHZ
Dn+2
tCD2 Qn+3 tCKLZ
DATAOUT Read
Operation
Write
Read
Notes: this depth expansion example, represents Bank Bank Each bank consists QuadPort device from this data sheet. ADDRESS(B1) ADDRESS(B2). CNTLD VIL; MRST CNTRST= MKLD VIH. Output state (HIGH, LOW, high-impedance) determined previous cycle control signals. CNTLD VIL; MRST CNTRST MKLD VIH. Addresses have accessed sequentially since CNTLD constantly loads address rising edge CLK; numbers reference only. During Operation," data memory selected address corrupted should rewritten ensure data integrity.
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Switching Waveforms (continued)
Read-to-Write-to-Read Controlled)[24,
tCH2 tCYC2 tCL2
An+1 An+2 Dn+2 tCD2 Dn+3 tCD2 tOHZ tCKLZ Qn+4 An+3 An+4 An+5
ADDRESS DATAIN
DATAOUT
Read Write Read
Read with Address Counter Advance[28,
tCH2 ADDRESS tSCLD CNTLD tSCINC CNTINC tCD2 DATAOUT Qx-1 Read External Address Read with Counter Qn+1 Counter Hold Qn+2 Qn+3 tHCINC tHCLD tCYC2 tCL2
Read with Counter
Notes: VIL; CNTRST MRST MKLD MKRD CNTRD VIH. "Internal Address" equal "External Address" when CNTLD VIL.
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Switching Waveforms (continued)
Write with Address Counter Advance [29,
tCH2 ADDRESS tCYC2 tCL2
INTERNAL ADDRESS tSCLD CNTLD tHCLD
An+1
An+2
An+3
An+4
CNTINC tSCINC DATAIN Write External Address tHCINC Dn+1 Write with Counter Dn+1 Write Counter Hold Dn+2 Dn+3 Dn+4
Write with Counter
Notes: VIL; CNTRST MRST MKLD MKRD CNTRD VIH. Counter operation only available CY7C0430BV. CY7C04312BV CY7C04314BV support counter functions.
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Switching Waveforms (continued)
Counter Reset [26,
tCH2 ADDRESS INTERNAL ADDRESS An+1 An+1 tCYC2 tCL2
tSCLD CNTLD tHCLD
CNTINC tSCRST CNTRST DATAIN tHCRST An+2
DATAOUT Counter Reset Write Address Read Address
Read Address Read Address
Notes: VIL; MRST MKLD MKRD CNTRD VIH. dead cycle exists during counter reset. Read Write cycle coincidental with counter reset.
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Switching Waveforms (continued)
Load Read Address Counter[31,
tCH2 A0-A15 tSCLD CNTLD tHCLD tCYC2 tCL2
Note
tCKLZ tCA2
Note
tCKHZ An+2[37]
CNTINC tSCINC CNTRD tHCINC
tSCRD
tHCRD
INTERNAL ADDRESS
An+1
An+2
An+2
An+2
tCD2 DATAOUT Qx-1 Load External Address
tCKHZ Qn+1 Qn+2 Read Internal Address
tCKLZ Qn+2
Read Data with Counter
Notes: VIL; CNTRST MRST MKLD MKRD VIH. Address output mode. Host must driving address after time tCKLZ next clock cycle. Address input mode. Host drive address after tCKHZ. This value address counter being read address lines.
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Switching Waveforms (continued)
Load Read Mask Register [31,
tCH2 A0-A15 tSMLD MKLD tHMLD tCYC2 tCL2
Note
tCKLZ tCA2
Note
tCKHZ [39]
tSMRD MKRD MASK INTERNAL VALUE Load Mask Register Value
Notes: VIL; CNTRST MRST CNTLD CNTRD CNTINC =VIH. This value Mask Register read address lines.
tHMRD
Read Mask Register Value
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Switching Waveforms (continued)
Port Write Port Read[40,
tCH2 CLKP1 PORT-1 ADDRESS R/WP1 tCKHZ tCCS tCYC2 tCL2
PORT-1
DATAIN tCYC2 tCL2 tCH2
tCKLZ
CLKP2
PORT-2 ADDRESS
R/WP2 tCD2
PORT-2
DATAOUT
Notes: CNTLD =VIL; CNTRST MRST MKLD MKRD CNTRD CNTINC =VIH. This timing valid when port writing, more three other ports reading same location same time. tCCS violated, indeterminate data will read out. tCCS< minimum specified value, then Port will read most recent data (written Port only (2*tCYC2 tCD2) after rising edge Port clock. tCCS minimum specified value, then Port will read most recent data (written Port (tCYC2 tCD2) after rising edge Port clock.
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Switching Waveforms (continued)
Counter Interrupt [31,
tCH2 tCYC2 tCL2
EXTERNAL ADDRESS tSMLD MKLD
007Fh
xx7Dh tHMLD
tSCLD CNTLD
tHCLD
tSCINC CNTINC
tHCINC
COUNTER INTERNAL ADDRESS
xx7Dh
xx7Eh
xx7Fh tSCINT
xx00h
xx00h tRCINT
CNTINT
Mailbox Interrupt Timing[46,
tCH2 CLKP1 PORT-1 ADDRESS INTP2 tCYC2 tCL2 tSINT tRINT An+1 An+2 An+3 tCYC2 tCL2
FFFE
tCH2 CLKP2
PORT-2 ADDRESS
Am+1 FFFE Am+3 Am+4
Notes: VIL; CNTRST MRST CNTRD MKRD VIH. CNTINT always driven. CNTINC goes counter address masked portion incremented from xx7Fh xx00h. "Don't Care." CNTLD =VIL; CNTRST MRST CNTRD CNTINC MKRD MKLD =VIH. Address "FFFE" mailbox location Port Port configured Write operation, Port configured Read operation. Port Port used simplicity. four ports write read from mailbox. Interrupt flag with respect rising edge write clock, reset with respect rising edge read clock.
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Table Read/Write Enable Operation (Any Port)[51, Inputs Outputs I/O0-I/O17 High-Z High-Z DOUT High-Z Deselected Deselected Write Read Outputs Disabled Operation
Table Address Counter Counter-Mask Register Control Operation (Any Port)[31, MRST CNTRST MKLD CNTLD CNTINC CNTRD MKRD Mode MasterReset Reset Load Load Operation Counter/Address Register Reset Mask Register (resets entire chip reset state table) Counter/Address Register Reset Load Address Lines into Mask Register Load Address Lines into Counter/Address Register
Increment Counter Increment Readback Readback Counter Address Lines Readback Readback Mask Register Address Lines Hold Counter Hold
Notes: "Don't Care," VIH, VIL. asynchronous input signal. When changes state, deselection read happen after cycle latency. VIL; VIH. Counter operation mask register operation independent Chip Enables.
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Master Reset
QuadPort device undergoes complete reset taking Master Reset (MRST) input LOW. Master Reset input switch asynchronously clocks. Master Reset initializes internal burst counters zero, counter mask registers ones (completely unmasked). Master Reset also forces Mailbox Interrupt (INT) flags Counter Interrupt (CNTINT) flags HIGH, resets BIST controller, takes registered control signals deselected read state.[56] Master Reset must performed QuadPort device after power-up. mailbox Port FFFE mailbox Port FFFD mailbox Port FFFC mailbox Port Table shows that order Port INTP1 flag, write other port address FFFF will assert INTP1 LOW. read FFFF location Port will reset INTP1 HIGH. When port writes other port's mailbox, Interrupt flag (INT) port that mailbox belongs asserted LOW. Interrupt reset when owner (port) mailbox reads contents mailbox. interrupt flag flow-through mode (i.e., follows clock edge writing port). Also, flag reset flow-through mode (i.e., follows clock edge reading port). Each port read other port's mailbox without resetting interrupt. application does require message passing, pins should treated no-connect should left floating. When ports more write same mailbox same time will asserted contents mailbox guaranteed valid.
Interrupts
upper four memory locations used message passing permit communications between ports. Table shows interrupt operation ports. 1-Mb QuadPort device, highest memory location FFFF Table Interrupt Operation Example Port Function Port INTP1 Flag Reset Port INTP1 Flag Port INTP2 Flag Reset Port INTP2 Flag Port INTP3 Flag Reset Port INTP3 Flag Port INTP4 Flag Reset Port INTP4 Flag A0P1-15P1 FFFF FFFE FFFD FFFC INTP1
Port A0P2-15P2 FFFF FFFE FFFD FFFC INTP2
Port A0P3-15P3 FFFF FFFE FFFD FFFC INTP3
Port A0P4-15P4 FFFF FFFE FFFD FFFC INTP
Note: During Master Reset control signals will deselected read state: CE0I R/WI MKLDI MKRDI CNTRDI CNTRSTI CNTLDI CNTINCI VIH; CE1I VIL. suffix these signals denotes that these internal registered equivalent associated signals.
Address Counter Control Operations[31]
Counter enable inputs provided stall operation address input utilize internal address generated internal counter fast interleaved memory applications. port's burst counter loaded with port's Counter Load (CNTLD). When port's Counter Increment (CNTINC) asserted, address counter will increment each HIGH transition that port's clock signal. This will read/write word from/into each successive address location until CNTINC deasserted. Depending mask register state, counter address entire memory array will loop back start. Counter Reset (CNTRST) used reset Burst Counter (the Mask Register value unaffected). When using counter readback mode, internal address value counter will read back address lines when Counter Readback Signal (CNTRD) asserted.
Figure provides block diagram readback operation. Table lists control signals required counter operations. signals listed based their priority. example, Master Reset takes precedence over Counter Reset, Counter Load lower priority than Mask Register Load (described below). counter operations independent Chip Enables (CE0 CE1). When address readback operation performed data I/Os three-stated active) one-clock cycle (no-operation cycle) latency experienced. address will read time tCA2 from rising edge clock following no-operation cycle. read back address either burst counter mask register based levels Counter Read signal (CNTRD) Mask Register Read signal (MKRD). Both signals synchronized port's clock shown Table Counter read higher priority than mask read.
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CNTRD MKRD
Readback Register
Addr. Readback
MKLD Bidirectional Address Lines Mask Register
Memory Array
CNTINC CNTLD CNTRST
Counter/ Address Register
Figure Counter Mask Register Read Back Address Lines
Counter-Mask Register[31]
Example: Load Counter-Mask Register CNTINT
Mask Register bit-0 Address Counter bit-0
Blocked Address Load Address Counter Address Register Address Register burst counter mask register that controls when where counter wraps. interrupt flag (CNTINT) asserted clock cycle when unmasked portion counter address wraps around from ones (CNTINC must asserted) zeros. example Figure shows counter mask register loaded with mask value 003F Document 38-06027 Rev.
Counter Address
unmasking first bits with "15" MSB. maximum value mask register loaded with FFFF. Setting mask register this value allows counter access entire memory space. address counter then loaded with initial value XXX8. "blocked" addresses this case, address through Page
Figure Programmable Counter-Mask Register Operation[57]
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15th address) loaded with address increment once loaded. counter address will start address XXX8. With CNTINC asserted LOW, counter will increment internal address value till reaches mask register value wraps around memory block location XXX0. Therefore, counter uses mask-register define wrap-around point. mask register every port loaded when MKLD (mask register load) that port LOW. When MKRD LOW, value mask register read address lines manner similar counter read back operation (see Table required conditions). When burst counter loaded with address higher than mask register value, higher addresses will form masked portion counter address called blocked addresses. blocked addresses will changed affected counter increment operation. only exception mask register masked allow address counter increment two. mask register loaded with logic value "0," then address counter masked changed during counter increment operation. loaded value address counter "0," counter will increment address values even. loaded value address counter "1," counter will increment address values odd. This operations allows user achieve 36-bit interface using ports, where counter port counts even addresses counter other port counts addresses. This even-odd address scheme stores half 36-bit word even memory locations, other half memory locations. CNTINT will asserted when unmasked portion counter wraps zeros. Loading mask register with allows counter increment address value sequentially. Table groups operations mask register with operations address counter. Address counter mask register signals synchronized port's clock CLK. Master reset (MRST) only asynchronous signal listed Table Signals listed based their priority going from left column right column with MRST being highest. MRST will reset both counter register zeros mask register ones. other hand, CNTRST will only clear address counter register zeros mask register will remain intact. There four operations counter mask register: Load operation: When CNTLD MKLD LOW, address counter mask register loaded with address value presented address lines. This value ranges from FFFF (64K). mask register load operation higher priority over address counter load operation. Increment: Once address counter loaded with external address, counter internally increment address value asserting CNTINC LOW. counter address entire memory array (depend value mask register) loop back location increment operation second priority load operation. Readback: internal value either burst counter mask register read address lines when CNTRD MKRD LOW. Counter readback higher priority over mask register readback. no-operation delay cycle experienced when readback operation performed. address will valid after tCA2 (for counter Document 38-06027 Rev. readback) tCM2 (for mask readback) from following port's clock rising edge. Address readback operation independent port's chip enables (CE0 CE1). address readback occurs while port enabled (chip enables active), data lines (I/Os) will three-stated. Hold operation: order hold value address counter certain address, signals Table have HIGH. This operation least priority. This operation useful many applications where wait states needed when address available cycles ahead data. counter mask register operations totally independent port chip enables.
IEEE 1149.1 Serial Boundary Scan (JTAG) Memory Built-In-Self-Test (MBIST)
CY7C0430BV incorporates serial boundary scan test access port (TAP). This port fully compatible with IEEE Standard 1149.1-2001[58]. operates using JEDEC standard 3.3V logic levels. composed three input connections output connection required test logic defined standard. Memory BIST circuitry will also controlled through interface. MBIST instructions compliant JTAG standard. external clock (CLKBIST) provided allow user BIST speeds MHz. CLKBIST multiplexed internally with ports clocks during BIST operation. Disabling JTAG Feature possible operate QuadPort device without using JTAG feature. disable controller, must tied (VSS) prevent clocking device. internally pulled unconnected. They alternately connected through pull-up resistor. should left unconnected. CLKBIST must tied disable MBIST. Upon power-up, device will come reset state which will interfere with operation device. Test Access Port (TAP)-Test Clock (TCK) test clock used only with controller. inputs captured rising edge TCK. outputs driven from falling edge TCK. Test Mode Select input used give commands controller sampled rising edge TCK. allowable leave this unconnected used. pulled internally, resulting logic HIGH level. Test Data-In (TDI) used serially input information into registers connected input registers. register between chosen instruction that loaded into instruction register. information loading instruction register, Controller State Diagram. internally pulled unconnected unused application. connected most significant (MSB) register.
Notes: this diagram represents counter upper-bits. Master Reset will reset JTAG controller.
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Test Data (TDO) output used serially clock data-out from registers. output active depending upon current state state machine (see Controller State Diagram (FSM)). output changes falling edge TCK. connected least significant (LSB) register. Performing Reset Reset performed forcing HIGH (VDD) five rising edges TCK. This RESET does affect operation QuadPort device performed while device operating. power-up, reset internally ensure that comes High-Z state. Registers Registers connected between pins allow data scanned into QuadPort device test circuitry. Only register selected time through instruction registers. Data serially loaded into rising edge TCK. Data output falling edge TCK. Instruction Register Four-bit instructions serially loaded into instruction register. This register loaded when placed between pins shown following JTAG/BIST Controller diagram. Upon power-up, instruction register loaded with IDCODE instruction. also loaded with IDCODE instruction controller placed reset state described previous section. When controller CaptureIR state, least significant bits loaded with binary "01" pattern allow fault isolation board level serial test path. Bypass Register save time when serially shifting data through registers, sometimes advantageous skip certain devices. bypass register single-bit register that placed between pins. This allows data shifted through QuadPort device with minimal delay. bypass register (VSS) when BYPASS instruction executed. Boundary Scan Register boundary scan register connected input output pins QuadPort device. boundary scan register loaded with contents QuadPort device Input Output ring when controller Capture-DR state then placed between pins when controller moved Shift-DR state. EXTEST, SAMPLE/PRELOAD instructions used capture contents Input Output ring. Identification (ID) Register register loaded with vendor-specific, 32-bit code during Capture-DR state when IDCODE command loaded instruction register. IDCODE hardwired into QuadPort device shifted when controller Shift-DR state. register vendor code other information described Identification Register Definitions table. Instruction Sixteen different instructions possible with 4-bit instruction register. combinations listed Table Instruction Codes. Seven these instructions (codes) listed RESERVED should used. other nine instructions described detail below. controller used this QuadPort device fully compatible[58] with 1149.1 convention. controller used load address, data control signals into QuadPort device preload Input output buffers. QuadPort device implements 1149.1 instructions except INTEST. Table lists instructions. Instructions loaded into controller during Shift-IR state when instruction register placed between TDO. During this state, instructions shifted through instruction register through pins. execute instruction once shifted controller needs moved into Update-IR state. EXTEST EXTEST mandatory 1149.1 instruction which executed whenever instruction register loaded with EXTEST allows circuitry external QuadPort device package tested. Boundary-scan register cells output pins used apply test stimuli, while those input pins capture test results. IDCODE IDCODE instruction causes vendor-specific, 32-bit code loaded into identification register. also places identification register between pins allows IDCODE shifted device when controller enters Shift-DR state. IDCODE instruction loaded into instruction register upon power-up whenever controller given test logic reset state. High-Z High-Z instruction causes bypass register connected between pins when controller Shift-DR state. also places QuadPort device outputs into High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD 1149.1 mandatory instruction. When SAMPLE/PRELOAD instructions loaded into instruction register controller Capture-DR state, snapshot data inputs output pins captured boundary scan register. user must aware that controller clock only operate frequency MHz, while QuadPort device clock operates more than order magnitude faster. Because there large difference clock frequencies, possible that during Capture-DR state, input output will undergo transition. then capture signal while transition (metastable state). This will harm device, there guarantee value that will captured. Repeatable results possible. guarantee that boundary scan register will capture correct value signal, QuadPort device signal must stabilized long enough meet controller's Page
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capture set-up plus hold times. Once data captured, possible shift data putting into Shift-DR state. This places boundary scan register between pins. controller goes into Update-DR state, sampled data will updated. BYPASS When BYPASS instruction loaded instruction register placed Shift-DR state, bypass register placed between pins. advantage BYPASS instruction that shortens boundary scan path when multiple devices connected together board. CLAMP optional CLAMP instruction allows state signals driven from QuadPort device pins determined from boundary-scan register while BYPASS register selected serial path between TDO. CLAMP controls boundary cells CYBIST CYBIST instruction provides user with means running user-accessible self-test function within QuadPort device result single instruction. This permits components board that offer CYBIST instruction execute their self-tests concurrently, providing quick check board. QuadPort device MBIST provides modes operation once controller loaded with CYBIST instruction: Non-Debug Mode (Go-NoGo) non-debug mode go-nogo test used simply BIST obtain pass-fail information after test run. addition that, total number failures encountered obtained. This information used debug mode (explained next) operation. pass-fail information failure count scanned using JTAG interface. MBIST Result Register (MRR) will used store pass-fail results. 25-bit register that will connected between during internal scan (INT_SCAN) operation. will contain total number fail read cycles entire MBIST sequence. MRR[0] (bit Pass/Fail bit. indicates some type failure occurred, indicates entire memory pass. order BIST non-debug mode, two-bit MBIST Control Register (MCR) loaded with default value "00", controller's finite state machine (FSM), which synchronous TCK, transitions Test/Idle state. entire MBIST test will performed with deterministic number cycles depending CLKBIST frequency. tCYC CLKBIST tCYC tCYC total number cycles required MBIST. Synchronization Padding Cycles (4-6 cycles). constant represents number read write operations required MBIST algorithms (31195136). Once entire MBIST sequence completed, supplying extra CLKBIST cycles will have effect MBIST controller state pass-fail status. Debug Mode With CYBIST instruction loaded loaded with value "01," transitions RUN_TEST/IDLE state, MBIST goes into CYBIST-debug mode. debug mode will used provide complete failure analysis information board level. recommended that user runs non-debug mode first then debug mode order save test time upper bound number scan outs that will needed. failure data will scanned automatically once failure occurs using JTAG interface. failure data will represented 100-bit packet given below. 100-bit Memory Debug Register (MDR) will connected between TDO, will shifted TDO, which synchronized TCK.
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P4_IO(17-9) P4_IO(8-0) A(15-0) MBIST_State Figure MBIST Debug Register Packet Figure representation 100-bit packet. packet follows two-bit header that logic value, represents cycles. MDR[97:26] represent BIST comparator values four ports (each port data lines). value indicates failure. scanned data from MSB. MDR[25:10] represent failing address (MSB LSB). state BIST controller scanned using MDR[9:4]. Test Done bit. means test complete. user monitor this every packet determine more failure packets need scanned BIST operations. value then BIST must repeated capture next failing packet. "1," means that last failing packets have been scanned out. trailer similar header represents packet. MCR_SCAN This instruction will connect Memory BIST Control Register (MCR) between TDO. default value (upon master reset) "00." Shift_DR state will allow modifying extend MBIST functionality. MBIST Control States Thirty-five states listed Table Four data algorithms used debug mode: moving inversion (MIA), march_2 (M2A), checkerboard (CBA), unique address algorithm (UAA). Only Port write MIA, M2A, data memory. four ports read algorithm data from QuadPort device memory. Ports will only write data. Boundary Scan Cells (BSC) Table lists QuadPort family I/Os with their associated BSC. Note that cells have even numbers. Every boundary scan cells. Bidirectional signals (address lines, datalines) require cells that (the cell) used control three-state buffer. Input only output only signals have extra dummy cell (odd cells) that used ease device layout. P3_IO(17-9) P3_IO(8-0) P2_IO(17-9) P2_IO(8-0) P1_IO(17-9) P1_IO(8-0)
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Controller State Diagram (FSM)[59] TEST-LOGIC RESET RUN_TEST/ IDLE SELECT DR-SCAN CAPTURE-DR SHIFT-DR EXIT1-DR PAUSE-DR EXIT2-DR UPDATE-DR EXIT2-IR UPDATE-IR CAPTURE-IR SHIFT-IR EXIT1-IR PAUSE-IR SELECT IR-SCAN
Note: "0"/"1" next each state represents value rising edge TCK.
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JTAG/BIST Controller Block Diagram
Bypass Register (BYR)
MBIST Control Register (MCR)
Instruction Register (IR) Selection Circuitry
MBIST Result Register (MRR)
Identification Register (IDR) MBIST Debug Register (MDR) Boundary Scan Register (BSR)
(MUX)
BIST CONTROLLER CLKBIST
CONTROLLER
MRST
MEMORY CELL
Table Identification Register Definitions Instruction Field Revision Number (31:28) Cypress Device (27:12) Cypress JEDEC (11:1) Register Presence C000h Value Description Reserved version number Defines Cypress part number Allows unique identification QuadPort device vendor Indicate presence register
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Table Scan Registers Sizes Register Name Instruction (IR) Bypass (BYR) Identification (IDR) MBIST Control (MCR) MBIST Result (MRR) MBIST Debug (MDR) Boundary Scan (BSR) Size
Table Instruction Identification Codes Instruction EXTEST BYPASS IDCODE HIGHZ CLAMP SAMPLE/PRELOAD CYBIST INT_SCAN MCR_SCAN RESERVED Code 0000 1111 0111 0110 0101 0001 1000 0010 0011 other codes Description Captures Input/Output ring contents. Places boundary scan register (BSR) between TDO. Places bypass register (BYR) between TDO. Loads register (IDR) with vendor code places register between TDO. Places between TDO. Forces QuadPort device output drivers High-Z state. Controls boundary 1/0. Uses BYR. Captures Input/Output ring contents. Places boundary scan register (BSR) between TDO. Invokes MBIST. Places MBIST Debug register (MDR) between TDO. Scans pass-fail information. Places MBIST Result Register (MRR) between TDO. Presets CYBIST mode. Places MBIST Control Register (MCR) between TDO. Seven combinations reserved. other than above.
Table MBIST Control States States Code 000001 000011 State Name movi_zeros movi_1_upcnt Description Port write zeros QuadPort device memory using Moving Inversion Algorithm (MIA). count from (depth QuadPort device). ports read then Port writes memory locations using MIA, then ports read read0_write1_read1 (MIA_r0w1r1). count from 64K. ports read then Port writes then ports read (MIA_r1w0r0). Down count from MIA_r0w1r1. Down count MIA_r1w0r0. Read Port write zeros memory using March2 Algorithm (M2A). count M2A_r0w1r1. count M2A_r1w0r0. Down count M2A_r0w1r1.
000010 000110 000111 000101 000100 001100 001101 001111
movi_0_upcnt movi_1_downcnt movi_0_downcnt movi_read mar2_zeros mar2_1_upcnt mar2_0_upcnt mar2_1_downcnt
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Table MBIST Control States (continued) States Code 001110 001010 001011 001001 001000 011000 011001 011011 011010 011110 011111 011101 011001 011011 011010 011110 011111 011101 011001 011011 011010 011110 011111 011101 110010 State Name mar2_0_downcnt mar2_read chkr_w chkr_r n_chkr_w n_chkr_r uaddr_zeros2 uaddr_write2 uaddr_read2 uaddr_ones2 n_uaddr_write2 n_uaddr_read2 uaddr_zeros3 uaddr_write3 uaddr_read3 uaddr_ones3 n_uaddr_write3 n_uaddr_read3 uaddr_zeros4 uaddr_write4 uaddr_read4 uaddr_ones4 n_uaddr_write4 n_uaddr_read4 complete Down count M2A_r1w0r0. Read Port writes topological checkerboard data memory. ports read topological checkerboard data. Port write inverse topological checkerboard data. ports read inverse topological checkerboard data. Port write zeros memory using Unique Address Algorithm (UAA). Port writes every address value into memory location (UAA). ports read data. Port writes ones memory. Port writes inverse address value into memory. ports read inverse data. Port write zeros memory using Unique Address Algorithm (UAA). Port writes every address value into memory location (UAA). ports read data. Port writes ones memory. Port writes inverse address value into memory. ports read inverse data. Port write zeros memory using Unique Address Algorithm (UAA). Port writes every address value into memory location (UAA). ports read data. Port writes ones memory. Port writes inverse address value into memory. ports read inverse data. Test complete. Table Boundary Scan Order (continued) Mode Non-Debug Debug Reserved Reserved Cell Bump (Ball) Signal Name A7_P4 A8_P4 A9_P4 A10_P4 A11_P4 A12_P4 A13_P4 A14_P4 A15_P4 CNTINT_P4 CNTRST_P4 MKLD_P4 CNTLD_P4 Bump (Ball) Description
Table MBIST Control Register (MCR) MCR[1:0] Table Boundary Scan Order Cell Signal Name A0_P4 A1_P4 A2_P4 A3_P4 A4_P4 A5_P4 A6_P4
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Table Boundary Scan Order (continued) Cell Signal Name CNTINC_P4 CNTRD_P4 MKRD_P4 LB_P4 UB_P4 OE_P4 R/W_P4 CE1_P4 CE0_P4 INT_P4 CLK_P4 A0_P3 A1_P3 A2_P3 A3_P3 A4_P3 A5_P3 A6_P3 A7_P3 A8_P3 A9_P3 A10_P3 A11_P3 A12_P3 A13_P3 A14_P3 A15_P3 CNTINT_P3 CNTRST_P3 MKLD_P3 CNTLD_P3 CNTINC_P3 CNTRD_P3 MKRD_P3 LB_P3 UB_P3 OE_P3 R/W_P3 CE1_P3 CE0_P3 INT_P3 Bump (Ball) Table Boundary Scan Order (continued) Cell Signal Name CLK_P3 IO0_P4 IO1_P4 IO2_P4 IO3_P4 IO4_P4 IO5_P4 IO6_P4 IO7_P4 IO8_P4 IO0_P3 IO1_P3 IO2_P3 IO3_P3 IO4_P3 IO5_P3 IO6_P3 IO7_P3 IO8_P3 IO0_P1 IO1_P1 IO2_P1 IO3_P1 IO4_P1 IO5_P1 IO6_P1 IO7_P1 IO8_P1 IO0_P2 IO1_P2 IO2_P2 IO3_P2 IO4_P2 IO5_P2 IO6_P2 IO7_P2 IO8_P2 A0_P2 A1_P2 A2_P2 A3_P2 Bump (Ball)
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Table Boundary Scan Order (continued) Cell Signal Name A4_P2 A5_P2 A6_P2 A7_P2 A8_P2 A9_P2 A10_P2 A11_P2 A12_P2 A13_P2 A14_P2 A15_P2 CNTINT_P2 CNTRST_P2 MKLD_P2 CNTLD_P2 CNTINC_P2 CNTRD_P2 MKRD_P2 LB_P2 UB_P2 OE_P2 R/W_P2 CE1_P2 CE0_P2 INT_P2 CLK_P2 A0_P1 A1_P1 A2_P1 A3_P1 A4_P1 A5_P1 A6_P1 A7_P1 A8_P1 A9_P1 A10_P1 A11_P1 A12_P1 A13_P1 Bump (Ball) Table Boundary Scan Order (continued) Cell Signal Name A14_P1 A15_P1 CNTINT_P1 CNTRST_P1 MKLD_P1 CNTLD_P1 CNTINC_P1 CNTRD_P1 MKRD_P1 LB_P1 UB_P1 OE_P1 R/W_P1 CE1_P1 CE0_P1 INT_P1 CLK_P1 IO9_P2 IO10_P2 IO11_P2 IO12_P2 IO13_P2 IO14_P2 IO15_P2 IO16_P2 IO17_P2 IO9_P1 IO10_P1 IO11_P1 IO12_P1 IO13_P1 IO14_P1 IO15_P1 IO16_P1 IO17_P1 IO9_P3 IO10_P3 IO11_P3 IO12_P3 IO13_P3 IO14_P3 Bump (Ball)
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Table Boundary Scan Order (continued) Cell Signal Name IO15_P3 IO16_P3 IO17_P3 IO9_P4 IO10_P4 IO11_P4 IO12_P4 IO13_P4 IO14_P4 IO15_P4 IO16_P4 IO17_P4 Bump (Ball)
Ordering Information
Gb/s 3.3V QuadPort Family (64K Speed (MHz) Ordering Code CY7C0430BV-133BGC CY7C0430BV-133BGI CY7C0430BV-100BGC CY7C0430BV-100BGI Package Name BG272 BG272 BG272 BG272 Package Type 272-ball Grid Array (BGA) 272-ball Grid Array (BGA) 272-ball Grid Array (BGA) 272-ball Grid Array (BGA) Operating Range Commercial Industrial Commercial Industrial
Gb/s 3.3V QuadPort Family (32K Speed (MHz) Ordering Code CY7C04312BV-133BGC CY7C04312BV-100BGC Package Name BG272 BG272 Package Type 272-ball Grid Array (BGA) 272-ball Grid Array (BGA) Operating Range Commercial
Gb/s 3.3V QuadPort Family (16K Speed (MHz) Ordering Code CY7C04314BV-133BGC CY7C04314BV-100BGC Package Name BG272 BG272 Package Type 272-ball Grid Array (BGA) 272-ball Grid Array (BGA) Operating Range Commercial
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Package Diagram
272-ball Ball Grid Array 1.27 BG272
51-85130
QuadPort trademark Cypress Semiconductor Corporation. product company names mentioned this document trademarks their respective holders.
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Cypress Semiconductor Corporation, 2002. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.
CY7C0430BV CY7C04312BV CY7C04314BV
Document Title: CY7C430BV, CY7C04312BV, CY7C04314BV Gb/s 3.3V QuadPort Family Document Number: 38-06027 REV. 109906 115042 Issue Date 09/10/01 05/23/02 Orig. Change Description Change Change from Spec number: 38-01052 38-06027 Remove Preliminary, from DSE. Change RUNBIST CYBIST. Updated values. Added notes Increased commercial prime MHz.
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Gb/s 3.3V QuadPortDSE Family QuadPortdatapath switching element (

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