Powerful Instructions (Most Executed Single Clock Cycle) Power Idle Po

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Powerful Instructions (Most Executed Single Clock Cycle) Power Idle Po

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High-performance, Low-power secureAVREnhanced RISC Architecture
Powerful Instructions (Most Executed Single Clock Cycle) Power Idle Power-down Modes Bond Locations Conforming 7816-2 Protection 6000V Operating Range: 1.62V 5.5V Compliant with GSM, 3GPP 2000 Specifications; Industry Compatible Available Wafers, Modules Industry-standard Packages
Memory
256K Bytes User Program Memory Bytes Dedicated Atmel's Crypto-library Bytes EEPROM, Including Bytes 384-byte Bit-addressable Area
128-byte Program/Erase 1.25 Program 1.25 Erase Typically More than 500,000 Write/Erase Cycles Temperature 25°C Years Data Retention EEPROM Erase Only Mode Write EEPROM With Without Autoerase Bytes
Secure Microcontroller Smart Cards AT90SC 25672RCT (-USB) Preliminary Summary
Peripherals
7816 Controller
kbps Compliant with Protocols Port Optional Full Speed interface with endpoints controller Programmable Internal Oscillator Crypto Accelerator) 16-bit Timers Random Number Generator (RNG) 2-level, 9-vector Interrupt Controller Hardware Triple DPA/DEMA Resistant Checksum Accelerator Engine (Compliant with ISO/IEC 3309) 32-bit AdvXCryptographic Accelerator Public Operations with GF(2n) Multiplier Firmware (RSA, ECC, Generation)
Security
Dedicated Hardware Protection Against SPA/DPA/SEMA/DEMA Attacks Advanced Protection Against Physical Attack, Including Active Shield Environmental Protection Systems Voltage Monitor Frequency Monitor Light Protection Temperature Monitor Secure Memory Management/Access Protection (Supervisor Mode)
Development Tools
Voyager Emulation Platform (ATV4 Advanced) Support Software Development Systems EWAVR® V3.10 Debugger Atmel's Studio® Version 4.07 Above Software Libraries Application Notes
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Description
AT90SC25672RCT(-USB) low-power, high-performance, 8/16-bit microcontroller with program memory, EEPROM data memory, cryptographic accelerator based secureAVR enhanced RISC architecture. executing powerful instructions single clock cycle, AT90SC25672RCT(-USB) achieves throughputs close MIPS MHz. Harvard architecture includes generalpurpose working registers directly connected ALU, allowing independent registers accessed single instruction executed clock cycle. AT90SC25672RCT(-USB) uses AVR® architecture, secureAVR that allows linear addressing bytes code bytes data well number functional security features. cryptographic accelerator featured this product AdvX, 32-bit accelerator dedicated performing fast encryption authentication functions. combined with byte-ROM high-performance secure crypto firmware. ability EEPROM code space allows parts program memory reprogrammed in-system. This technology combined with versatile 8/16-bit monolithic chip provides highly flexible cost-effective solution many smart card applications. Additional security features include power frequency protection logic, logical scrambling program data addresses, Power Analysis countermeasures memory accesses controlled supervisor mode. block diagram AT90SC25672RCT(-USB) shown Figure hereafter.
Optional Controller Description
AT90SC25672RCT(-USB) optionally features V2.0 Full Speed controller which requires external crystal data transfer. interface consists Serial Interface Engine (SIE) Universal Function Interface (UFI). performs clock/data separation, NRZI encoding decoding, stuffing, generation checking serial-parallel data conversion. connects interface AVR. consists protocol engine provides five configurable data transfer endpoints, each with it's DPRAM memory area. data transfer type each endpoint configured software. table below indicates characteristics each endpoint:
Table Characteristics each endpoint.
Endpoint number Size (bytes) Available data transfer modes BULK, ISOCHRONOUS, INTERRUPT, CONTROL BULK, ISOCHRONOUS, INTERRUPT BULK, ISOCHRONOUS, INTERRUPT BULK, ISOCHRONOUS, INTERRUPT, CONTROL BULK, ISOCHRONOUS, INTERRUPT, CONTROL
controller allows fast communication rate between DPRAM. controller provides dynamic pull-up attachment detachment host detection mechanism. addition, offers automatic interface detection between ISO7816 port.
AT90SC25672RCT (-USB)
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AT90SC25672RCT (-USB)
Figure AT90SC25672RCT(-USB) secureAVR Enhanced RISC Architecture.
EEPROM User Memory Crypto Program Memory Instruction Register Instruction Decoder Control Lines Status Register General Purpose Registers Access Control
Data 8-bit (USB (USB (USB-Xin) (USB-Xout) Secure Control Advx Crypto Accel.
(Optional controller)
Vbus
Data Memory Interrupt Unit 7816 Controller
Reset Circuit
Access Control
7816 Port DES/Triple
IN/OUT0
Checksum Accelerator On-Chip Security Timers
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6522AS-SMIC-05

Powerful Instructions (Most Executed Single Clock Cycle) Power Idle Po

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