General Description AS1152 Quad Flow-Through LVDS (Low-Voltage Di

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General Description AS1152 Quad Flow-Through LVDS (Low-Voltage Di

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General Description
AS1152 Quad Flow-Through LVDS (Low-Voltage Differential Signaling) Line Driver which accepts converts LVTTL/LVCMOS input levels into LVDS output signals. device perfect low-power lownoise applications requiring high signaling rates reduced emissions. device guaranteed transmit data speeds 500Mbps (250MHz) over controlled impedance media approximately 100. Supported transmission media traces, backplanes, cables. AS1152 capable setting four outputs high-impedance state through Enable Inputs internally pulled down GND), dropping device ultra-low-power state 16mW (typical) during high impedance. Enable Inputs common four drivers. Outputs conform ANSI TIA/EIA-644 LVDS standards. Flow-through pinout simplifies board layout reduces crosstalk separating LVTTL/LVCMOS inputs LVDS outputs. AS1152 operates from single +3.3V supply specified operation from +85°C.
Features
Flow-Through Pinout Guaranteed 500Mbps Data Rate (paired with AS1150) 350ps Pulse Skew (Max) Conforms ANSI TIA/EIA-644 LVDS Standards Single +3.3V Supply Operating Temperature Range: +85°C 16-Pin TSSOP Package
Applications
Digital Copiers, Laser Printers, Cellular Phone Base Stations, Add/Drop Muxes, Digital Cross-Connects, DSLAMs, Network Switches/Routers, Backplane Interconnect, Clock Distribution Computers, Intelligent Instruments, Controllers, Critical Microprocessors Microcontrollers, Power Monitoring, Portable/Battery-Powered Equipment.
Figure Block Diagram
OUT1+ OUT1-
OUT2+ OUT2-
OUT3+ OUT3-
OUT4+ OUT4-
AS1152
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AS1152 Data Sheet
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Absolute Maximum Ratings
Stresses beyond those listed Table cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Table Absolute Maximum Ratings Parameter INx, OUTx+, OUTx- Short Circuit Duration (OUTx+, OUTx-) Continuous Power Dissipation +70°C) Storage Temperature Range Maximum Junction Temperature Operating Temperature Range Limits -0.3 +5.0 -0.3 (VCC 0.3) -0.3 Continuous +150 +150
Units
Notes
Derate 9.4mW/°C Above +70°C
Package Body Temperature
reflow peak soldering temperature (body temperature) specified compliance with IPC/ JEDEC J-STD-020C "Moisture/ Reflow Sensitivity Classification Non-Hermetic Solid State Surface Mount Devices". Human Body Model, INx, OUTx+, OUTx-
Protection
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AS1152 Data Sheet
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Electrical Characteristics
Electrical Characteristics
Electrical Characteristics
(VCC +3.0 +3.6V, +85°C 100, 150Mhz Typical values +3.3V, +25°C, Unless Otherwise Noted.)1, Table Electrical Characteristics Parameter LVDS Output (OUtx+, OUTx-) Differential Output Voltage
Change Magnitude Between Complementary Output States
Symbol
Conditions
Unit
Figure page Figure page Figure page Figure page
1.375
Offset Voltage
Change Magnitude Between Complementary Output States
1.125
1.25
IOSD IOFF
Output High Voltage Output Voltage Differential Output Short-Circuit Current Output Short-Circuit Current Output High-Impedance Current Power-Off Output Current Inputs (INx, ENn) High-Level Input Voltage Low-Level Input Voltage Input Current Supply Current No-Load Supply Current Loaded Supply Current Disabled Supply Current Notes:
0.90
Enabled, OUTx+ OUTx- enabled high, OUTx+ VCC, OUTx- VCC, open, OUTx+ 3.6V, OUTx- 3.6V,
-3.8
INx, channels 100, channels Disabled, channels,
ICCL ICCZ
Maximum minimum limits over temperature guaranteed design characterization. Devices 100% tested +25°C. Currents into device positive, current device negative. voltages referenced ground except VOD. Guaranteed correlation data.
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AS1152 Data Sheet
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Switching Characteristics
Switching Characteristics
(VCC +3.0 +3.6V, ±1%, 150MHz, +85°C Typical values +3.3V, Unless Otherwise Noted.)
Table Switching Characteristics Parameter Differential Propagation Delay, High-to-Low Differential Propagation Delay, Low-to-High Differential Pulse Skew Differential Channel-to-Channel Skew Differential Part-to-Part Skew Differential Part-to-Part Skew Rise Time Fall Time Disable Time, High-to-Z Disable Time, Low-to-Z Enable Time, Z-to-High Enable Time, Z-to-Low Maximum Operating Frequency Notes: Parameters guaranteed design characterization. includes probe capacitance. Signal generator conditions dynamic tests: 100MHz, duty cycle, 1ns, 100%). tSKD1 magnitude difference differential propagation delay. tSKD1 |tPHLD tPLHD|. tSKD2 magnitude difference tPHLD tPLHD channel tPHLD tPLHD another channel same device. tSKD3 magnitude difference differential propagation delays between devices same within each other. tSKD4 magnitude difference differential propagation delays between devices operating over rated supply temperature ranges. fMAX signal generator conditions: duty cycle, 1ns, 100%). Conforms ANSI TIA/EIA LVDS Standards 150MHz. Maximum operating frequency 250MHz possible using AS1150 receiver. Symbol tPHLD tPLHD tSKD1 tSKD2 tSKD3 tSKD4 tTLH tTHL tPHZ tPLZ tPZH tPZL fMAX Conditions Figure page Figure page Figure page Figure page Figure page Figure page Figure page Figure page Figure page Figure page Figure page Figure page Figure page Figure page Figure page Figure page Figure page Figure page Figure page Figure page Figure page Figure page Figure page Figure page 0.04 0.07 0.13 0.43 0.39 0.39 0.35 0.60 Unit
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Switching Characteristics
Typical Operating Characteristics
+3.3V, +1.2V, |VID| 0.2V, CLOAD 15pF, Tamb unless otherwise noted Figure Output High Voltage
1.41
Figure Output Voltage
1.08
Output High Voltage
1.408
VOUT+
Output Voltage
1.075
VOUT-
1.406
VOUT-
1.07
VOUT+
1.404
1.402
1.065
1.06
Power-Supply Voltage
Power-Supply Voltage
Figure Output Short-Circuit Current VCC;
3.700
Figure Output High-Impedance State Current VCC;
Output Short-Circuit Current (mA)
3.675 3.650 3.625 3.600 3.575 3.550 3.525 3.500
Output High-Z State Current (µA)
Power-Supply Voltage
Power-Supply Voltage
Figure Differential Output Voltage
Figure Differential Output Voltage Load Resistor
Differential Output Voltage (mV)
Differential Output Voltage
Power-Supply Voltage
Load Resistor (Ohm)
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Switching Characteristics
Figure Offset Voltage
1.244
Figure Power Supply Current Frequency;
Power-Supply Current (mA)
Offset Voltage
1.243 1.242
Channels
1.241
Channels
1.24
1000
Power-Supply Voltage
Frequency (MHz)
Figure VCC; Freq 1MHz
19.5
Figure Temperature; Freq 1MHz
Power-Supply Current (mA)
Power-Supply Current (mA)
19.25 18.75 18.5 18.25
Power-Supply Voltage
Temperature(°C)
Figure Differential Propagation Delay VCC; Freq 1MHz
Figure Differential Propagation Delay Temperature; Freq 1MHz
Diff. Propagation Delay (ns)
Diff. Propagation Delay (ns)
tPHLD
tPHLD
tPLHD
tPLHD
Power-Supply Voltage
Temperature (°C)
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Switching Characteristics
Figure Differential Skew VCC; Freq 1MHz
Figure Differential Skew Temperature; Freq 1MHz
Diff. Pulse Skew (ps)
Diff. Pulse Skew (ps)
Power Supply Voltage
Temperature (°C)
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Assignments
Pinout Packaging
Assignments
Figure AS1152 Assignments (Top View)
OUT1OUT1+ OUT2+ OUT2OUT3OUT3+ OUT4+ OUT4-
AS1152
TSSOP
Descriptions
Table AS1152 Descriptions Number Name OUT4OUT4+ OUT3+ OUT3OUT2OUT2+ OUT1+ OUT1Description Driver Enable Input. Internally pulled down GND. When high open, driver outputs active. other combinations ENn, outputs disabled high impedance. LVTTL/LVCMOS Driver Input LVTTL/LVCMOS Driver Input Power Supply Input. Bypass with 0.1µF 0.001µF ceramic capacitors. Ground LVTTL/LVCMOS Driver Input LVTTL/LVCMOS Driver Input Driver Enable Input. Internally pulled down GND. When high open, driver outputs active. other combinations ENn, outputs disabled high impedance. Inverting LVDS Driver Output Noninverting LVDS Driver Output Noninverting LVDS Driver Output Inverting LVDS Driver Output Inverting LVDS Driver Output Noninverting LVDS Driver Output Noninverting LVDS Driver Output Inverting LVDS Driver Output
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LVDS Interface
Detailed Description
LVDS Interface
LVDS interface standard signaling method intended point-to-point communication over controlled-impedance medium defined ANSI/TIA/EIA-644 IEEE 1596.3 standards. LVDS standard uses lower voltage swing than other common communication standards, achieving higher data rates with reduced power consumption while reducing emissions system susceptibility noise. AS1152 500Mbps quad differential LVDS driver that designed high-speed, point-to-point, low-power applications. This device accepts LVTTL/LVCMOS input levels translates them LVDS output signals. AS1152 generates 2.5mA 4.5mA output current using current-steering configuration. This current steering approach induces less ground bounce shoot-through current, enhancing noise margin system speed performance. driver outputs short-circuit current limited, enter high-impedance state when device powered disabled. current-steering architecture AS1152 requires resistive load terminate signal complete transmission loop. Because device switches current voltage, actual output voltage swing determined value termination resistor input LVDS receiver (AS1150, AS1151). Logic states determined direction current flow through termination resistor. With typical 3.7mA output current, AS1152 produces output voltage 370mV when driving load.
Note: AS1152 conform ANSI TIA/EIA LVDS Standards when operating 150MHz. Paired with AS1150 datarate increased 500Mbps. While operating faster then 150MHz, rise fall time, well setup hold time conform ANSI TIA/EIA LVDS Standards.
Termination
Because AS1152 current-steering device, output voltage will generated without termination resistor. termination resistors should match differential impedance transmission line. Output voltage levels depend upon value termination resistor. AS1152 optimized point-to-point interface with termination resistors receiver inputs. Termination resistance values range between and132, depending characteristic impedance transmission medium.
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Power-Supply Bypassing
Applications
Table Function Table Enable Pins Open Open INx+ Don't Care Input INxL Output OUTx
Other Combinations Enable Settings Figure Typical Application Circuit
LVDS Signals
LVTTL/LVCMOS Data Inputs
LVTTL/LVCMOS Data Outputs
AS1152
AS1151
Quad LVDS Receiver
Shielded Twisted Cable Microstrip Board Traces
Power-Supply Bypassing
bypass VCC, high-frequency surface-mount ceramic 0.1µF 0.001µF capacitors parallel close device possible, with smaller valued capacitor closest VCC.
Differential Traces
Input trace characteristics adversely affect performance AS1152.
controlled-impedance board traces match cable characteristic impedance. termination resistor also matched this characteristic impedance. Eliminate reflections ensure that noise couples common mode running differential traces near each other. Reduce skew using matched trace lengths. Tight skew control required minimize emissions proper data recovery devices. Route each channel's differential signals very close each other optimal cancellation their respective external magnetic fields. constant distance between differential traces avoid irregularities differential impedance. Avoid turns (use turns). Minimize number vias further prevent impedance irregularities.
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Cables Connectors
Supported transmission media include printed circuit board traces, backplanes, cables.
cables connectors with matched differential impedance (typically 100) minimize impedance mismatches. Balanced cables such twisted pair offer superior signal quality tend generate less magnetic field canceling effects. Balanced cables pick noise common mode, which rejected LVDS receiver. Avoid unbalanced cables such ribbon cable simple coaxial cable.
Board Layout
device should placed close interface connector possible minimize LVDS trace length.
Keep LVDS other digital signals separated from each other reduce crosstalk. four-layer board that provides separate power, ground, LVDS signals, input signals. Isolate input LVDS signals from each other output LVCMOS/LVTTL signals from each other prevent coupling. Separate input LVDS signals from output signals planes with power ground planes best results.
Figure Driver Propagation Delay Transition Time Waveforms
1.5V tPLHD OUTx0 Differential OUTx+
1.5V
tPHLD
VDIFF (VOUTx+) (VOUTx-)
tTLH
tTHL
Figure Driver Propagation Delay Transition Time Test Circuit
OUTx+
Generator
OUTx-
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Figure Driver Test Circuit
OUTx+
RL/2 RL/2
OUTx-
Figure Driver High Impedance Delay Waveforms
when Open 1.5V 1.5V
1.5V when tPHZ OUTx+ When OUTx- When 1.2V 1.2V OUTx+ When OUTx- When tPLZ tPZL tPZH 1.5V
Figure Driver High-Impedance Delay Test Circuit
OUTx+ RL/2 +1.2V RL/2 Generator OUTxENn AS1152
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Board Layout
Package Drawings Markings
Figure 16-pin TSSOP Package
Notes: dimensions millimeters; angles degrees. Dimensioning tolerancing ASME Y14.5M 1994. Dimension does include mold flash, protrusions, gate burrs. Mold flash, protrusions, gate burrs shall exceed 0.15mm side. Dimension does include interlead flash protrusion. Interlead flash protrusions shall exceed 0.25mm side. Dimension does include dambar protrusion. Allowable dambar protrusion shall 0.08mm total excess dimension maximum material condition. Dambar cannot located lower radius foot. Terminal numbers reference only. Datums determined datum plane Dimensions determined datum plane This dimension applies only variations with even number leads side. Cross section determined 0.10 0.25mm from leadtip.
Symbol
0.90 0.60 0.22 1.0REF 0.10 0.10 0.05 0.20 0.65BSC Variations 4.90 5.00 4.30 4.40 6.4BSC 0.65BSC
0.05 0.85 0.50 0.09 0.09 0.19 0.19 0.09 0.09
1.10 0.15 0.95 0.75 0.30 0.25 0.20 0.16
Notes 1,2,5 1,2,3,8 1,2,4,8 1,2,6
5.10 4.50
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Board Layout
Ordering Information
Part Number AS1152 AS1152-T Description Quad low-voltage differential signaling driver Quad low-voltage differential signaling driver Package Type 16-pin TSSOP 16-pin TSSOP Delivery Form Tube Tape Reel
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Board Layout
Copyrights
Copyright 1997-2005, austriamicrosystems Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered rights reserved. material herein reproduced, adapted, merged, translated, stored, used without prior written consent copyright owner. products companies mentioned trademarks registered trademarks their respective companies.
Disclaimer
Devices sold austriamicrosystems covered warranty patent indemnification provisions appearing Term Sale. austriamicrosystems makes warranty, express, statutory, implied, description regarding information forth herein regarding freedom described devices from patent infringement. austriamicrosystems reserves right change specifications prices time without notice. Therefore, prior designing this product into system, necessary check with austriamicrosystems current information. This product intended normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, high reliability applications, such military, medical life-support lifesustaining equipment specifically recommended without additional processing austriamicrosystems each application. information furnished here austriamicrosystems believed correct accurate. However, austriamicrosystems shall liable recipient third party damages, including limited personal injury, property damage, loss profits, loss use, interruption business indirect, special, incidental consequential damages, kind, connection with arising furnishing, performance technical data herein. obligation liability recipient third party shall arise flow austriamicrosystems rendering technical other services.
Contact Information
Headquarters austriamicrosystems A-8141 Schloss Premstaetten, Austria Tel: 3136 Fax: 3136 Sales Offices, Distributors Representatives, please visit:
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General Description AS1152 Quad Flow-Through LVDS (Low-Voltage Di

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