General Description AS1150 AS1151 quad flow-through LVDS (low-vol

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General Description AS1150 AS1151 quad flow-through LVDS (low-vol

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General Description
AS1150 AS1151 quad flow-through LVDS (low-voltage differential signaling) receivers which accept LVDS differential inputs convert them LVCMOS outputs. receivers perfect lowpower low-noise applications requiring high signaling rates reduced emissions. devices guaranteed receive data speeds 500Mbps (250MHz) over controlled impedance media approximately 100. Supported transmission media traces, backplanes, cables. AS1150 uses high impedance inputs requires external termination resistor when used point-topoint connection. AS1151 features integrated parallel termination resistors (nominally 107), which eliminate requirement discrete termination resistors, reduce stub lengths. integrated failsafe feature sets output high inputs open, undriven terminated, undriven shorted. Enable inputs internally pulled down GND) control high-impedance output common four receivers. inputs conform ANSI TIA/EIA- LVDS standards. Flow-through pinout simplifies board layout reduces crosstalk separating LVDS inputs LVCMOS outputs. devices available 16-pin TSSOP package. Figure Block Diagrams
Features
Flow-Through Pinout Guaranteed 500Mbps Data Rate 300ps Pulse Skew (Max) Conform ANSI TIA/EIA-644 LVDS Standards Single +3.3V Supply Operating Temperature Range: Failsafe Circuit Integrated Termination (AS1151) 16-pin TSSOP Package
Applications
devices ideal digital copiers, laser printers, cellular phone base stations, add/drop muxes, digital cross-connects, dslams, network switches/routers, backplane interconnect, clock distribution computers, intelligent instruments, controllers, critical microprocessors microcontrollers, power monitoring, portable/battery-powered equipment.
IN1+ IN1-
IN1+ OUT1 IN1-
OUT1
IN2+ IN2-
IN2+ OUT2 IN2-
OUT2
IN3+ IN3-
IN3+ OUT3 IN3-
OUT3
IN4+ IN4EN
IN4+ OUT4 IN4EN
OUT4
AS1150
AS1151
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Absolute Maximum Ratings
Stresses beyond those listed Table cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated Section Electrical Characteristics page implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Table Absolute Maximum Ratings Parameter INx+, INx- OUTx Continuous Power Dissipation (TAMB Storage Temperature Range Maximum Junction Temperature Operating Temperature Range Protection -0.3 -0.3 -0.3 -0.3 +5.0 +5.0 +150 +150 Units Human Body Model, INx+, INxThe reflow peak soldering temperature (body temperature) specified compliance with IPC/JEDEC J-STD-020C "Moisture/ Reflow Sensitivity Classification Non-Hermetic Solid State Surface Mount Devices". Derate 9.4mW/°C Above +70°C Notes
Package Body Temperature
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Electrical Characteristics
Electrical Characteristics
Electrical Characteristics
+3.0 +3.6V, Differential Input Voltage |VID| 1.0V, Common-Mode Voltage |VID/2| 2.4V |VID/2|,TAMB Typical values +3.3V, TAMB (unless otherwise specified). Table Electrical Characteristics Parameter LVDS Inputs (INx+, INx-) Differential Input High Threshold Differential Input Threshold Input Current (AS1150) Power-Off Input Current (AS1150) Input Resistor (AS1150) Input Resistor (AS1150) Common Mode Input Resistance Differential Input Resistance IINx+, IINxIINOFF RIN1 RIN2 RINCM RDIFF 0.1V |VID| 0.6V 0.6V |VID| 1.0V 0.1V |VID| 0.6V, 0.6V |VID| 1.0V, 3.6V Figure page 3.6V Figure page AS1151: Input AS1151: 3.6V Figure page Open, undriven short, undriven parallel termination +100mV -4.0mA (AS1151) Output Voltage Output Short-Circuit Current Output High-Impedance Current Logic Inputs (EN, ENn) Input High Voltage Input Voltage Input Current Supply Supply Current Disabled Supply Current Notes: Current into defined positive. Current defined negative. voltages referenced ground except VTH, VTL, VID. Short only output time. exceed absolute maximum junction temperature specification. ICCZ Enabled, Inputs Open average value, |VID| 200mV Disabled, Inputs Open VINx
Symbol
Conditions
Unit
-100
LVCMOS/LVTTL Outputs (OUTx) -4.0mA (AS1150) 0.25
Output High Voltage (Table
Open Undriven Short +100mV
+4.0mA, -100mV Enabled, 0.1V, VOUTx Disabled, VOUTx
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Electrical Characteristics
Electrical Characteristics
+3.0 +3.6V, CLOAD 15pF, Differential Input Voltage |VID| 1.0V, Common-Mode Voltage |VID/2| 2.4V -|VID/2|, Input Rise Fall Time 80%), Input Frequency 100MHz, TAMB Typical values +3.3V, 1.2V, |VID| 0.2V, TAMB (unless otherwise specified). Table Electrical Characteristics Parameter Differential Propagation Delay Highto-Low Differential Propagation Delay Lowto-High
Differential Pulse Skew (tPHLD tPLHD)
Symbol tPHLD tPLHD tSKD1 tSKD2 tSKD3 tSKD4 tTLH tTHL tPHZ tPLZ tPZH tPZL
Conditions Figure page Figure page Figure page Figure page Figure page Figure page
Figure page Figure
Unit
Differential Channel-to-Channel Skew Differential Part-to-Part Skew Differential Part-to-Part Skew Rise Time Fall Time Disable Time High-to-Z Disable Time Low-to-Z Enable Time Z-to-High Enable Time Z-to-Low Maximum Operating Frequency Notes:
page Figure page Figure page Figure page Figure page Figure page Figure page Figure page Figure page RLOAD Figure page Figure page RLOAD Figure page Figure page RLOAD Figure page Figure page RLOAD Figure page Figure page Channels Switching
fMAX
parameters guaranteed design characterization. includes scope probe test capacitance. tSKD1 magnitude difference differential propagation delays channel. tSKD1 |tPHLD tPLHD|. tSKD2 magnitude difference tPLHD tPHLD channel tPLHD tPHLD other channel same device. tSKD3 magnitude difference differential propagation delays between devices operating over rated conditions same within each other. tSKD4 magnitude difference differential propagation delays between devices operating over rated conditions. fMAX generator output conditions: Rise time fall time 100%) duty cycle +1.3V +1.1V Output criteria: Duty cycle 0.4V (max) 2.7V (min) Load 15pF
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Electrical Characteristics
Typical Operating Characteristics
+3.3V, +1.2V, |VID| 0.2V, CLOAD 15pF, TAMB unless otherwise noted. Figure Supply Current Frequency
Figure Supply Current Temperature
Channels Switching
Supply Current (mA)
Supply Current (mA)
Outputs
0,01
Channel Switching
Outputs High
1000
Frequency (MHz)
perature (°C)
Figure Diff. Threshold Voltage
Figure Output Short-Circuit Current
Diff. Threshold Voltage (mV)
High
High
Output Short-Circuit Current (mA)
Supply Voltage
Supply Voltage
Figure Output Voltage
Figure Output High Voltage
Output Voltage (mV)
Output High Voltage
Supply Voltage
Supply Voltage
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Electrical Characteristics
Figure Differential Propagation Delay
Figure Differential Propagation Delay Temperature
2,25
Diff. Propagation Delay (ns)
Diff. Propagation Delay (ns)
2,16 2,12
tPHLD
2,15
tPLHD
2,08
tPLHD
tPHLD
2,04
2,05
Supply Voltage
perature (°C)
Figure Differential Propagation Delay
Figure Differential Propagation Delay
Diff. Propagation Delay (ns)
tPHLD
Diff. Propagation Delay (ns)
tPHLD
tPLHD
tPLHD
-0,5
Common-Mode Voltage
Figure Differential Pulse Skew
Differential Input Voltage
Figure Transition Time
Diff. Pulse Skew (ps)
Transition Time (ps)
tTLH
tTHL
Supply Voltage
Supply Voltage
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Electrical Characteristics
Figure Transition Time Temperature
Transition Time (ps)
tTLH
tTHL
perature (°C)
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Assignments
Pinout
Assignments
Figure Assignments (Top View)
IN1IN1+ IN2+ IN2IN3IN3+ IN4+ IN4-
OUT1 OUT2
AS1150 AS1151
OUT3 OUT4
Descriptions
Table Descriptions Number Name IN1IN1+ IN2+ IN2IN3IN3+ IN4+ IN4ENn OUT4 OUT3 OUT2 OUT1 Description Inverting Differential Receiver Input Noninverting Differential Receiver Input Noninverting Differential Receiver Input Inverting Differential Receiver Input Inverting Differential Receiver Input Noninverting Differential Receiver Input Noninverting Differential Receiver Input Inverting Differential Receiver Input Receiver Enable Input. Internally pulled down GND. When high open, receiver outputs active. other combinations ENn, outputs disabled high impedance. LVCMOS/LVTTL Receiver Output LVCMOS/LVTTL Receiver Output Ground Power-Supply Input. Bypass with 0.1µF 0.001µF ceramic capacitors. LVCMOS/LVTTL Receiver Output LVCMOS/LVTTL Receiver Output Receiver Enable Input. Internally pulled down GND. When high open, receiver outputs active. other combinations ENn, outputs disabled high impedance.
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LVDS Interface
Detailed Description
AS1150 AS1151 500Mbps, four-channel LVDS receivers intended high-speed, point-to-point, lowpower applications. Each independent channel accepts converts LVDS input LVTTL/LVCMOS output. devices capable detecting differential signals from 100mV within input voltage range 2.4V. 450mV differential output LVDS driver nominally centered around 1.25V. receiver input voltage range, voltage shift signal relative receiver allowed. Thus, difference ground references transmitter receiver, well common mode effect coupled noise, tolerated.
LVDS Interface
LVDS Interface Standard signaling method defined point-to-point communication over controlled-impedance medium defined ANSI TIA/EIA-644 IEEE 1596.3 standards. LVDS standard uses lower voltage swing than other common communication standards, resulting higher data rates, reduced power consumption emissions, less susceptibility noise. devices fully comply with LVDS standard input voltage range +2.4V referenced receiver ground. AS1151 integrated termination resistors connected internally across each receiver input. This internal termination saves board space, eases layout, reduces stub length compared external termination resistor. other words, transmission line terminated
Failsafe Circuit
devices contain integrated failsafe circuit prevent noise inputs that open, undriven terminated, undriven shorted. Open undriven terminated input conditions occur there cable failure when LVDS driver outputs high impedance. short condition also occur because cable failure. failsafe circuit AS1150/AS1151 automatically sets output high these conditions true. failsafe input circuit (see Figure samples input common-mode voltage compares 0.3V (nominal). input driven levels specified LVDS standards, input common-mode voltage less than 0.3V failsafe circuit activated. inputs open, undriven shorted, undriven parallel terminated, there input current. this case, pullup resistor failsafe circuit pulls both inputs above 0.3V, activating failsafe circuit thus forcing device output high. Figure Failsafe Input Circuit
RIN2
RIN2
0.3V INx+ RIN1 OUTx RIN1 INx+ RIN1 RDIFF RIN1
0.3V
OUTx
INx-
INx-
AS1150
AS1151
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Applications
Table Function Table Enable Pins INx+ +100mV +100mV Open AS1150 Open, undriven short, undriven parallel termination AS1151 Open undriven short Other Combinations Enable Settings Figure Typical Application Circuit
LVDS Signals
Input INx-
Output OUTx
Don't Care
LVTTL/LVCMOS Data Inputs
LVTTL/LVCMOS Data Outputs
AS1152 Quad LVDS Driver
AS1151
Shielded Twisted Cable Microstrip Board Traces
Power-Supply Bypassing
bypass VCC, high-frequency surface-mount ceramic 0.1µF 0.001µF capacitors parallel close device possible, with smaller valued capacitor closest VCC.
Differential Traces
Input trace characteristics adversely affect performance AS1150 AS1151.
controlled-impedance board traces match cable characteristic impedance. termination resistor must also matched this characteristic impedance. Eliminate reflections ensure that noise couples common mode running differential traces close together. Reduce skew using matched trace lengths. Tight skew control required minimize emissions proper data recovery devices. Route each channel's differential signals very close each other optimal cancellation their respective external magnetic fields. constant distance between differential traces avoid irregularities differential impedance. Avoid turns (use turns). Minimize number vias further prevent impedance irregularities.
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Cables Connectors
Supported transmission media include printed circuit board traces, backplanes, cables.
cables connectors with matched differential impedance (typically 100) minimize impedance mismatches. Balanced cables such twisted pair offer superior signal quality tend generate less magnetic field canceling effects. Balanced cables pick noise common mode, which rejected LVDS receiver. Avoid unbalanced cables such ribbon cable simple coaxial cable.
Termination
high data rates LVDS drivers, matched termination will prevent generation signal reflections, reduce EMI.
AS1151 integrated termination resistors connected across inputs each receiver. value integrated resistor specified Table page AS1150 requires external termination resistor. termination resistor should match differential impedance transmission line placed close receiver inputs possible. Termination resistance values range between depending characteristic impedance transmission medium. surface-mount resistors.
Board Layout
device should placed close interface connector possible minimize LVDS trace length.
Keep LVDS other digital signals separated from each other reduce crosstalk. four-layer board that provides separate power, ground, LVDS signals, input signals. Isolate input LVDS signals from each other output LVCMOS/LVTTL signals from each other prevent coupling. Separate input LVDS signals from output signals planes with power ground planes best results.
Figure Propagation Delay Transition Time Test Circuit
INx+ Pulse Generator** INx50
Receiver Enabled AS1150, AS1151
required pulse generator. When testing AS1151, adjust pulse generator output account internal termination resistor.
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Figure Propagation Delay Transition Time Waveforms
INxVID INx+ tPLHD tPHLD (VINx+) (VINx-) Note: (VIN- VIN+)
OUTx tTLH
tTHL
Figure High Impedance Delay Test Circuit
INx+ Generator INx-
Device Under Test OUTx
includes load test capacitance. tPZL tPLZ measurements. tPZH tPHZ measurements.
Figure High Impedance Delay Waveforms
when Open 1.5V 1.5V
1.5V when tPZL tPLZ Output when -100mV Output when +100mV 0.5V tPHZ 0.5V tPZH 1.5V
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Board Layout
Package Drawings Markings
Figure 16-Pin TSSOP Package
Symbol Notes:
0.65mm Lead Pitch 1.10 0.05 0.15 0.85 0.90 0.95 0.50 0.60 0.75 0.09 0.09 0.19 0.30 0.19 0.22 0.25 0.09 0.20 0.09 0.16 4.90 4.30 5.00 4.40 5.10 4.50
Note
Symbol
0.65mm Lead Pitch 0.10 0.10 0.05 0.20 0.65
Note
Variations
0.65
dimensions millimeters; angles degrees. Dimensions tolerancing ASME Y14.5M-1994. Dimension does include mold flash, protrusions, gate burrs. Mold flash, protrusions, gate burrs shall exceed 0.15mm side. Dimension does include interlead flash protrusion. Interlead flash protrusion shall exceed 0.25mm side. Dimension does include dambar protrusion. Allowable dambar protrusion shall 0.08mm total excess dimension maximum material condition. Dambar cannot located lower radius foot. Minimum space between protrusion adjacent lead 0.07mm 0.5mm pitch packages. Terminal numbers shown reference only. Datums determined datum plane Dimensions determined datum plane This dimension applies only variations with even number leads side. variations with number leads package, center lead must coincident with package centerline, datum Cross section determined 0.10 0.25mm from leadtip.
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Board Layout
Ordering Information
Model AS1150 AS1150-T AS1151 AS1151-T Description Quad low-voltage differential signaling receiver Quad low-voltage differential signaling receiver Quad low-voltage differential signaling receiver with integrated termination Quad low-voltage differential signaling receiver with integrated termination Package Type 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP Delivery Form Tubes Tape Reel Tubes Tape Reel
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Board Layout
Copyrights
Copyright 1997-2006, austriamicrosystems Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered rights reserved. material herein reproduced, adapted, merged, translated, stored, used without prior written consent copyright owner. products companies mentioned trademarks registered trademarks their respective companies.
Disclaimer
Devices sold austriamicrosystems covered warranty patent indemnification provisions appearing Term Sale. austriamicrosystems makes warranty, express, statutory, implied, description regarding information forth herein regarding freedom described devices from patent infringement. austriamicrosystems reserves right change specifications prices time without notice. Therefore, prior designing this product into system, necessary check with austriamicrosystems current information. This product intended normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, high reliability applications, such military, medical life-support lifesustaining equipment specifically recommended without additional processing austriamicrosystems each application. shipments less than parts manufacturing flow might show deviations from standard production flow, such test flow test location. information furnished here austriamicrosystems believed correct accurate. However, austriamicrosystems shall liable recipient third party damages, including limited personal injury, property damage, loss profits, loss use, interruption business indirect, special, incidental consequential damages, kind, connection with arising furnishing, performance technical data herein. obligation liability recipient third party shall arise flow austriamicrosystems rendering technical other services.
Contact Information
Headquarters austriamicrosystems A-8141 Schloss Premstaetten, Austria Tel: 3136 Fax: 3136 Sales Offices, Distributors Representatives, please visit:
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General Description AS1150 AS1151 quad flow-through LVDS (low-vol

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