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1 General Description

2 Key Features

1 General Description
The AS1150 and AS1151 are quad flow-through LVDS (low-voltage differential signaling) receivers which accept LVDS differential inputs and convert them to LVCMOS outputs. The receivers are perfect for lowpower low-noise applications requiring high signaling rates and reduced EMI emissions. The devices are guaranteed to receive data at speeds up to 500Mbps (250MHz) over controlled impedance media of approximately 100. Supported transmission media are PCB traces, backplanes, and cables. The AS1150 uses high impedance inputs and requires an external termination resistor when used in a point-topoint connection. The AS1151 features integrated parallel termination resistors (nominally 107), which eliminate the requirement for discrete termination resistors, and reduce stub lengths. The integrated failsafe feature sets the output high if the inputs are open, undriven and terminated, or undriven and shorted. Enable inputs (EN and ENn - internally pulled down to GND) control the high-impedance output and are common to all four receivers. All inputs conform to the ANSI TIA / EIA- 644 LVDS standards. Flow-through pinout simplifies PC board layout and reduces crosstalk by separating the LVDS inputs and LVCMOS outputs. The devices are available in a 16-pin TSSOP package. Figure 1. Block Diagrams
2 Key Features
3 Applications
The devices are ideal for digital copiers, laser printers, cellular phone base stations, add / drop muxes, digital cross-connects, dslams, network switches / routers, backplane interconnect, clock distribution computers, intelligent instruments, controllers, critical microprocessors and microcontrollers, power monitoring, and portable / battery-powered equipment.
IN1+ IN1-
IN1+ OUT1 IN1-
IN2+ IN2-
IN2+ OUT2 IN2-
IN3+ IN3-
IN3+ OUT3 IN3-
IN4+ IN4EN
IN4+ OUT4 IN4EN
AS1150
AS1151
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AS1150, AS1151 Data Sheet
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4 Absolute Maximum Ratings
Package Body Temperature
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DC Electrical Characteristics
5 Electrical Characteristics
DC Electrical Characteristics
Symbol
Conditions
Output High Voltage (Table 5)
VOL IOS IOZ
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AC Electrical Characteristics
Differential Pulse Skew (tPHLD - tPLHD)
Symbol tPHLD tPLHD tSKD1 tSKD2 tSKD3 tSKD4 tTLH tTHL tPHZ tPLZ tPZH tPZL
Conditions Figure 18 on page 11 and Figure 19 on page 12 Figure 18 on page 11 and Figure 19 on page 12 Figure 18 on page 11 and Figure 19 on page 12
Figure 18 on page 11 and Figure 19 on
Min 1.6 1.6
Typ 2.0 2.0 140
Max 3.1 3.1 300 400 0.8 1.5
Unit ns ns ps ps ns ns ns ns ns ns ns ns MHz
Differential Channel-to-Channel 4 Skew Differential Part-to-Part Skew Differential Part-to-Part Skew Rise Time Fall Time Disable Time High-to-Z Disable Time Low-to-Z Enable Time Z-to-High Enable Time Z-to-Low Maximum Operating Frequency Notes: 1. 2. 3. 4. 5. 6. 7.
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AC Electrical Characteristics
6 Typical Operating Characteristics
Figure 3. Supply Current vs. Temperature
All Channels Switching
Supply Current (mA)
Outputs Low
One Channel Switching
Outputs High
Frequency (MHz)
Tem perature (°C)
Figure 4. Diff. Threshold Voltage vs. VCC
Figure 5. Output Short-Circuit Current vs. VCC
Diff. Threshold Voltage (mV)
High to Low
Low to High
Output Short-Circuit Current (mA) .
Supply Voltage (V)
Figure 6. Output Low Voltage vs. VCC
Figure 7. Output High Voltage vs. VCC
Output Low Voltage (mV)
Output High Voltage (V) .
Supply Voltage (V)
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AC Electrical Characteristics
Figure 8. Differential Propagation Delay vs. VCC
Figure 9. Differential Propagation Delay vs. Temperature
Diff. Propagation Delay (ns)
tPHLD
tPLHD
tPHLD
Supply Voltage (V)
Tem perature (°C)
Figure 10. Differential Propagation Delay vs. VCM
Figure 11. Differential Propagation Delay vs. VID
Diff. Propagation Delay (ns)
tPHLD
Diff. Propagation Delay (ns)
tPHLD
tPLHD
Common-Mode Voltage (V)
Figure 12. Differential Pulse Skew vs. VCC
Differential Input Voltage (V)
Figure 13. Transition Time vs. VCC
Diff. Pulse Skew (ps)
Transition Time (ps)
Supply Voltage (V)
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AC Electrical Characteristics
Figure 14. Transition Time vs. Temperature
Transition Time (ps)
Tem perature (°C)
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Pin Assignments
7 Pinout
Pin Assignments
Figure 15. Pin Assignments (Top View)
IN1IN1+ IN2+ IN2IN3IN3+ IN4+ IN4-
16 EN 15 OUT1 14 OUT2
AS1150 AS1151
13 VCC 12 GND 11 OUT3 10 OUT4 9 ENn
Pin Descriptions
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LVDS Interface
8 Detailed Description
LVDS Interface
The LVDS Interface Standard is a signaling method defined for point-to-point communication over a controlled-impedance medium as defined by the ANSI TIA / EIA-644 and IEEE 1596.3 standards. The LVDS standard uses a lower voltage swing than other common communication standards, resulting in higher data rates, reduced power consumption and EMI emissions, and less susceptibility to noise. The devices fully comply with the LVDS standard input voltage range of 0 to +2.4V referenced to receiver ground. The AS1151 has an integrated termination resistors connected internally across each receiver input. This internal termination saves board space, eases layout, and reduces stub length compared to an external termination resistor. In other words, the transmission line is terminated on the IC.
Failsafe Circuit
The devices contain an integrated failsafe circuit to prevent noise at inputs that are open, undriven and terminated, or undriven and shorted. Open or undriven terminated input conditions can occur if there is a cable failure or when the LVDS driver outputs are high impedance. A short condition also can occur because of a cable failure. The failsafe circuit of the AS1150 / AS1151 automatically sets the output high if any of these conditions are true. The failsafe input circuit (see Figure 16) samples the input common-mode voltage and compares it to VCC - 0.3V (nominal). If the input is driven to levels specified in the LVDS standards, the input common-mode voltage is less than VCC 0.3V and the failsafe circuit is not activated. If the inputs are open, undriven and shorted, or undriven and parallel terminated, there is no input current. In this case, a pullup resistor in the failsafe circuit pulls both inputs above VCC - 0.3V, activating the failsafe circuit and thus forcing the device output high. Figure 16. Failsafe Input Circuit
VCC VCC
VCC - 0.3V INx+ RIN1 OUTx RIN1 INx+ RIN1 RDIFF RIN1
VCC - 0.3V
AS1150
AS1151
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AS1150, AS1151 Data Sheet
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9 Applications
Table 5. Function Table Enable Pins EN ENn INx+ VID +100mV VID +100mV H L or Open AS1150 - Open, undriven short, or undriven 100 parallel termination AS1151 - Open or undriven short Other Combinations of Enable Pin Settings Figure 17. Typical Application Circuit
LVDS Signals Tx 107 Rx
Input INx-
Output OUTx H L H Z
Tx LVTTL / LVCMOS Data Inputs
Rx LVTTL / LVCMOS Data Outputs
AS1152 Quad LVDS Driver
AS1151
100 Shielded Twisted Cable or Microstrip PC Board Traces
Power-Supply Bypassing
To bypass VCC, use high-frequency surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to pin VCC.
Differential Traces
Input trace characteristics can adversely affect the performance of the AS1150 and AS1151.
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Cables and Connectors
Supported transmission media include printed circuit board traces, backplanes, and cables.
Use cables and connectors with matched differential impedance (typically 100) to minimize impedance mismatches. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver. Avoid the use of unbalanced cables such as ribbon cable or simple coaxial cable.
Termination
Due to the high data rates of LVDS drivers, matched termination will prevent the generation of any signal reflections, and reduce EMI.
Board Layout
The device should be placed as close to the interface connector as possible to minimize LVDS trace length.
Keep the LVDS and any other digital signals separated from each other to reduce crosstalk. Use a four-layer PC board that provides separate power, ground, LVDS signals, and input signals. Isolate the input LVDS signals from each other and the output LVCMOS / LVTTL signals from each other to prevent coupling. Separate the input LVDS signals from the output signals planes with the power and ground planes for best results.
Figure 18. Propagation Delay and Transition Time Test Circuit
INx+ Pulse Generator INx50 50 CL OUT
Receiver Enabled 1 / 4 AS1150, AS1151
50 required for pulse generator. When testing the AS1151, adjust the pulse generator output to account for internal termination resistor.
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Figure 19. Propagation Delay and Transition Time Waveforms
Figure 20. High Impedance Delay Test Circuit
VCC S1
INx+ Generator 50 EN ENn INx-
RL Device Under Test OUTx CL
Figure 21. High Impedance Delay Waveforms
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Board Layout
10 Package Drawings and Markings
Figure 22. 16-Pin TSSOP Package
Symbol A A1 A2 L R R1 b b1 c c1 D E1 E Notes:
0.65mm Lead Pitch Min Nom Max 1.10 0.05 0.15 0.85 0.90 0.95 0.50 0.60 0.75 0.09 0.09 0.19 0.30 0.19 0.22 0.25 0.09 0.20 0.09 0.16 4.90 4.30 5.00 4.40 6.4 BSC 5.10 4.50
Symbol 1 L1 aaa bbb ccc ddd e 2 3
Variations 3, 8 e 4, 8 N
0.65 BSC 16
1. All dimensions are in millimeters angles in degrees. 2. Dimensions and tolerancing per ASME Y14.5M-1994. 3. Dimension D does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15mm per side. 4. Dimension E1 does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25mm per side. 5. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm total in excess of dimension b at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07mm for 0.5mm pitch packages. 6. Terminal numbers shown are for reference only. 7. Datums A and B to be determined at datum plane H. 8. Dimensions D and E1 to be determined at datum plane H. 9. This dimension applies only to variations with an even number of leads per side. For variations with an odd number of leads per package, the center lead must be coincident with the package centerline, datum A. 10. Cross section A-A to be determined at 0.10 to 0.25mm from the leadtip.
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11 Ordering Information
Model AS1150 AS1150-T AS1151 AS1151-T Description Quad low-voltage differential signaling receiver Quad low-voltage differential signaling receiver Quad low-voltage differential signaling receiver with integrated termination Quad low-voltage differential signaling receiver with integrated termination Package Type 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP Delivery Form Tubes Tape and Reel Tubes Tape and Reel
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Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services.
Contact Information
Headquarters austriamicrosystems AG A-8141 Schloss Premstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com
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