AKD4702 Evaluation board Rev.A AK4702 GENERAL DESCRIPTION AK

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AKD4702 Evaluation board Rev.A AK4702 GENERAL DESCRIPTION AK

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[AKD4702]
AKD4702
Evaluation board Rev.A AK4702
GENERAL DESCRIPTION AKD4702 evaluation board quickly evaluating AK4702 with SCART switch. Evaluation requires audio/video analog analyzer, analog video signal source, digital audio signal source, power supply. AKM's evaluation board also used audio source. Also included AK4112B digital audio interface receiver which receives SPDIF compatible audio data. digital audio data available optical connector BNC.
AKD4702 -Evaluation board AK4702 (Cable connecting with printer port IBM-AT compatible control software enclosed with board.)
FUNCTION connectors analog audio input/output connectors analog video input/output On-board clock generator connector external clock input Compatible with types digital interface Serial interface: Direct interface with evaluation boards AKM's converter evaluation boards. S/PDIF: On-board AK4112BVF that accepts optical input input 10pin header serial control interface
VVD2 VVD1
JP10
Reg.
+12V
PORT3 P-IF Control Data 10pin Heder Port1
DATA DATA 10pin Header
JP11
(Digital)
TVOUTR VCROUTR TVINL VCRINL VCRSB VCRB TVSB VCRINR TVINR MONOIN VCROUTL
JP2~
PORT2
Clock Generator
AK4702
VCRVOUT
TVFB
JP12
VCRC
TVRC
TVVOUT
ENCB
ENCRC
ENCV
TVVIN
VCRFB
VCRG
ENCG
ENCC
ENCY
VCRVIN
VCRRC
Figure AKD4702 Block Diagram Circuit diagram layout attached this manual.
<KM067304>
TVOUTL
MONOOUT
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[AKD4702]
Operation sequence
power supply lines. (Note [+12V] [+5V] [D5V] [VVD1] [VVD2] [AGND] [DGND] [VVSS2] (Orange) (Red) (Red) (Red) (Blue) (Black) (Black) (Black) +11.4 +12.6V +4.75 +5.25V (Note +4.75 +5.25V (Note +4.75 VVD2 (Note VDD1 +5.25V (Note
Note: Each supply line should distributed from power supply unit. (REG) should open when "+5V" jack used. (D-A) should open when "D5V" jack used. JP10 (VDD1) JP11 (VDD2) should open when "VDD1" jack "VDD2" jack used respectively. Set-up evaluation modes, jumper pins DIP-switches. (Refer following sections.) Connect PORT3 (=µP-I/F) with enclosed 10-wire flat cable. execute enclosed control software. (See "CONTROL SOFTWARE MANUAL".) Turn power Reset AK4702 once bringing (PDN) "L", turn "H".
<KM067304>
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[AKD4702]
Evaluation mode S/PDIF mode (Optical Link BNC: default)
When (DIP-switch S1_1 board) "L", AK4112B (DIR) generates MCLK, BICK, LRCK SDATA from received bitstream through PORT2 (TORX176: optical link) (BNC). This mode used evaluation using test disk. PORT1 (EXT) should open. 1)-1. DIP-switch set-up DIF1 DIF0 Audio Data Format AK4112B 16bit justified 18bit justified justified Notes
Table DIP-switch set-up Please match data format AK4702 C-bus control following notes. Note 16bit justified DIP-switch follows.
AK4112B
(Reserved) (Reserved) (Reserved) (Reserved)
control registers DIF1/0 AK4702 enclosed software follows.
Note 18bit justified DIP-switch follows.
control registers DIF1/0 AK4702 enclosed software follows.
<KM067304>
DIF2 DIF0
DIF2 DIF0
AK4112B
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[AKD4702]
Note justified DIP-switch follows.
AK4112B
(Reserved) (Reserved) (Reserved) (Reserved)
control registers DIF1/0 AK4702 enclosed software follows.
Note DIP-switch follows.
control registers DIF1/0 AK4702 enclosed software follows.
<KM067304>
DIF2 DIF0
DIF2 DIF0
AK4112B
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[AKD4702]
1)-2. Jumper pins
MCLK
BICK
SDTI
LRCK
selects input port bitstream form Port2 (TOTX176) (BNC RX).
TORX
TORX
Using TORX
Using
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[AKD4702]
On-board X'tal mode/ Feeding external MCLK
When (DIP-switch S1_1 board) "H", AK4112B generates MCLK, BICK LRCK from on-board X'tal external clock form SDATA should PORT1. 2)-1. DIP-switch set-up DIF1 Don't care DIF0 Don't care
Table DIP-switch set-up
2)-2. Jumper pins
2)-2-a. Using on-board X'tal
MCLK BICK SDTI LRCK
JP6: Don't care. 2)-2-b. Using external clock connector MCLK BICK SDTI LRCK
JP6: Don't care. Remove on-board X'tal.
<KM067304>
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[AKD4702]
Feeding clocks from external
Under following set-up, external signals AK4702 through POTR1 (EXT). AKM's evaluation board used. 3)-1. DIP-switch set-up Don't care DIF1 Don't care DIF0 Don't care
Table DIP-switch set-up 3)-2. Jumper pins MCLK BICK SDTI LRCK
JP6: Don't care.
Other jumper pins
[JP12](VCRRC): Input Jack selection VCRRC AK4702 When VCRC AK4702 outputs setting "1", signal through (VCRCOUT) VCRRC pin. "I": signal through J18(VCRRC) VCRRC pin. (Default) "I/O": signal through J27(VCRCOUT) VCRRC pin. AK4702 should "1".
[JP7](GND): Analog ground digital ground Open: separated. (Default) Short: connected. (The jack "DGND" open.)
DGND AGND
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[AKD4702]
DIP-switch (S1) List
Switch Name DIF0 DIF2 Default Function Refer Evaluation mode"
(Reserved) (Reserved) Table DIP-switch list
Jumper List 2,3, Jumper Name MCLK source set-up when CM0="H". MCLK, BICK, LRCK, SDTI
Short: X'tal (default). Open: External clock (J1). Remove on-board X'tal.
Function
Clock source set-up
Short: Connect (AK4112B). (default) Open: Separate DIR. Supply clocks Port1.
S/PDIF's port set-up when CM0="L".
TORX: Optical connector PORT2. (default) BNC: connector
Analog ground digital ground
Open: separated (default). Short: connected (The connector "DGND" open.).
Power supply source set-up digital section AKD4702.
Open: from "D5V" Jack. (default) Short: from regulator "+5V" Jack. Don't connect anything "D5V" Jack.(default)
Power supply source set-up AK4702.
Open: from "+5V" Jack. Short: from regulator. Don't connect anything "+5V" Jack. (default)
Power supply source set-up VVD1 AK4702. VVD1
Open: from "VVD1" Jack. Short: from regulator "+5V" Jack. Don't connect anything "VVD1" Jack. (default)
Power supply source set-up VVD1 AK4702. VVD2
Open: from "VVD2" Jack. Short: from regulator "+5V" Jack. Don't connect anything "VVD2" Jack. (default)
Input Selection VCRRC VCRRC
side: Input VCRRC from VCRRC jack. "I/O" side: Input VCRC from VCRC jack. (Note: Refer AK4702)
Table Jumper list
<KM067304>
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[AKD4702]
Serial Control
AK4702 controlled printer port (parallel port) IBM-AT compatible Connect PORT3 (µP-IF) with wire flat cable packed with AKD4702. careful connector direction. Flat cable should connected 10-pin header, line 10pin header pin.
Connect
SDA(ACK) AKD4702
wire flat cable Connector PORT3 µP-IF
Header
Figure Connection flat cable PORT3
Input/Output port List
Table Input/Output port List Signal Name (VCRINL), (VCRINR), (TVINL), (TVINR) (MONOIN) (VCROUTL), (VCROUTR), (TVOUTL), (TVOUTR), (MONOOUT) Port2 (TORX176) (RX) (ENCB), (ENCG), (ENCRC), (ENCC), (ENCV), J23(ENCY), J25(TVVIN), J14(VCRVIN), J18(VCRRC; Note), J20(VCRG), J22(VCRB) (VCRCOUT; Note), (TVVOUT), (TVRC), (TVG), (TVB), (RFV), (VCRVOUT) (VCRSB) (VCRSB) (TVSB) (VCRFB) (TVFB) Notes Max: 2Vrms Max: 1Vrm Max: 3Vrm Max: D5V+0.3V Max: 1.5Vp-p Max: 3Vp-p Max: VP+0.3V Max: Max: VVD1+0.3V Max: VVD2
Input Audio Output Digital Input Input Video Output Slow Blanking Fast Blanking Input Output Input Output
Note: Refer JP12 AK4702.
indication content
turns during each output "H". [LE1] (Unlock Parity Error DIF): (AK4112B). Normally off. [LE2] (Validity Flag): (AK4112B). Normally off.
Toggle switch (SW1 board) operation
"H": AK4702 Active. "L": AK4702 Powered Down (Note; When power AKD4702 first, should switched from "H".)
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[AKD4702]
MEASUREMENT RESULTS Audio
[Measurement condition] Measurement unit Audio Precision System Cascade MCLK 256fs BICK 64fs 48kHz 10Hz20kHz 18bit Power Supply VD=5V, VDD1=5V, VDD2=5V, VP=12V Interface Temperature Room Volume#0=Volume#1=0dB Measurement signal line path: Volume#0 Volume#1 TVOUTL/R Parameter S/(N+D) 2Vrms Output Input signal 1kHz, 0dBFS 1kHz, -60dBFS data Measurement filter 20kLPF 22kLPF, A-weighted 22kLPF, A-weighted Results [dB] 91.5 96.0 96.0
Plots
Figure 1-1. (1kHz, 0dBFS input) 2Vrms output Figure 1-2. (1kHz, -60dBFS input) Figure 1-3. (Noise floor) Figure 1-4. (Out-of band noise) Figure 1-5. THD+N Input Level (fin=1kHz) Figure 1-6. THD+N (Input Level=0dBFS) Figure 1-7. Linearity (fin=1kHz) Figure 1-8. Frequency Response (Input Level=0dBFS) Figure 1-9. Crosstalk (Input Level=0dBFS)
<KM067304>
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[AKD4702]
Video
[Measurement condition] Signal Generator Sony Tectonics TG2000 Measurement unit Sony Tectonics VM700T VD=5V, VDD1=5V, VDD2=5V, VP=12V Power Supply Interface Room Temperature Measurement signal line path: ENCV TVVOUT, ENCRC TVRC Parameter Measurement conditions Input flat field Filter Uni-weighted, 15kHz 5MHz Input 100%red(ENCRC), Measured TVVOUT Input Modulated Lamp Input Modulated Lamp Results 75.8 Unit
Crosstalk
-0.1 +0.24 +0.40
deg.
Plots
Figure 2-1. Noise spectrum (Input=0%flat field, BW=15kHz 5MHz, weighted) Figure 2-2. Frequency Response (Input= Multi Burst) Figure Crosstalk (Input= 100% (ENCRC), measured TVVOUT) Figure (Input= Modulated Lamp)
<KM067304>
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[AKD4702]
Plots (Audio)
-100 -110 -120 -130 -140 -150
AK4702 (DAC->TVOUT: fs=48kHz, sigal 1kHz/0dB)
Figure1-1. (fin=1kHz Input Level=0dBFS)
-100 -110 -120 -130 -140 -150
AK4702 (DAC->TVOUT: fs=48kHz, sigal 1kHz/-60dB)
Figure-1-2. (fin=1kHz Input Level=-60dBFS)
<KM067304>
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[AKD4702]
-100 -110 -120 -130 -140 -150
AK4702 (DAC->TVOUT: fs=48kHz, sigal)
Figure1-3. (Noise Floor)
-100 -110 -120 -130 -140 -150
AK4702 (DAC->TVOUT: fs=48kHz, sigal, band)
100k
Figure1-4. (Outband Noise)
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[AKD4702]
AK4702 THD+N Level (DAC->TVOUT: fs=48kHz, signal= 1kHz
-100 -110
-100
dBFS
Figure1-5. THD+N Input level (fin=1kHz)
AK4702 THD+N Input Frequency (DAC->TVOUT: fs=48kHz, signal=
-100
Figure1-6. THD+N Input Frequency (Input level=0dBFS)
<KM067304>
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[AKD4702]
AK4702 Linearity ->TVOUT: fs=48kHz, signal= 1kHz
-100
-110 -110
-100
dBFS
Figure1-7.Linearity (fin=1kHz)
+0.5
AK4702 Frequency response (DAC->TVOUT: fs=48kHz, signal=
+0.4
+0.3
+0.2
+0.1 -0.1
-0.2
-0.3
-0.4
-0.5
Figure1-8. Frequency Response (Input level=0dBFS)
<KM067304>
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[AKD4702]
AK4702 Crosstalk (DAC->TVOUT: fs=48kHz, signal=
-100
-105 -110 -115
-120
Figure1-9. Crosstalk (Input level=0dBFS)
<KM067304>
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[AKD4702]
Plots(Video)
Figure 2-1. Noise spectrum (Input=0%flat field, BW=15kHz 5MHz, weighted)
Figure 2-2. Frequency Response (Input= Multi Burst)
<KM067304>
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[AKD4702]
Figure Crosstalk (Input= 100% (ENCRC), measured TVVOUT)
Figure (Input= Modulated Lamp)
<KM067304>
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[AKD4702]
CONTROL SOFTWARE MANUAL Introduction
This manual software that controls AK4702, with SCART switch. enclosed software AKD4702.exe control registers AK4702 using control I/F.
System Requirements
this software, followings required PC.: Windows 95/98/ME/2000/XP. (This software does operate Windows NT.) Printer port
Set-up evaluation board control software
AKD4702. Insert Connect IBM-AT compatible with AKD4702 10-line type flat cable (packed with AKD4702). Take care direction 10pin header. (Please install driver CD-ROM disk when this control software used Windows 2000/XP. Please refer "Installation Manual Control Software Driver device control software". case Windows95/98/ME, this installation needed. This control software does operate Windows NT.) CD-ROM disk labeled "AKD4702 Control Program 1.0" into CD-ROM disk drive.
Operations
Execute AKD4702.exe. Then following window opens. function each button shown below. Clicking button does each operation alone.
Write defalt resisters.
Read resisters.
Close this window.
"means "1". Write each byte.
Space means "0".
Read address this box.
Read 08H.
Write DATA address this box.
<KM067304>
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[AKD4702]
Write/Read Register There ways Write/Read register. Check After checking each each bit, click "Write" "Read" button right end. each check means check means "0". Each check mark toggles clicking. address Read-only. Edit There edit left bottom. register written read using edit box. When writing register, input DATA Address click "Write" button. When reading register, input Address click "Read" button.
<KM067304>
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[AKD4702]
IMPORTANT NOTICE These products their specifications subject change without notice. Before considering application, consult Asahi Kasei Microsystems Co., Ltd. (AKM) sales office authorized distributor concerning their current status. assumes liability infringement patent, intellectual property, other right application information contained herein. export these products, devices systems containing them, require export license other official approval under regulations country export pertaining customs tariffs, currency exchange, strategic materials. products neither intended authorized critical components safety, life support, other hazard related device system, assumes responsibility relating such use, except with express written consent Representative Director AKM. used here: hazard related device system designed intended life support maintenance safety applications medicine, aerospace, nuclear energy, other fields, which failure function perform reasonably expected result loss life significant injury damage person property. critical component whose failure function perform reasonably expected result, whether directly indirectly, loss safety effectiveness device system containing which must therefore meet very high standards performance reliability. responsibility buyer distributor product distributes, disposes otherwise places product with third party notify that party advance above content conditions, buyer distributor agrees assume responsibility liability hold harmless from claims arising from said product absence such notification.
<KM067304>
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[AKD4702]
<KM067304>
2002/12
4112B_3.3V
0.1u
MCLK BICK LRCK SDATA Logic
PORT1
Logic
Logic
74HCU04
(OPEN)
(OPEN)
4112B_3.3V
Logic
PORT2 R-PACK5R
TORX176
BNC(RX)
0.1u
Size Date:
0.1u
12.288MHz
DVDD DVSS TVDD V/TX AVDD AVSS DIF0/RX2 DIF1/RX3 DIF2/RX4
CM0/CDTO CM1/CDTI OCKS1/CCLK OCKS0/CSN MCK01 MCK02 DAUX BICK SDTO LRCK FS96 AUTO
INTRUPT
MCLK
MCLK BICK SDTI LRCK Logic
BICK SDTI LRCK
AK4112BVF
74HCU04
DIF0 DIF2 DIF0 DIF2
AK4112B
DIP-5
74HCU04
Logic
74HCU04
0.1u
DIF0 DIF2
74HCU04 74HCU04
0.1u
TORX
Title Document Number
AKD4702
AK4112B
Sheet
Resister Contorol
VVD2
Analog Ground Digital Ground
LRCK SDTI BICK MCLK
input
+C13
0.1u
(VVSS) +C16
0.1u
+C19
+C23
0.1u
0.1u
(VVSS) (VVSS)
+12V
+C21
VCRVOUT
MCLK
TVFB
LRCK
BICK
SDTI
(VVSS2)
VCRC VVSS2 TVVOUT VVD2 TVRC VVD1 ENCB ENCG ENCRC
PVCOM DVCOM MONOOUT
0.1u
(VVSS)
VVD1
TVOUTL TVOUTR VCROUTL VCROUTR MONOIN TVINL TVINR INTRUPT VCRINR
4702
MONOOUT TVOUTL TVOUTR VCROUTL VCROUTR
Analog output
+C15
0.1u
(VVSS2) Video Block output
VCRC TVVOUT TVRC VCRVOUT TVFB TVSB VCRSB ENCB ENCG ENCRC ENCC ENCV ENCY TVVIN VCRVIN VCRFB VCRRC VCRG VCRB
MONOIN TVINL TVINR VCRINL VCRINR
Analog input
VCRVIN
VCRRC
VCRSB
VCRFB
ENCC TVVIN ENCV ENCY
VCRINL
VCRG
VCRB
TVSB
Video Block input/output
Video Block input
INTRUPT
Title Size Date: Document Number
AKD4702
AK4702
Sheet
VCRINR 0.47u (open)
(VVSS)
MONOOUT
VCRINR
MONOOUT
(VVSS) (VVSS)
(VVSS)
VCRINL 0.47u (open) TVINR
(VVSS)
TVOUTL
VCRINL
(VVSS)
TVOUTL
(VVSS)
(VVSS)
From Analog output
TVINR 0.47u (open)
(VVSS) (VVSS)
TVOUTR
TVOUTR
Analog input
(VVSS)
(VVSS)
TVINL 0.47u (open)
VCROUTL
TVINL
(VVSS)
VCROUTL
(VVSS)
(VVSS)
(VVSS)
MONOIN 0.47u (open)
(VVSS) (VVSS)
VCROUTR
MONOIN
VCROUTR
(VVSS)
(VVSS)
Title Size Date:
Document Number
AKD4702
Sheet
Friday, April 2003
Analog Input/Output Circuit
74HCT541
Logic
Logic
74HCT14 74HCT14
PORT3
SDA(ACK)
uP-I/F
0.1u
74HCT14
74LS07 74LS07 74LS07 74LS07 74LS07
74LS07
Logic
(short)
74HCT14 74HCT14 74HCT14
SDA(ACK)
Logic
NJM78M05FA
+12V
+C39
+12V Short
0.1u
0.1u
Short VVD1 JP10 VDD1 VVD2
Logic
LP2950A 4112B_3.3V
0.1u Logic 0.1u
0.1u
0.1u
0.1u
0.1u
VVD1
0.1u
74HCT14, 74HCU04, 74LS07, 74HCT541
Title
VVD2 short
JP11 VDD2
Size Date:
Document Number
AKD4702
Sheet
POWER SUPPLY
ENCB
(short)
VCRVIN ENCB
(VVSS2) (VVSS2)
(short)
VCRVIN 0.1u
0.1u
(VVSS2)
ENCG
(VVSS2)
(short)
VCRFB ENCG
(VVSS2) (VVSS2)
VCRFB
0.1u
(VVSS2)
(VVSS2)
ENCRC
ENCRC 0.1u
VCRRC
(VVSS2) (VVSS2)
JP12
(short)
VCRRC 0.1u VCRCOUT
(short)
VCRRC
(VVSS2)
(VVSS2)
ENCC
(VVSS2) (VVSS2)
(short)
ENCC 0.1u
VCRG
(VVSS2) (VVSS2)
(short)
VCRG 0.1u
ENCV
(short)
ENCV 0.1u
VCRB
(VVSS2) (VVSS2)
(short)
VCRB 0.1u
(VVSS2)
(VVSS2)
ENCY
(VVSS2) (VVSS2)
(short)
ENCY 0.1u
VCRSB
(VVSS) (VVSS)
VCRSB
TVVIN
(VVSS2)
(short)
TVVIN 0.1u
Size Date:
Title Document Number
AKD4702
Sheet
(VVSS2)
Video Block Input Circuit
VCRC
VCRCOUT
VCRCOUT
(VVSS2)
(VVSS2)
TVVOUT
TVVOUT
TVFB
(VVSS2)
TVFB
TVRC
TVRC
(VVSS2)
TVSB
TVSB
(VVSS2)
(VVSS2)
(VVSS2)
(VVSS2)
VCRVOUT
VCRVOUT
(VVSS2)
Title Size Date:
Document Number
AKD4702
Sheet
Video Block Output Circuit

AKD4702 Evaluation board Rev.A AK4702 GENERAL DESCRIPTION AK

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