AKD4683-A AK4683 Evaluation Board Rev.1 FEATURE AKD4683-A ev

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AKD4683-A AK4683 Evaluation Board Rev.1 FEATURE AKD4683-A ev

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[AKD4683-A]
AKD4683-A
AK4683 Evaluation Board Rev.1
FEATURE AKD4683-A evaluation board AK4683, single chip 24bit CODEC that channels four channels with internal DIR, DIT. This board interfaces with AKM's evaluation boards converter converter makes easy evaluate AK4683. Also this board digital audio interface then achieves interface with digital audio systems opt-connector connector. Ordering guide
AKD4683-A AK4683 Evaluation Board wire flat cable connection with printer port (IBM-AT compatible machine), control software AK4589, driver control software Windows 2000/XP packed with this. Control software does work Windows Windows 2000/XP needs installation driver. Windows 95/98/ME does need installation driver. AK4683 supports standard-mode I2C-bus (max: 100kHz), does support fast-mode I2C-bus system (max: 400kHz).
FUNCTION On-board clock generator (use AK4114, Compatible with types digital audio interface Optical output/input input/output 10pin header interface with external data source (x2) connector clock input with external clock source 10pin header register control
AVDD1 AVDD2 HVDD DVDD PVDD TVDD Regulator Regulator 3.3V
+12V -12V
RX0/1/2/3 Control Data 10pin Header PORT
OpAmp LOUT1/ROUT1
OpAmp LOUT2/ROUT2 HP-Jack HPL/HPR LIN1/RIN1
AK4683
10pin Header PORT 10pin Header AK4114 AK4114 IN/OUT
LIN2/RIN2 LIN3/RIN3 LIN5/RIN5 LIN4/RIN4 LIN6/RIN6 MCKI
IN/OUT
(Note) AK4114 DIR, X'tal oscillator. Figure AKD4683-A Block Diagram Circuit diagram layout attached this manual.) <KM077504> -12005/08
[AKD4683-A]
EVALUATION BOARD MANUAL Operation sequence
Power supply lines jumpers power supply ground 1-1. Power supply circuit 1-2. Power supply lines 1-3. Jumpers power supply ground Register control 2-1. 10-wire flat cable register control 2-2. 4-wire serial control 2-3. I2C-bus control 10-wire flat cable interface with external data source 3-1. PORT4 (for PORTA) 3-2. PORT5 (for PORTB) Jumpers Master Clock: MCKI MCLK2 4-1. External Master Clock 4-2. PORTA: AK4114 (U7) 4-3. PORTB: AK4114 (U10) Jumpers Master Clock: MCKO X'tal 5-1. PORTA: AK4114 (U7) 5-2. PORTB: AK4114 (U10) Switches 6-1. (PORTA_DIR/4683) 6-2. (PORTB_DIR) Evaluation mode 7-1. with internal 7-2. with internal 7-3. with external 7-3-1. with PORTA: AK4114 (U7) external 7-3-2. with PORTB: AK4114 (U10) external 7-4. with external 7-4-1. with PORTA: AK4114 (U7) external 7-4-2. with PORTB: AK4114 (U10) external 7-5. Internal loop back (Analog input Analog output) 7-6. Headphone output Power 8-1. Toggle switch 8-2. 8-3. Reset after power
<KM077504>
2005/08
[AKD4683-A]
Power supply lines jumpers power supply ground
1-1. Power supply circuit
-12V N12V HVSS AVDD1 AVSS1 AVDD1 AVDD2 HVSS AVDD2 DVDD DVSS DVDD (short) PVDD PVSS PVDD
0.1u
(short)
(short)
JP25
AVDD1
NJM78M05FA
+12V P12V 0.1u HVSS HVSS (short)
AVDD1_SEL
0.1u
AVSS1
AVSS1
AVSS1
(short)
JP26 AVDD2 AVDD1 AVDD2_SEL
HVDD HVSS HVDD (short) JP27 HVDD AVDD1 HVDD_SEL
(short)
JP28 DVDD AVDD1 DVDD_SEL PVDD JP30 AVDD1 PVDD_SEL TA48M033F
(short)
JP29 DVDD
PVSS
DVDD VDD_SEL
(short)
(short) DVSS 4683_TVDD (short) 4114_TVDD (short)
TVDD(4683) JP32 REG2 TVDD_SEL D3.3V (short) DVSS
Figure Power supply circuit
<KM077504>
TVDD(4683)
JP31 DVDD
0.1u
0.1u
HVSS
2005/08
[AKD4683-A]
1-2. Power supply lines Name jack Color jack Voltage Used Comment attention Default Setting Open
Should always connected when JP25 (AVDD1_SEL) AVDD1 side. AVDD1 Orange +4.5+5.5V AVDD1 AK4683 open when JP25 (AVDD1_SEL) side. Should always connected when JP26 (AVDD2_SEL) AVDD2 side. AVDD2 Orange +4.5+5.5V AVDD2 AK4683 open when JP26 (AVDD2_SEL) AVDD1 side. Should always connected when JP28 (DVDD_SEL) DVDD side. DVDD Orange +4.5+5.5V DVDD AK4683 open when JP28 (DVDD_SEL) AVDD1 side. Should always connected when JP30 (PVDD_SEL) PVDD side. PVDD Orange +4.5+5.5V PVDD AK4683 open when JP30 (PVDD_SEL) AVDD1 side. Should always connected when JP27 (HVDD_SEL) HVDD side. HVDD Orange +4.5+5.5V HVDD AK4683 open when JP27 (HVDD_SEL) AVDD1 side. Should always connected when JP29 (VDD_SEL) side. Orange +4.5+5.5V Logic Parts open when JP29 (VDD_SEL) DVDD side. Should always connected when JP31 (DVDD) open, JP32 (TVDD_SEL) TVDD side. TVDD TVDD AK4683, Orange +2.7+5.5V open when JP31 (DVDD) open, (4683) TVDD AK4114 JP32 (TVDD_SEL) REG2 side, when JP31 (DVDD) short, JP32 (TVDD_SEL) TVDD side. Power supply Regulator, Output Buffer Regulator, +12V (Op-amp). +12+15V Output Buffer (Op-amp) Should always connected. Power supply Output Buffer (Op-amp). -12V Blue Output Buffer (Op-amp) -12-15V Should always connected. AVSS1 Black Analog Ground Analog Ground. Should always connected. HVSS Black Analog Ground Analog Ground. Should always connected. DVSS Black Analog Ground Analog Ground. Should always connected. PVSS Black Analog Ground Analog Ground. Should always connected. Digital Ground. DGND Black Digital Ground Should connected when open. open when short. Table Power supply lines (Note) Each supply line should distributed from power supply unit.
Open
Open
Open
Open
+12V -12V
<KM077504>
2005/08
[AKD4683-A]
1-3. Jumpers power supply ground 1-3-1. AVDD1 JP25 (AVDD1_SEL) controls AVDD1 source (regulator jack "AVDD1").
JP25 AVDD1_SEL
JP25 AVDD1_SEL
AVDD1
AVDD1
REG<Default>
AVDD1
Figure JP25 (AVDD1_SEL) 1-3-2. AVDD2 JP26 (AVDD2_SEL) controls AVDD2 source (AVDD1 line jack "AVDD2").
JP26 AVDD2_SEL
JP26 AVDD2_SEL
AVDD1
AVDD2
AVDD1
AVDD2
(AVDD1)<Default> Figure JP26 (AVDD2_SEL)
(AVDD2)
1-3-3. DVDD JP28 (DVDD_SEL) controls DVDD source (AVDD1 line jack "DVDD").
JP28 DVDD_SEL
JP28 DVDD_SEL
AVDD1
DVDD
AVDD1
DVDD
(AVDD1)<Default> (DVDD) Figure JP28 (DVDD_SEL)
<KM077504>
2005/08
[AKD4683-A]
1-3-4. PVDD JP30 (PVDD_SEL) controls PVDD source (AVDD1 line jack "PVDD").
JP30 PVDD_SEL
JP30 PVDD_SEL
PVDD
AVDD1
PVDD
AVDD1
(AVDD1)<Default> Figure JP30 (PVDD_SEL)
1-3-5. HVDD
(PVDD)
JP27 (HVDD_SEL) controls HVDD source (AVDD1 line jack "HVDD").
JP27 HVDD_SEL
JP27 HVDD_SEL
AVDD1
HVDD
AVDD1
HVDD
(AVDD1)
Figure JP27 (HVDD_SEL) 1-3-6.
(HVDD)<Default>
JP29 (VDD_SEL) controls source (DVDD line jack "VDD").
JP29 VDD_SEL
JP29 VDD_SEL
DVDD
DVDD
(DVDD)
Figure JP29 (VDD_SEL)
(VDD)<Default>
<KM077504>
2005/08
[AKD4683-A]
1-3-7. TVDD DVDD JP31 (DVDD) controls separate (open) connect (short) TVDD DVDD.
JP31 DVDD
JP31 DVDD
(open)<Default>
Figure JP31 (DVDD)
(short)
1-3-8. TVDD AK4683 AK4114 JP32 (TVDD_SEL) controls TVDD source (regulator jack "TVDD (4683)") AK4683 AK4114.
JP32 TVDD_SEL
JP32 TVDD_SEL
REG2
TVDD
REG2
TVDD
(REG2)<Default> (TVDD) Figure JP32 (TVDD_SEL)
1-3-9. Analog Ground Digital Ground (DGND) controls separate (open) connect (short) Analog Ground Digital Ground. this case, jack "DGND" open.
DGND DGND
(open)<Default> (short) Figure (DGND)
<KM077504>
2005/08
[AKD4683-A]
Register control
2-1. 10-wire flat cable register control AK4683 controlled printer port (parallel port) IBM-AT compatible Connect printer port (parallel port) PORT2 (uP-I/F) AKD4683-A 10-wire flat cable (packed with AKD4683-A). Take care direction 10-pin connector 10-pin header. (The line side 10-wire flat cable 10-pin connector should connected No.5pin No.6pin 10-pin header.)
PORT2 UP-I/F Connect CCLK CDTI (ACK) CDTO 10-wire flat cable 10-pin connector
10-pin header
AKD4683-A
Figure 10-wire flat cable, 10-pin connector 10-pin header 2-2. 4-wire serial control (SDA/CDTO) "CDTO/CM0=H". <Default>
SDA/CDTO
CDTO/CM0=H CM0=L
(CDTO/CM0=H)<Default> Figure (SDA/CDTO)
(PORT A_DIR/4683): No.8 (I2C) "OFF". <Default>
<KM077504>
2005/08
[AKD4683-A]
2-3. C-bus control (SDA/CDTO) "SDA".
SDA/CDTO
CDTO/CM0=H CM0=L
(SDA) Figure (SDA/CDTO)
(PORT A_DIR/4683): No.8 (I2C) "ON".
<KM077504>
2005/08
[AKD4683-A]
10-wire flat cable interface external
AK4683 achieve interface with external data source PORT4 (PORTA), PORT5 (PORTB). Connect PORT4 (PORTA) external port PORT5 (PORTB) external port 10-wire flat cable. Take care direction 10-pin connector 10-pin header. (The line side 10-wire flat cable 10-pin connector should connected No.5pin No.6pin 10-pin header.) 3-1. PORT4 (for PORTA) layout PORT4 (for PORTA) shown Figure
PORT4 MCLK BICKA OLRCKA SDTOA MCKO SDTIA1 SDTIA2
SDTIA3 ILRCKA PORTA
Figure PORT4 (for PORTA) 3-2. PORT5 (for PORTB) layout PORT5 (for PORTB) shown Figure
MCLK BICKB LRCKB SDTOB PORTB PORT5 MCKO SDTIB
Figure PORT5 (for PORTB)
<KM077504>
2005/08
[AKD4683-A]
Jumpers Master Clock: MCKI MCLK2
4-1. External Master Clock JP19 (MCLK_SEL) controls External Master Clock source (MCKI MCLK2) AK4683. these cases above, JP16 (MCLKA_SEL) JP22 (MCLKB_SEL) should open.
JP19 MCLK_SEL MCLK_SEL
MCLK2
MCKI
MCLK2
MCKI
(MCKI) JP16 MCLKA_SEL
(MCLK2)
MCKO1
(open)<Default>
MCKO2
JP22 MCLKB_SEL
MCKO1
MCKO2
(open)<Default>
Figure JP19 (MCLK_SEL)
<KM077504>
2005/08
[AKD4683-A]
4-2. PORTA: AK4114 (U7) JP16 (MCLKA_SEL) controls PORTA: AK4114 (U7): Master Clock source (MCKO1 MCKO2) AK4683: MCLK2. these cases above, JP19 (MCLK_SEL) JP22 (MCLKB_SEL) should open.
JP16 MCLKA_SEL MCLKA_SEL
MCKO1
MCKO2
MCKO1
MCKO2
(MCKO1) JP19 MCLK_SEL
(MCKO2)
MCLK2
MCKI
(open)<Default> JP22 MCLKB_SEL
MCKO1
MCKO2
(open)<Default>
Figure JP16 (MCLKA_SEL)
<KM077504>
2005/08
[AKD4683-A]
4-3. PORTB: AK4114 (U10) JP22 (MCLKB_SEL) controls PORTB: AK4114 (U10): Master Clock source (MCKO1 MCKO2) AK4683: MCLK2. these cases above, JP19 (MCLK_SEL) JP16 (MCLKA_SEL) should open.
JP22 MCLKB_SEL MCLKB_SEL
MCKO1
MCKO2
MCKO1
MCKO2
(MCKO1)
(MCKO2) JP19 MCLK_SEL
MCLK2
MCKI
(open)<Default> JP16 MCLKA_SEL
MCKO1
(open)<Default>
MCKO2
Figure JP22 (MCLKB_SEL)
<KM077504>
2005/08
[AKD4683-A]
Jumpers Master Clock: MCKO X'tal
5-1.PORTA: AK4114 (U7) JP10 (XTIA) controls Master Clock source (AK4683: MCKO (short) X'tal (open)) PORTA: AK4114 (U7):XTI.
JP10 XTIA
JP10 XTIA
(open)<Default>
Figure JP10 (XTIA) 5-2. PORTB: AK4114 (U10)
(short)
JP20 (XTIB) controls Master Clock source (AK4683: MCKO (short) X'tal (open)) PORTB: AK4114 (U10):XTI.
JP20 XTIB
JP20 XTIB
(open)<Default>
Figure JP20 (XTIB)
(short)
<KM077504>
2005/08
[AKD4683-A]
Switches
6-1. (PORT A_DIR/4683) Setting AK4683 PORT AK4114 (U7) Name ("H") ("L") DIF0 Setting Audio Format AK4114 DIF1 (Refer Table DIF2 Selection Clock Mode (Clock Source) (Refer Table OCKS0 Selection frequency Master Clock Output OCKS1 (ReferTable4.) I2C-bus control mode 4-wire serial control mode Table (PORT A_DIR 4683) (Note) ("1"), OFF: ("0") 6-2. (PORT B_DIR) Setting PORT AK4114 (U10) Name ("H") ("L") DIF0 Setting Audio Format AK4114 DIF1 (Refer Table DIF2 Selection Clock Mode (Clock Source) (Refer Table OCKS0 Selection frequency Master Clock Output OCKS1 (Refer Table4.) Un-used Table (PORT B_DIR) (Note) ("1"), OFF: ("0")
Default ("L", "0") ("H", "1") ("H", "1") ("L", "0") ("L", "0") ("L", "0") ("L", "0") ("L", "0")
Default ("L", "0") ("H", "1") ("H", "1") ("L", "0") ("L", "0") ("L", "0") ("L", "0") ("L", "0")
<KM077504>
2005/08
[AKD4683-A]
Mode
DIF2
DIF1
DIF0
LRCK 24bit, Left justified 16bit, Right justified 24bit, Left justified 18bit, Right justified 24bit, Left justified 20bit, Right justified 24bit, Left justified 24bit, Right justified 24bit, Left justified 24bit, Left justified 24bit, 24bit, 24bit, Left justified 24bit, Left justified 24bit, 24bit, Table Audio Interface Format AK4114 DAUX SDTO
BICK 64fs 64fs 64fs 64fs 64fs 64fs 64-128fs 64-128fs
<Default>
Mode
UNLOCK X'tal Clock source SDTO (Note1) <Default> X'tal DAUX X'tal DAUX X'tal DAUX Table Clock Mode (Clock Source) (Note1) When X'tal used reference clock (XTL0, 1"), this setting "OFF" (Note2) Normally, "Default" setting. OCKS1 OCKS0 MCKO1 MCKO2 X'tal (max) 256fs 256fs 256fs 256fs 128fs 256fs 512fs 256fs 512fs 128fs 64fs 128fs Table Frequency Master Clock Output
<Default>
<KM077504>
2005/08
[AKD4683-A]
Evaluation mode
7-1. with internal 7-1-1. Connection connector case input through RX0, optical connector PORT3 (TORX176) connector (RX0) available. case input through RX1, RX3, only optical connector PORT3 available. 7-1-2. Setting jumper case input through RX0, (RX0) controls digital input (optical connector PORT3 connector J14).
(OPT)<Defaukt>
Figure (RX0)
(RCA)
case input through RX1, RX3, jumpers (RX1), (RX2) (RX3) control digital input channels (RX1, RX3) from PORT3. About only input channels, some jumpers (RX1), (RX2) (RX3) OPT. About no-input channels, other jumpers (RX1), (RX2) (RX3) GND.
(OPT)
(GND)<Default>
(OPT)
(GND)<Default>
(OPT)
(GND)<Default>
Figure (RX1), (RX2), (RX3)
<KM077504>
2005/08
[AKD4683-A]
Setting interface signal PORTA: AK4114 (U7) follows.
JP17 BICKA
JP18 OLRCKA
JP11 ILRCKA
JP12 SDTIA
JP14 JP13 SDTIA1_SEL SDTIA2_SEL
JP15 SDTIA3_SEL
(GND) (GND) (GND) Figure JP17 (BICKA), JP18 (OLRCKA), JP11 (ILRCKA), JP12 (SDTIA), JP13 (SDTIA1_SEL), JP14 (SDTIA2_SEL), JP15 (SDTIA3_SEL)
Setting interface signal PORTB: AK4114 (U10) follows.
(open)
(open)
(open)
(open)
JP23 BICKB
JP24 LRCKB
JP21 SDTIB_SEL
(open)
(open)
(GND)
Figure JP23 (BICKB), JP24 (LRCKB), JP21 (SDTIB_SEL) 7-1-3. Setting switch (PORTA_DIR/4683) (PORTB_DIR) "Don't care". 7-1-4. Setting toggle switch (DIR PORTA) OFF. (DIR PORTB) OFF. (PDN) OFFON.
<KM077504>
2005/08
[AKD4683-A]
7-2. with internal 7-2-1. Connection connector output, optical connector PORT1 (TOTX176) connector (TX1) available. 7-2-2. Setting jumper (TX1) controls digital output (optical connector PORT1 connector J13).
(OPT)<Default>
(RCA)
Figure (TX1) Setting interface signal PORTA: AK4114 (U7) follows.
JP17 BICKA
JP18 OLRCKA
JP11 ILRCKA
JP12 SDTIA
JP14 JP13 SDTIA1_SEL SDTIA2_SEL
JP15 SDTIA3_SEL
(open)
(open)
(open)
(open)
(GND)
(GND)
(GND)
Figure JP17 (BICKA), JP18 (OLRCKA), JP11 (ILRCKA), JP12 (SDTIA), JP13 (SDTIA1_SEL), JP14 (SDTIA2_SEL), JP15 (SDTIA3_SEL) Setting interface signal PORTB: AK4114 (U10) follows.
JP23 BICKB
JP24 LRCKB
JP21 SDTIB_SEL
(open)
(open)
(GND)
Figure JP23 (BICKB), JP24 (LRCKB), JP21 (SDTIB_SEL) 7-2-3. Setting switch (PORTA_DIR/4683) (PORTB_DIR) "Don't care". 7-2-4. Setting toggle switch (DIR PORTA) OFF. (DIR PORTB) OFF. (PDN) OFFON.
<KM077504>
2005/08
[AKD4683-A]
7-3. with external 7-3-1. with PORT AK4114 (U7) external 7-3-1-1. Connection connector digital input, connector (PORTA_RX0) available. 7-3-1-2. Setting jumper Setting interface signal PORTA: AK4114 (U7) follows.
JP17 BICKA
JP18 OLRCKA
JP11 ILRCKA
JP12 SDTIA
JP14 JP13 SDTIA1_SEL SDTIA2_SEL
JP15 SDTIA3_SEL
(short)
(open)
(short)
(short)
(DIR)
(DIR)
(DIR)
Figure JP17 (BICKA), JP18 (OLRCKA), JP11 (ILRCKA), JP12 (SDTIA), JP13 (SDTIA1_SEL), JP14 (SDTIA2_SEL), JP15 (SDTIA3_SEL) Setting interface signal PORTB: AK4114 (U10) follows.
JP23 BICKB
JP24 LRCKB
JP21 SDTIB_SEL
(open)
(open)
(GND)
Figure JP23 (BICKB), JP24 (LRCKB), JP21 (SDTIB_SEL) When master clock PORTA: AK4114 (U7): MCKO1 supplied AK4683: MCLK2, setting master clock follows.
JP16 MCLKA_SEL
JP22 MCLKB_SEL
JP19 MCLK_SEL
MCKO1
MCKO2
MCKO1 MCKO2
MCLK2
MCKI
(MCKO1)
(open)<Default>
(open)<Default>
Figure JP16 (MCLKA_SEL), JP22 (MCLKB_SEL), JP19 (MCLK_SEL) 7-3-1-3. Setting switch (PORTA_DIR/4683): 5pin (CM1) OFF. (PORTA_DIR/4683): 4pin (CM0) OFF. 7-3-1-4. Setting toggle switch (DIR PORTA) (DIR PORTB) OFF. (PDN) OFFON.
<KM077504>
2005/08
[AKD4683-A]
7-3-2. with PORT AK4114 (U10) external 7-3-2-1. Connection connector digital input, connector (PORTB_RX0) available. 7-3-2-2. Setting jumper Setting interface signal PORTA: AK4114 (U7) follows.
JP17 BICKA
JP18 OLRCKA
JP11 ILRCKA
JP12 SDTIA
JP14 JP13 SDTIA1_SEL SDTIA2_SEL
JP15 SDTIA3_SEL
(open)
(open)
(open)
(open)
(GND)
(GND)
(GND)
Figure JP17 (BICKA), JP18 (OLRCKA), JP11 (ILRCKA), JP12 (SDTIA), JP13 (SDTIA1_SEL), JP14 (SDTIA2_SEL), JP15 (SDTIA3_SEL) Setting interface signal PORTB: AK4114 (U10) follows.
JP23 BICKB
JP24 LRCKB
JP21 SDTIB_SEL
(short)
(short)
(DIR)
Figure JP23 (BICKB), JP24 (LRCKB), JP21 (SDTIB_SEL) When master clock PORTB: AK4114 (U10): MCKO1 supplied AK4683: MCLK2, setting master clock follows.
JP22 MCLKB_SEL
JP16 MCLKA_SEL
JP19 MCLK_SEL
MCKO1
(open) (open) (MCKO1) Figure JP22 (MCLKB_SEL), JP16 (MCLKA_SEL), JP19 (MCLK_SEL)
MCKO2
MCKO1
MCKO2
MCLK2
MCKI
7-3-2-3. Setting switch (PORTB_DIR): 5pin (CM1) OFF. (PORTB_DIR): 4pin (CM0) OFF. 7-3-2-4. Setting toggle switch (DIR PORTA) OFF. (DIR PORTB) (PDN) OFFON.
<KM077504>
2005/08
[AKD4683-A]
7-4. with external 7-4-1. with PORT AK4114 (U7) external 7-4-1-1. Connection connector digital output, connector (PORTA_TX1) available. 7-4-1-2. Setting jumper Setting interface signal PORTA: AK4114 (U7) follows.
JP17 BICKA
JP18 OLRCKA
JP11 ILRCKA
JP12 SDTIA
JP14 JP13 SDTIA1_SEL SDTIA2_SEL
JP15 SDTIA3_SEL
(short)
(short)
(open)
(open)
(GND)
(GND)
(GND)
Figure JP17 (BICKA), JP18 (OLRCKA), JP11 (ILRCKA), JP12 (SDTIA), JP13 (SDTIA1_SEL), JP14 (SDTIA2_SEL), JP15 (SDTIA3_SEL) Setting interface signal PORTB: AK4114 (U10) follows.
JP23 BICKB
JP24 LRCKB
JP21 SDTIB_SEL
(open)
(open)
(GND)
Figure JP23 (BICKB), JP24 (LRCKB), JP21 (SDTIB_SEL) When master clock AK4683: MCKO supplied PORTA: AK4114 (U7): XTI, setting master clock follows.
JP10 XTIA
(short) Figure JP10 (XTIA)
7-4-1-3. Setting switch (PORTA_DIR/4683): 5pin (CM1) OFF. (PORTA_DIR/4683): 4pin (CM0) 7-4-1-4. Setting toggle switch (DIR PORTA) (DIR PORTB) OFF. (PDN) OFFON.
<KM077504>
2005/08
[AKD4683-A]
with PORT AK4114 (U10) external 7-4-2-1. Connection connector digital output, connector (PORTB_TX1) available. 7-4-2-2. Setting jumper Setting interface signal PORTA: AK4114 (U7) follows.
JP17 BICKA
JP18 OLRCKA
JP11 ILRCKA
JP12 SDTIA
JP14 JP13 SDTIA1_SEL SDTIA2_SEL
JP15 SDTIA3_SEL
(open)
(open)
(open)
(open)
(GND)
(GND)
(GND)
Figure JP17 (BICKA), JP18 (OLRCKA), JP11 (ILRCKA), JP12 (SDTIA), JP13 (SDTIA1_SEL), JP14 (SDTIA2_SEL), JP15 (SDTIA3_SEL) Setting interface signal PORTB: AK4114 (U10) follows.
JP23 BICKB
JP24 LRCKB
JP21 SDTIB_SEL
(short)
(short)
(GND)
Figure JP23 (BICKB), JP24 (LRCKB), JP21 (SDTIB_SEL) When master clock AK4683: MCKO supplied PORTB: AK4114 (U10): XTI, setting master clock follows.
JP20 XTIB
(short) Figure JP20 (XTIB)
7-4-2-3. Setting switch (PORTB_DIR): 5pin (CM1) OFF. (PORTB_DIR): 4pin (CM0) 7-4-2-4. Setting toggle switch (DIR PORTA) OFF. (DIR PORTB) (PDN) OFFON.
<KM077504>
2005/08
[AKD4683-A]
7-5. Internal loop back (Analog input Analog output) 7-5-1. Connection connector analog input, connector (LIN1)/ (RIN1), (LIN2)/ (RIN2), (LIN3)/ (RIN3), (LIN4)/ (RIN4), (LIN5)/ (RIN5), (LIN6)/ (RIN6) available. analog output, connector (LOUT1)/ (ROUT1), (LOUT2)/ (ROUT2) available. 7-5-2. Setting jumper Setting interface signal PORTA: AK4114 (U7) follows.
JP17 BICKA
JP18 OLRCKA
JP11 ILRCKA
JP12 SDTIA
JP14 JP13 SDTIA1_SEL SDTIA2_SEL
JP15 SDTIA3_SEL
(open)
(open)
(open)
(open)
(GND)
(GND)
(GND)
Figure JP17 (BICKA), JP18 (OLRCKA), JP11 (ILRCKA), JP12 (SDTIA), JP13 (SDTIA1_SEL), JP14 (SDTIA2_SEL), JP15 (SDTIA3_SEL) Setting interface signal PORTB: AK4114 (U10) follows.
JP23 BICKB
JP24 LRCKB
JP21 SDTIB_SEL
(open)
(open)
(GND)
Figure JP23 (BICKB), JP24 (LRCKB), JP21 (SDTIB_SEL) 7-5-3. Setting switch (PORTA_DIR/4683) (PORTB_DIR) "Don't care". 7-5-4. Setting toggle switch (DIR PORTA) OFF. (DIR PORTB) OFF. (PDN) OFFON.
<KM077504>
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[AKD4683-A]
7-6. Headphone output 7-6-1. Connection connector headphone output, connector (HPL) (HPR) stereo mini jack (HP) available. 7-6-2. Setting jumper (HPL) (HPR) control headphone output (RCA connector stereo mini jack J20).
(RCA)
(HP)<Default>
(RCA)
(HP)<Default>
Figure (HPL), (HPR) 7-6-3. Setting switch case evaluation mode using external DIR, settings switches: (PORTA_DIR/4683) (PORTB_DIR) should done following setting evaluation mode. case evaluation mode using internal DIR, settings switches: (PORTA_DIR/4683) (PORTB_DIR) "Don't care". 7-6-4. Setting toggle switch case evaluation mode using external DIR, settings toggle switches: (DIR PORTA) (DIR PORTB) should done following setting evaluation mode. case evaluation mode using internal DIR, settings toggle switches: (DIR PORTA) (DIR PORTB) OFF. (PDN) OFFON.
<KM077504>
2005/08
[AKD4683-A]
Power
8-1. Toggle switch Switch power down reset AK4589. Power down reset AK4589 will done setting (PDN) once, after power Keep during operation AK4589. [SW3] (DIR PORTA): Switch power down reset PORTA: AK4114 (U7). Power down reset PORTA: AK4114 (U7) will done setting (DIR PORTA) once, after power Keep during operation PORTA: AK4114 (U7) [SW5] (DIR PORTB): Switch power down reset PORTB: AK4114 (U10). Power down reset PORTB: AK4114 (U10) will done setting (DIR PORTB) once, after power Keep during operation PORTB: AK4114 (U10). 8-2. [LE1] (INT): output AK4683: INT. turns when output AK4683: "H". [LED1] (ERF): output PORTA: AK4114 (U7): INT0. turns when output PORTA: AK4114 (U7): INT0 "H". [LED2] (ERF): output PORTB: AK4114 (U10): INT0. turns when output PORTB: AK4114 (U10): INT0 "H". 8-3. Reset after power AK4683, PORTA: AK4114 (U7), PORTB: AK4114 (U10) should reset setting (PDN), (DIR PORTA), (DIR PORTB) once, after power [SW1] (PDN):
<KM077504>
2005/08
[AKD4683-A]
Analog Input Circuit
LIN1 LIN1
LIN2
LIN2
MR-552LS AVSS1 RIN1 RIN1
MR-552LS AVSS1 RIN2 RIN2
MR-552LS AVSS1 AVSS1
MR-552LS
LIN3
LIN3
LIN4
LIN4
MR-552LS AVSS1 RIN3 RIN3
MR-552LS AVSS1 RIN4
RIN4
MR-552LS AVSS1 AVSS1
MR-552LS
LIN5
LIN5
LIN6
LIN6
MR-552LS AVSS1 RIN5 AVSS1
MR-552LS AVSS1
RIN5 RIN6
RIN6
MR-552LS AVSS1
MR-552LS
Figure Analog Input Circuit analog input, connector: (LIN1)/ (RIN1), (LIN2)/ (RIN2), (LIN3)/ (RIN3), (LIN4)/ (RIN4), (LIN5)/ (RIN5), (LIN6)/ (RIN6) available use. Analog inputs single-ended input ranges each channel nominally 6.1Vpp@5V. Input range: proportional AVDD1 (AIN=1.22 AVDD1=1.22 5=6.1).
<KM077504>
2005/08
[AKD4683-A]
Analog Output Circuit
P12V
LOUT1 HVSS
NJM5532
LOUT1
N12V 330p HVSS 4.7K 4.7k
MR-552LS
HVSS
ROUT1 HVSS
P12V N12V 330p HVSS 4.7K 4.7k NJM5532
ROUT1
MR-552LS
HVSS LOUT2 P12V
NJM5532
LOUT2
HVSS
N12V 330p HVSS 4.7K 4.7k
MR-552LS
HVSS P12V +22u ROUT2 HVSS NJM5532
ROUT2
N12V 330p HVSS 4.7K 4.7k
MR-552LS
HVSS
Figure Analog Output Circuit
analog output, connector: (LOUT1)/ (ROUT1), (LOUT2)/ (ROUT2) available use. Analog outputs single-ended output ranges each channel nominally 3.0Vpp@5V. Output range: AOUT proportional AVDD2 (AOUT=0.6 AVDD2=0.6 5=3.0).
<KM077504>
2005/08
[AKD4683-A]
Digital Input Circuit (Internal DIR)
RX0/1/2/3 PORT3
0.1u
TORX176
PVSS
PVSS 0.1u
MR-552LS PVSS
PVSS
PVSS
PVSS
Figure Digital Input Circuit (Internal DIR)
case input through RX0, optical connector PORT3 (TORX176) connector (RX0) available. case input through RX1, RX3, only optical connector PORT3 available. case input through RX0, (RX0) controls digital input (optical connector PORT3 connector J14). case input through RX1, RX3, jumpers (RX1), (RX2) (RX3) control digital input channels (RX1, RX3) from PORT3. About only input channels, some jumpers (RX1), (RX2) (RX3) OPT. About no-input channels, other jumpers (RX1), (RX2) (RX3) GND. Digital input: RX0, RX1, available select overwriting IPS10 control register (Addr=03H) AK4683: DIR/DIT part control software.
Digital Input Circuit (External DIR: PORT
PORTA_RX0
DGND2 0.1u
MR-552LS DGND2
Figure Digital Input Circuit (External DIR: PORT digital input, connector: (PORTA_RX0) available.
Digital Input Circuit (External DIR: PORT
PORTB_RX0
DGND1 0.1u
MR-552LS DGND1
Figure Digital Input Circuit (External DIR: PORT
digital input, connector: (PORTB_RX0) available.
<KM077504>
2005/08
[AKD4683-A]
Digital Output Circuit (Internal DIT)
PORT1
0.1u DVSS
TOTX176 DVSS
DA02 MR-552LS DVSS
DVSS
Figure Digital Output Circuit (Internal DIT) digital output, optical connector PORT1 (TOTX176) connector (TX1) available. (TX1) controls digital output (optical connector PORT1 connector J13).
Digital Output Circuit (External DIT: PORT
PORTA_TX1
DA02
MR-552LS
DGND2
DGND2
Figure Digital Output Circuit (External DIT: PORT digital output, connector: (PORTA_TX1) available.
Digital Output Circuit (External DIT: PORT
PORTB_TX1
DA02
MR-552LS
DGND1
DGND1
Figure Digital Output Circuit (External DIT: PORT digital output, connector: (PORTB_TX1) available.
<KM077504>
2005/08
[AKD4683-A]
Headphone Output Circuit
(short)
HVSS HVSS
100u
MR-552LS
(short)
HVSS
01J0154
100u
MR-552LS HVSS
HVSS
Figure Headphone Output Circuit headphone output, connector (HPL), (HPR) stereo mini jack (HP) available. (HPL) (HPR) control headphone output (RCA connector stereo mini jack J20).
<KM077504>
2005/08
[AKD4683-A]
AKD4683 (DIR/DIT) part Control Program operation manual
Set-up evaluation board control software
(Note) Control software does work Windows Windows 2000/XP needs installation driver. Windows 95/98/ME does need installation driver. Please refer "Installation Manual Control Software Driver device control software", about method installation driver. AK4683 supports standard-mode I2C-bus (max: 100kHz), does support fast-mode I2C-bus system (max: 400kHz).
AKD4683-A according above mentioned setting. Connect printer port (parallel port) PORT1 (up-I/F) AKD4683-A 10-wire flat cable packed with AKD4683-A. Then take care direction 10pin connector 10-pin header. Insert CD-ROM labeled "AKD4683-A Control Program ver. 2.0" into CD-ROM drive. Access CD-ROM drive double-click icon "akd4683-a_dir_dit_2.exe", control program. Then evaluate AK4683 (DIR/DIT) part according follows. (Note) Chip Address DIR/DIT: CAD1, CAD0 0(L), 0(L) fixed. (CAD10=00)
Operation flow
Keep following flow. control program according explanation above. Click Write default button. Then dialog input data evaluate AK4683 (DIR/DIT) part.
Explanation each buttons
[Write default]: Write default data into registers. Default data indicated register registers. letter indicates blue letter indicates "0". Blank part that defined datasheet. [All Read]: Read data registers. Read data indicated register register. letter indicates blue letter indicates "0". Blank part that defined datasheet. [Function1]: dialog write data keyboard operation. [Write]: exists each register corresponding registers. dialog write data each register mouse operation. ON/OFF clicking each bits. Click "OK" button write input data register. Click "Cancel" button don't write input data register. [Read]: exists each register corresponding some registers. Read data from each register. Read data indicated register register. letter indicates blue letter indicates "0". Blank part that defined datasheet.
<KM077504>
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[AKD4683-A]
Explanation each dialog
[Function1 Dialog]: Dialog write data keyboard operation Address Input Box: Input address register which data should written into, figures hexadecimal. Data Input Box: Input data which should written into register, figures hexadecimal. Click "OK" button, write input data into register. Click "Cancel" button, don't write input data into register. [Write Dialog]: Dialog write data mouse operation There dialogs corresponding each register. Click "Write" button corresponding each register dialog. check check box, data becomes "1". not, "0". Click "OK" button, write input data into register. Click "Cancel" button, don't write input data into register.
Indication data
Input data indicated register map. letter indicates blue letter indicates "0". Blank part that defined datasheet.
Attention operation
Input data boxes when have "Function1 dialog". "attention dialog" indicated input data address that specified datasheet click "OK" button before input data. that case dialog input data once more again. These operations does need click "Cancel" button check check box.
<KM077504>
2005/08
[AKD4683-A]
AK4683 (ADC/DAC) part Control Program Operation Manual
Set-up evaluation board control software
(Note) Control software does work Windows Windows 2000/XP needs installation driver. Windows 95/98/ME does need installation driver. Please refer "Installation Manual Control Software Driver device control software", about method installation driver. AK4683 supports standard-mode I2C-bus (max: 100kHz), does support fast-mode I2C-bus system (max: 400kHz).
AKD4683-A according above mentioned setting. Connect printer port (parallel port) PORT1 (up-I/F) AKD4683-A 10-wire flat cable packed with AKD4683-A. Then take care direction 10pin connector 10-pin header. Insert CD-ROM-disk labeled "AKD4683-A Control Program ver. 2.0" into CD-ROM-disk drive. Access CD-ROM-disk drive double-click icon "akd4683-a_adc_dac_2.exe" control program. Then evaluate AK4683 (ADC/DAC) part according followings. (Note) Chip Address ADC/DAC: CAD1, CAD0 1(H), 0(L) fixed, (CAD10=10) Register ADC/DAC part "write only", cannot read.
Operation flow
Keep following flow. control program according explanation above Click Write default button. Then dialog input data evaluate AK4683 (ADC/DAC) part.
Explanation each buttons
[Write default]: Write default data into register. Default data indicated register registers. letter indicates blue letter indicates "0". Blank part that defined datasheet. [Function1]: dialog write data keyboard operation. [Function2]: dialog write data keyboard operation. [Write]: exists corresponding each register. dialog write data each register mouse operation. ON/OFF clicking each bits. Click "OK" button write input data into register. Click "Cancel" button don't write input data into register.
<KM077504>
2005/08
[AKD4683-A]
Explanation each dialog
[Function1 Dialog]: Dialog write data keyboard operation Address Input Box: Input address register which data should written into, figures hexadecimal. Data Input Box: Input data which should written into register, figures hexadecimal. Click "OK" button, write input data into register. Click "Cancel" button, don't write input data into register. [Function2 Dialog]: Dialog evaluate LIN/RIN/LOUT1/ROUT1/LOUT2/ROUT2 Volume Control. This dialog corresponds addr:0CH, 0DH, 0EH, 0FH, 10H, 11H. Address Input Box: Input address register which data should written into, figures hexadecimal. Start Data Input Box: Input first data (start data) which should written into register, figures hexadecimal. Data Input Box: Input last data (end data) which should written into register, figures hexadecimal. Interval Input Box: Input time distance (interval time) between write write when data written into register, decimal. Unit time Step Input Box: Input value distance (step data) between data data when data written into register, decimal. Mode Select Check Box: Select mode data flow, "Data returns start data after data reached data." "Data flow when data reached data." mode data flow checked into this check box. When checked into this: Data returns start data after data reached data. When check into this: Data flow when data reached data. [Example when checked into this] Start Data Data Data flow: [Example when check into this] Start Data Data Data flow: Click "OK" button, write input data into register. Click "Cancel" button, don't write input data into register. [Write Dialog]: Dialog write data mouse operation There dialogs corresponding each register. Click "Write" button corresponding each register dialog. check check box, data becomes "1". not, "0". Click "OK" button, write input data into register. Click "Cancel" button, don't write input data into register.
Indication data
Input data indicated register map. letter indicates blue letter indicates "0". Blank part that defined datasheet.
Attention operation
Input data boxes when have "Function1 dialog" "Function2 dialog". "attention dialog" indicated input data address that specified datasheet click "OK" button before input data. that case dialog input data once more again. These operations does need click "Cancel" button check check box.
<KM077504>
2005/08
[AKD4683-A]
Measure Result
part [Measurement condition] Measurement unit Audio Precision System Cascade (AP2) MCLK 256fs (fs=48kHz), 256fs (fs=96kHz) BICK 64fs 48kHz, 96kHz 20Hz20kHz (fs=48kHz), 20Hz40kHz (fs=96kHz) 24bit Power Supply AVDD=PVDD=DVDD=5V, TVDD=3.3V Interface Internal (fs=48kHz, 96kHz) Temperature Room Temp fs=48kHz Parameter S/(N+D) fs=96kHz Parameter S/(N+D)
Input signal 1kHz, -0.5dB 1kHz, -60dB 1kHz, -60dB signal signal
Measurement filter 20kLPF 20kLPF 20kLPF, A-weighted 20kLPF 20kLPF, A-weighted
Results 93.1 97.1 100.6 98.2 101.1
Input signal 1kHz, -0.5dB 1kHz, -60dB 1kHz, -60dB signal signal
Measurement filter fs/2 fs/2 20kLPF, A-weighted fs/2 20kLPF, A-weighted
Results 92.0 96.3 102.7 96.3 102.9
<KM077504>
2005/08
[AKD4683-A]
part [Measurement condition] Measurement unit Audio Precision System Cascade (AP2) MCLK 256fs (fs=48kHz, 96kHz), 128fs (fs=192kHz) BICK 64fs 48kHz, 96kHz, 192kHz 20Hz20kHz (fs=48kHz), 20Hz40kHz (fs=96kHz), 20Hz40kHz (fs=192kHz) Resolution 24bit Power Supply AVDD=PVDD=DVDD=5V, TVDD=3.3V Interface Internal (48kHz, 96kHz, 192kHz) Temperature Room Temp fs=48kHz Parameter S/(N+D) fs=96kHz Parameter S/(N+D) fs=192kHz Parameter S/(N+D)
Input signal 1kHz, 1kHz, -60dB 1kHz, -60dB data data
Measurement filter 20kLPF 20kLPF 22kLPF, A-weighted 20kLPF 22kLPF, A-weighted
Results 94.3 105.0 105.6 103.4 106.0
Input signal 1kHz, 1kHz, -60dB 1kHz, -60dB data data
Measurement filter 40kLPF 40kLPF 22kLPF, A-weighted 40kLPF 22kLPF, A-weighted
Results 92.3 102.0 105.6 101.0 106.2
Input signal 1kHz, 1kHz, -60dB 1kHz, -60dB data data
Measurement filter 40kLPF 40kLPF 22kLPF, A-weighted 40kLPF 22kLPF, A-weighted
Results 88.8 102.5 106.2 101.3 106.2
<KM077504>
2005/08
[AKD4683-A]
Plots
[Measurement condition] Measurement Unit MCLK BICK Resolution Power Supply Interface Temperatur
Audio Precision System Cascade 256fs(fs=48kHz), 256fs(fs=96kHz) 64fs 48kHz, 96kHz 20Hz20kHz (fs=48kHz), 40Hz40kHz (fs=96kHz) 24bit AVDD=PVDD=DVDD=5V, TVDD=3.3V Internal (fs=48kHz, 96kHz) Room Temp
fs=48kHz Figure (Input Frequency =1kHz, Input Level =-0.5dBFS) Figure (Input Frequency =1kHz, Input Level =-60dBFS) Figure (noise floor) Figure THD+N Input Level (Input Frequency =1kHz) Figure THD+N Input Frequency (Input Level=-0.5dBFS) Figure Linearity (Input Frequency =1kHz) Figure Frequency Response (Input Level=-0.5dBFS) Figure Cross-talk (Input Level=-0.5dBFS) fs=96kHz Figure (Input Frequency =1kHz, Input Level =-0.5dBFS) Figure (Input Frequency =1kHz, Input Level =-60dBFS) Figure (noise floor) Figure THD+N Input Level (Input Frequency =1kHz) Figure THD+N (Input Level=-0.5dBFS) Figure Linearity (Input Frequency =1kHz) Figure Frequency Response (Input Level=-0.5dBFS) Figure Cross-talk (Input Level=-0.5dBFS) point=16384, Avg=8, Window=Equirriple
<KM077504>
2005/08
[AKD4683-A]
[Measurement Condition] Measurement Unit MCLK BICK Resolution Power Supply Interface Temperature
Audio Precision System Cascade 256fs(fs=48kHz, 96kHz), 128fs(fs=192kHz) 64fs 48kHz, 96kHz, 192kHz 20Hz20kHz (fs=48kHz), 40Hz40kHz (fs=96kHz), 40Hz80kHz (fs=192kHz) 24bit AVDD=PVDD=DVDD=5V, TVDD=3.3V Internal (48kHz, 96kHz, 192kHz) Room Temp
fs=48kHz Figure (Input Frequency =1kHz, Input Level =0dBFS) Figure (Input Frequency =1kHz, Input Level =-60dBFS) Figure (noise floor) Figure (out-of-band noise) Figure THD+N Input Level (Input Frequency =1kHz) Figure THD+N Input Frequency (Input Level=0dBFS) Figure Linearity (Input Frequency =1kHz) Figure Frequency Response (Input Level=0dBFS) Figure Cross-talk (Input Level=0dBFS) fs=96kHz Figure (Input Frequency =1kHz, Input Level =0dBFS) Figure (Input Frequency =1kHz, Input Level =-60dBFS) Figure (noise floor) Figure (out-of-band noise) Figure THD+N Input Level (Input Frequency =1kHz) Figure THD+N (Input Level=0dBFS) Figure Linearity (Input Frequency =1kHz) Figure Frequency Response (Input Level=0dBFS) Figure Cross-talk (Input Level=0dBFS) fs=192kHz Figure (Input Frequency =1kHz, Input Level =0dBFS) Figure (Input Frequency =1kHz, Input Level =-60dBFS) Figure (noise floor) Figure (out-of-band noise) Figure THD+N Input Level (Input Frequency =1kHz) Figure THD+N (Input Level=0dBFS) Figure Linearity (Input Frequency =1kHz) Figure Frequency Response (Input Level=0dBFS) Figure Cross-talk (Input Level=0dBFS) point=16384, Avg=8, Window=Equirriple
<KM077504>
2005/08
[AKD4683-A]
1.ADC (ADC fs=48kHz)
-100 -110 -120 -130 -140 -150 -160
Red=Lch,Blu=Rch
Figure FFT(Input Frequency=1kHz,Input Level=-0.5dBFS)
-100 -110 -120 -130 -140 -150 -160
Red=Lch,Blu=Rch
Figure FFT(Input Frequency=1kHz,Input Level=-60dBFS)
<KM077504>
2005/08
[AKD4683-A]
(ADC fs=48kHz)
-100 -110 -120 -130 -140 -150 -160
Red=Lch,Blu=Rch
Figure FFT(noise floor)
-100 -102 -104 -106 -108 -110 -112 -114 -116 -118 -120 -140 -130 -120 -110 -100
Red=Lch,Blu=Rch
Figure Input Level(Input Frequency=1kHz)
<KM077504>
2005/08
[AKD4683-A]
(ADC fs=48kHz)
-100 -102 -104 -106 -108 -110 -112 -114 -116 -118 -120
Red=Lch,Blu=Rch
Figure Input Frequency (Input Level=-0.5dBFS)
-100 -110 -120 -130 -140 -140
Red=Lch,Blu=Rch
-130
-120
-110
-100
Figure Linearity (Input Frequency=1kHz)
<KM077504>
2005/08
[AKD4683-A]
(ADC fs=48kHz)
-0.05 -0.1 -0.15 -0.2 -0.25 -0.3 -0.35 -0.4 -0.45 -0.5 -0.55 -0.6 -0.65 -0.7 -0.75 -0.8 -0.85 -0.9 -0.95
Red=Lch,Blu=Rch
Figure Frequency Response (Input Level=-0.5dBFS)
-100 -105 -110 -115 -120 -125 -130 -135 -140
Red=Lch,Blu=Rch
Figure Crosstalk (Input Level=-0.5dBFS)
<KM077504>
2005/08
[AKD4683-A]
(ADC fs=96kHz)
-100 -110 -120 -130 -140 -150 -160
Red=Lch,Blu=Rch
Figure FFT(Input Frequency=1kHz,Input Level=-0.5dBFS)
-100 -110 -120 -130 -140 -150 -160
Red=Lch,Blu=Rch
Figure FFT(Input Frequency=1kHz,Input Level=-60dBFS)
<KM077504>
2005/08
[AKD4683-A]
(ADC fs=96kHz)
-100 -110 -120 -130 -140 -150 -160
Red=Lch,Blu=Rch
Figure FFT(Noise floor)
-100 -102 -104 -106 -108 -110 -112 -114 -116 -118 -120 -140 -130 -120 -110 -100
Red=Lch,Blu=Rch
Figure Input Level (Input Frequency=1kHz)
<KM077504>
2005/08
[AKD4683-A]
(ADC fs=96kHz)
-100 -102 -104 -106 -108 -110 -112 -114 -116 -118 -120
Red=Lch,Blu=Rch
Figure Input Frequency (Input Level=-0.5dBFS)
-100 -110 -120 -130 -140 -140
Red=Lch,Blu=Rch
-130
-120
-110
-100
Figure Linearity (Input Frequency=1kHz)
<KM077504>
2005/08
[AKD4683-A]
(ADC fs=96kHz)
-0.05 -0.1 -0.15 -0.2 -0.25 -0.3 -0.35 -0.4 -0.45 -0.5 -0.55 -0.6 -0.65 -0.7 -0.75 -0.8 -0.85 -0.9 -0.95
Red=Lch,Blu=Rch
Figure Frequency Response (Input Level=-0.5dBFS)
-100 -105 -110 -115 -120 -125 -130 -135 -140
Red=Lch,Blu=Rch
Figure Crosstalk (Input Level=-0.5dBFS)
<KM077504>
2005/08
[AKD4683-A]
2.DAC (DAC fs=48kHz)
-100 -110 -120 -130 -140 -150 -160
Red=Lch,Blu=Rch
Figure FFT(Input Frequency=1kHz, Input Level=0dBFS)
-100 -110 -120 -130 -140 -150 -160
Red=Lch,Blu=Rch
Figure FFT(Input Frequency=1kHz, Input Level=-60dBFS)
<KM077504>
2005/08
[AKD4683-A]
(DAC fs=48kHz)
-100 -110 -120 -130 -140 -150 -160
Red=Lch,Blu=Rch
Figure FFT(noise floor)
-100 -110 -120 -130 -140 -150 -160
Red=Lch,Blu=Rch
100k
Figure FFT(out-of-band noise)
<KM077504>
2005/08
[AKD4683-A]
(DAC fs=48kHz)
-100 -102 -104 -106 -108 -110 -112 -114 -116 -118 -120 -140 -130 -120 -110 -100 dBFS
Red=Lch,Blu=Rch
Figure THD+N Input Level (Input Frequency=1kHz)
-100 -102 -104 -106 -108 -110
Red=Lch,Blu=Rch
Figure THD+N Input Frequency (Input Level=0dBFS)
<KM077504>
2005/08
[AKD4683-A]
(DAC fs=48kHz)
-100 -110 -120 -130 -140 -140
Red=Lch,Blu=Rch
-130
-120
-110
-100
dBFS
Figure Linearity (Input Frequency=1kHz)
+0.5 +0.45 +0.4 +0.35 +0.3 +0.25 +0.2 +0.15 +0.1 +0.05 -0.05 -0.1 -0.15 -0.2 -0.25 -0.3 -0.35 -0.4 -0.45 -0.5
Red=Lch,Blu=Rch
Figure Frequency Response (Input Level=0dBFS)
<KM077504>
2005/08
[AKD4683-A]
(DAC fs=48kHz)
-100 -102 -104 -106 -108 -110 -112 -114 -116 -118 -120 -122 -124 -126 -128 -130
Red=Lch,Blu=Rch
Figure Cross-talk (Input Level=0dBFS)
<KM077504>
2005/08
[AKD4683-A]
(DAC fs=96kHz)
-100 -110 -120 -130 -140 -150 -160
Red=Lch,Blu=Rch
Figure FFT(Input Frequency=1kHz, Input Level=0dBFS)
-100 -110 -120 -130 -140 -150 -160
Red=Lch,Blu=Rch
Figure FFT(Input Frequency=1kHz, Input Level=0dBFS,Notch-on)
<KM077504>
2005/08
[AKD4683-A]
(DAC fs=96kHz)
-100 -110 -120 -130 -140 -150 -160
Red=Lch,Blu=Rch
Figure FFT(Input Frequency=1kHz, Input Level=-60dBFS)
-100 -110 -120 -130 -140 -150 -160
Red=Lch,Blu=Rch
Figure FFT(noise floor)
<KM077504>
2005/08
[AKD4683-A]
(DAC fs=96kHz)
-100 -110 -120 -130 -140 -150 -160
Red=Lch,Blue=Rch
100k
Figure (out-of-band noise)
-100 -102 -104 -106 -108 -110 -112 -114 -116 -118 -120 -140 -130 -120 -110 -100
Red=Lch,Blu=Rch
dBFS
Figure THD+N Input Level (Input Frequency=1kHz)
<KM077504>
2005/08
[AKD4683-A]
(DAC fs=96kHz)
-100 -102 -104 -106 -108 -110 -112 -114 -116 -118 -120
Red=Lch,Blu=Rch
Figure THD+N Input Frequency (Input Level=0dBFS)
-100 -110 -120 -130 -140 -140
Red=Lch,Blu=Rch
-130
-120
-110
-100
dBFS
Figure Linearity (Input Frequency=1kHz)
<KM077504>
2005/08
[AKD4683-A]
(DAC fs=96kHz)
+0.1 +0.05 -0.05 -0.1 -0.15 -0.2 -0.25 -0.3 -0.35 -0.4 -0.45 -0.5 -0.55 -0.6 -0.65 -0.7 -0.75 -0.8 -0.85 -0.9 2.5k 7.5k 12.5k 17.5k 22.5k 27.5k 32.5k 37.5k
Red=Lch,Blu=Rch
Figure Frequency Response (Input Level=0dBFS)
-82.5 -87.5 -92.5 -97.5 -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120 -122.5 -125 -127.5 -130
Red=Lch,Blu=Rch
Figure Cross-talk (Input Level=0dBFS)
<KM077504>
2005/08
[AKD4683-A]
(DAC fs=192kHz)
-100 -110 -120 -130 -140 -150 -160
Red=Lch,Blu=Rch
Figure FFT(Input Frequency=1kHz, Input Level=0dBFS)
-100 -110 -120 -130 -140 -150 -160
Red=Lch,Blu=Rch
Figure FFT(Input Frequency=1kHz, Input Level=0dBFS,Notch-on)
<KM077504>
2005/08
[AKD4683-A]
(DAC fs=192kHz)
-100 -110 -120 -130 -140 -150 -160
Red=Lch,Blu=Rch
Figure FFT(Input Frequency=1kHz, Input Level=-60dBFS)
-100 -110 -120 -130 -140 -150 -160
Red=Lch,Blu=Rch
Figure FFT(noise floor)
<KM077504>
2005/08
[AKD4683-A]
(DAC fs=192kHz)
-100 -110 -120 -130 -140 -150 -160 100k
Red=Lch,Blu=Rch
Figure FFT(out-of-band noise)
-100 -102 -104 -106 -108 -110 -112 -114 -116 -118 -120 -140 -130 -120 -110 -100
Red=Lch,Blu=Rch
dBFS
Figure THD+N Input Level (Input Frequency=1kHz)
<KM077504>
2005/08
[AKD4683-A]
(DAC fs=192kHz)
-100 -102 -104 -106 -108 -110 -112 -114 -116 -118 -120
Red=Lch,Blu=Rch
Figure THD+N Input Frequency (Input Level=0dBFS)
-100 -110 -120 -130 -140 -140
Red=Lch,Blu=Rch
-130
-120
-110
-100
dBFS
Figure Linearity (Input Frequency=1kHz)
<KM077504>
2005/08
[AKD4683-A]
(DAC fs=192kHz)
+0.2 -0.2 -0.4 -0.6 -0.8 -1.6 -1.8 -2.2 -2.4 -2.6 -1.2 -1.4
Red=Lch,Blu=Rch
Figure Frequency Response (Input Level=0dBFS)
-100 -105 -110 -115 -120 -125 -130
Red=Lch,Blu=Rch
Figure Cross-talk (Input Level=0dBFS)
<KM077504>
2005/08
[AKD4683-A]
Revision History
Date (YY/MM/DD) 05/03/10 05/04/05 Manual Revision KM077501 KM077502 Board Reason Contents Revision First Edition Circuit Change Board Change: REV.0 REV.1 Resistance Value Change R45: R46: Measurement Device Revision Change: Rev.A Rev.C Result Change Measurement Result Change (ADC part: fs=48KHz, part: fs=48KHz) Plots (ADC part:fs=48KHz,96KHz, part:fs=48KHz,96KHz,192KHz) Measurement Measurement Result Change (DAC part: fs=48KHz, Result Change 96KHz, 192KHz)
05/07/19
KM077503
05/08/03
KM077504
IMPORTANT NOTICE
These products their specifications subject change without notice. Before considering application, consult Asahi Kasei Microsystems Co., Ltd. (AKM) sales office authorized distributor concerning their current status. assumes liability infringement patent, intellectual property, other right application information contained herein. export these products, devices systems containing them, require export license other official approval under regulations country export pertaining customs tariffs, currency exchange, strategic materials. products neither intended authorized critical components safety, life support, other hazard related device system, assumes responsibility relating such use, except with express written consent Representative Director AKM. used here: hazard related device system designed intended life support maintenance safety applications medicine, aerospace, nuclear energy, other fields, which failure function perform reasonably expected result loss life significant injury damage person property. critical component whose failure function perform reasonably expected result, whether directly indirectly, loss safety effectiveness device system containing which must therefore meet very high standards performance reliability. responsibility buyer distributor product distributes, disposes otherwise places product with third party notify that party advance above content conditions, buyer distributor agrees assume responsibility liability hold harmless from claims arising from said product absence such notification.
<KM077504>
2005/08
RIN6
LIN6
RIN5
LIN5
RIN4
LIN4
RIN3
LIN3
RIN2
LIN2
RIN1
LIN1
AVDD1
PVSS
64pin_4
AVSS1
PVSS
0.1u
AVSS1
AVSS1
LIN6
LIN5
LIN4
LIN3
LIN2
LIN1
AVDD1
RIN6
RIN5
RIN4
RIN3
RIN2
PVSS
RIN1
PVDD
0.1u
AVDD2
VCOM
0.1u
VOUT
(short) CDTO (short) LRCKB (short) BICKB (short) SDTOB (short) OLRCKA
AK4683
2.2u
ROUT1
TST1
CDTO
LOUT1
LRCKB
ROUT2
BICKB
LOUT2
SDTOB
MUTET
OLRCKA
(short) ILRCKA (short) BICKA (short) SDTOA
SDTOA SDTIA1 SDTIA2 SDTIA3 MCLK2 MCKO SDTIB DVDD DVSS TVDD CCLK CDTI HVDD BICKA HVSS ILRCKA
0.1u
64pin_1
12.288MHz 0.1u 0.1u
DVSS
DVSS
64pin_2 DVSS MCKO 4683_TVDD DVDD (short) (short)
(short) (short) (short) (short) (short) (short) (short)
MCLK2
CDTI/SDA
CCLK/SCL
SDTIA1
SDTIA2
SDTIA3
SDTIB
MCKI
0.1u
PVDD
64pin_3
RISEL
ROPIN
LOPIN
LISEL
AVSS2
HVSS
HVSS AVDD2
HVSS
ROUT1
LOUT1
ROUT2
LOUT2
HVSS
HVSS
HVSS HVDD
Title Size
Document Number
AKD4683-A
AK4683
Sheet
Date:
Tuesday, April 2005
LIN1
LIN2 MR-552LS
LIN1
LIN2 LIN3
LIN3
MR-552LS
MR-552LS
AVSS1 RIN1
AVSS1 RIN2 MR-552LS
AVSS1 RIN2 RIN3 MR-552LS
RIN1
RIN3
MR-552LS AVSS1
AVSS1
AVSS1
LIN4
LIN5 MR-552LS
LIN4
LIN5 LIN6
LIN6
MR-552LS
MR-552LS AVSS1
AVSS1 RIN4
AVSS1 RIN5 MR-552LS
RIN4
RIN5 RIN6
RIN6
MR-552LS
MR-552LS AVSS1
AVSS1
AVSS1
Title Size Document Number
AK4683-A
LIN/RIN
Sheet
Date:
Tuesday, April 2005
CCLK/SCL CDTI/SDA CDTO DVSS
PORT1
0.1u DVSS
74LS07
TOTX176
PORT2 A1-10PA-2.54DSA
SCL/CCLK SDA/CDTI SDA(ACK)/CDTO
74HCT157 (short) DGND2 MR-552LS
DA02
DVSS
DGND2
uP-I/F
(open)
DVSS RX0/1/2/3 SDA/CDTO DGND2 PORT3
CDTO/CM0=H CM0=L
0.1u
1S1588
TORX176
PVSS
PVSS 0.1u
ATE1D-2M3
0.1u
74HC14
74HC14
MR-552LS DGND2 4683_TVDD U13A
PVSS
4683_TVDD PR4553K
PVSS
PVSS
PVSS
74HC14
DGND
DGND2
DVSS
Title Size Document Number
AKD4683-A
INPUT/OUTPUT
Sheet
Date:
Tuesday, April 2005
LOUT1 HVSS
LOUT1 LOUT2
P12V NJM5532
P12V NJM5532
LOUT2
N12V HVSS
330p HVSS
N12V 330p HVSS
MR-552LS
MR-552LS
4.7K
4.7k
4.7K
4.7k
HVSS HVSS
P12V
ROUT1 HVSS
ROUT1
P12V NJM5532
ROUT2
NJM5532
ROUT2
N12V 330p
MR-552LS HVSS HVSS
N12V 330p
MR-552LS
HVSS 4.7K 4.7k 4.7K 4.7k
HVSS
HVSS
(short) 100u HVSS HVSS
MR-552LS
(short) 100u HVSS
01J0154
MR-552LS HVSS
HVSS
Title Size Document Number
AKD4683-A
LOUT/ROUT
Sheet
Date:
Tuesday, April 2005
DGND2
D3.3V D3.3V D3.3V U14B D3.3V U14A
PORTA_RX0
DGND2 DGND2 0.47u 0.1u
MR-552LS DGND2 DVDD D3.3V PORT A_DIR/4683
0.1u
74HC14
74HC14
0.1u
HSU119
ATE1D-2M3 PORTA
DIF0 DIF1 DIF2 OCKS0 OCKS1
VCOM
AVSS
TEST1
AVDD
INT1
D3.3V
INT0
LED1
IPS0
D3.3V DGND2
74HC04
OCKS0
OCKS0
DIF0 OCKS1
OCKS1
OCKS0 OCKS1
TEST2
DIF1
DGND2
DIF2
AK4114
(open)
JP10 XTIA MCKO
11.2896MHz
(open)
IPS1
DGND2
P/SN DAUX
DGND2 SDTOA MCLK2
XTL0 MCKO2
BICKA OLRCKA
XTL1
BICK
JP12 SDTIA
MCKO1 DVDD COUT UOUT BOUT VOUT DVSS DVSS TVDD LRCK SDTO
JP11 ILRCKA JP13 SDTIA1_SEL JP14 SDTIA2_SEL JP15 SDTIA3_SEL
ILRCKA
SDTIA1
DGND2
0.1u
0.1u
SDTIA2
4114_TVDD PORTA_TX1
DGND2 D3.3V DGND2 MCKO2 MCKO1
JP16 MCLKA_SEL DGND2
MCKO SDTIA1 SDTIA2 SDTIA3
SDTIA3
DA02
JP17 BICKA JP18 OLRCKA
MCLK BICKA OLRCKA SDTOA ILRCKA
MR-552LS
DGND2
PORT PORT4 A1-10PA-2.54DSA DGND2
DGND2
MCKI
JP19 MCLK_SEL MCKI MCLK2
MCKI MCLK2
Title Size Document Number
74VHC04 DVSS
MR-552LS
AKD4683-A
PORT
Sheet
Date:
Tuesday, April 2005
DGND1
D3.3V D3.3V
PORTB_RX0
DGND1 DGND1 0.47u 0.1u
0.1u D3.3V U14C
MR-552LS
DGND1
U14D
D3.3V PORT B_DIR
74HC14
74HC14
0.1u
D3.3V
HSU119
ATE1D-2M3 PORTB
DIF0 DIF1 DIF2 OCKS0 OCKS1
VCOM
AVSS
TEST1
AVDD
INT1
D3.3V
INT0
LED2
D3.3V DGND2
IPS0
74HC04
OCKS0
OCKS0
DIF0 OCKS1
OCKS1
OCKS0 OCKS1
TEST2
DGND1
DIF1
DIF2
AK4114
(open)
JP20 XTIB MCKO
11.2896MHz
(open)
IPS1
DGND1
P/SN DAUX
DGND1 SDTOB
XTL0
MCKO2
MCLK2
XTL1
BICK
BICKB
LRCKB
MCKO1 DVDD COUT UOUT BOUT VOUT DVSS DVSS TVDD LRCK SDTO
JP21 SDTIB_SEL SDTIB DGND1
0.1u
0.1u
4114_TVDD PORTB_TX1
DGND1 D3.3V MCKO2 DGND1 MCKO1
DGND1
JP22 MCLKB_SEL
MCLK BICKB LRCKB SDTOB
PORT5 A1-10PA-2.54DSA
MCKO SDTIB
DGND1
DA02
JP23 BICKB DGND1 JP24 LRCKB
MR-552LS
PORT
DGND1
Title Size Document Number
AKD4683-A
PORT
Sheet
Date:
Tuesday, April 2005
AVDD1 (short) AVSS1
JP25
AVDD1
NJM78M05FA
+12V P12V
-12V N12V HVSS 0.1u (short)
AVDD1_SEL
AVDD1 AVDD2 (short) HVSS AVDD2 DVDD (short) JP28 DVDD AVDD1 DVDD_SEL DVDD (short) PVDD (short) PVSS PVDD PVDD JP30 AVDD1 PVDD_SEL PVSS HVDD JP26 AVDD2 AVDD1 AVDD2_SEL HVDD AVSS1
AVSS1
AVSS1
HVSS
HVSS HVSS
HVSS (short) JP27 HVDD AVDD1 HVDD_SEL
DVSS
(short) DVDD VDD_SEL JP29 DVDD
NJM5532 TA48M033F
N12V C100 0.1u 0.1u
(short) DVSS 4683_TVDD (short) 4114_TVDD (short)
TVDD(4683) JP32 REG2 TVDD_SEL D3.3V (short) DVSS P12V
TVDD(4683)
JP31 DVDD
0.1u
HVSS
C104
NJM5532 C102 0.1u
HVSS U14F
C106
74HC14
U14E
U13F
74HC04(U8) ,74HC14(U14) D3.3V 0.1u 0.1u 4683_TVDD
74LS07
74VHC04
74HC14
74HC14 U13E
74LS07
74HC04
74VHC04
74HC14
74HC14 U13D
DGND2 74HCT157(U2), 74HC14(U4), 74LS07(U3) 0.1u 0.1u 0.1u
74LS07
74HC04
74VHC04
74HC14
74HC14 U13C
74LS07
74HC04
74VHC04
74HC14
74HC14 U13B
74LS07
74HC04 DVSS
74VHC04 DGND2
74HC14 DGND2
74HC14
DGND2
DGND2
DGND2
0.1u
0.1u
(short)
C101 0.1u
C105
74VHC04(U9)
0.1u
C103 0.1u
C107
DVSS
74HC14(U13)
0.1u
DGND2
Title Size Document Number
AKD4683-A
Power Supply
Sheet
Date:
Tuesday, April 2005

AKD4683-A AK4683 Evaluation Board Rev.1 FEATURE AKD4683-A ev

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