AKD4631-VN AK4631-VN Evaluation board Rev.0 GENERAL DESCRIPT
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[AKD4631-VN]
AKD4631-VN
AK4631-VN Evaluation board Rev.0
GENERAL DESCRIPTION AKD4631-VN evaluation board AK4631VN, 16bit mono CODEC with MIC/SPK amplifier. AKD4631-VN evaluate converter converter separately addition loopback mode (A/D D/A). AKD4631-VN also digital audio interface achieve interface with digital audio systems opt-connector. Ordering guide
AKD4631-VN Evaluation board AK4631VN (Cable connecting with printer port IBM-AT, compatible control software packed with this. This control software does support Windows NT.)
FUNCTION DIT/DIR with optical input/output connector external clock input 10pin Header serial control mode
AVDD DVDD SVDD 3.3V Regulator
MIC-Jack
Control Data 10pin Header
BEEP/MIN/MOUT AOUT SPK-Jack
AK4631VN
10pin Header
AK4114
Clock
Figure AKD4631-VN Block Diagram Circuit diagram layout attached this manual.
<KM077301>
2005/01
[AKD4631-VN]
Evaluation Board Manual Operation sequence
power supply lines. 1-1) When AVDD, DVDD, SVDD, supplied from regulator. (AVDD, DVDD, SVDD, jack should open.). "Other jumper pins (page 10)". <default> [REG] [AVDD] [DVDD] [SVDD] [VCC] [AVSS] [AGND] [DGND] (red (orange) (orange) (blue) (orenge) (black) (black) (black) open open open open
3.3V supplied AVDD AK4631-VN from regulator. 3.3V supplied DVDD AK4631-VN from regulator. 3.3V supplied SVDD AK4631-VN from regulator. 3.3V supplied logic block from regulator. analog ground analog ground logic ground
1-2) When AVDD, DVDD, SVDD, supplied from regulator. (AVDD, DVDD, SVDD, jack should junction.) "Other jumper pins (page 10)". [REG] [AVDD] [DVDD] [SVDD] [VCC] [AVSS] [AGND] [DGND] (red) (orange) (orange) (blue) (orenge) (black) (black) (black) "REG" jack should open. 3.6V AVDD AK4631-VN (typ. 3.3V) 3.6V DVDD AK4631-VN (typ. 3.3V) 5.25V SVDD AK4631-VN (typ. 3.3V, 5.0V) 3.6V logic (typ. 3.3V) analog ground analog ground logic ground
Each supply line should distributed from power supply unit. AVDD DVDD must same voltage level. evaluation mode, jumper pins switches. (See followings.) Power AK4631VN AK4114 should reset once bringing SW1, upon power-up.
Evaluation mode
case AK4631VN evaluation using AK4114, necessary correspond audio interface format AK4631VN AK4114. About AK4631VN's audio interface format, refer datasheet AK4631VN. About AK4114's audio interface format, refer Table this manual. Applicable Evaluation Mode Evaluation loop-back mode (A/D D/A) PLL, Master Mode (Default) Evaluation loop-back mode (A/D D/A) PLL, Slave Mode (PLL Reference CLOCK: MCKI pin) Evaluation loop-back mode (A/D D/A) PLL, Slave Mode (PLL Reference CLOCK: BICK pin) Evaluation using AK4114 (opt-connector) EXT, Slave Mode Evaluation using AK4114 (opt-connector) EXT, Slave Mode
<KM077301>
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[AKD4631-VN]
Evaluation loop-back mode (A/D D/A) PLL, Master Mode (Default) jumper pins MCKI clock "MCKPD bit" AK4631-VN should "0". X'tal 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz 27MHz X'tal 11.2896MHz (Default) AKD4631-VN. "No.8 SW3" "H". When external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz 27MHz) through connector (J8: EXT/BICK) supplied, select JP21 (MCLK_SEL) short JP17 (XTE). JP23 (EXT1) should properly selected order much output impedance clock generator.
MCKI JP17 JP18 MKFS
JP21 MCLK_SEL
256fs 512fs 1024fs MCKO
jumper pins BICK clock Output frequency (16fs/32fs/64fs) BICK should "BCKO1-0 bit" AK4631-VN. There necessity JP19.
JP20 BICK
JP27 BICK
JP29 BICK_INV
JP19 BICK_SEL
64fs 32fs 16fs
jumper pins clock
JP22 FCK_SEL
JP28
jumper pins DATA When AK4631VN evaluated loop-back mode (A/D D/A), jumper pins should following.
JP30 SDTI JP26 4631_SDTI
DAC/LOOP
<KM077301>
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[AKD4631-VN]
Evaluation loop-back mode (A/D D/A) PLL, Slave Mode (PLL Reference CLOCK: MCKI pin) jumper pins MCKI clock "MCKPD bit" AK4631VN should "0". X'tal 11.2896MHz (Default) AKD4631-VN. this case, AK4631VN corresponds reference clock 12.2896MHz. this evaluation mode, output clock from MCKO-pin AK4631VN supplied divider (U3: 74VHC4040), BICK clocks generated divider. Then "MCKO bit" AK4631VN should "1". When external clock through connector (J8: EXT/BICK) supplied, select JP21 (MCLK_SEL) short JP17 (XTE). JP23 (EXT1) should properly selected order match output impedance clock generator.
JP17 JP18 MKFS
MCKI
JP21 MCLK_SEL
256fs 512fs 1024fs MCKO
jumper pins BICK clock
JP20 BICK
JP27 BICK
JP29 BICK_INV
JP19 BICK_SEL
64fs 32fs 16fs
jumper pins clock
JP22 FCK_SEL
JP28
jumper pins DATA When AK4631-VN evaluated loop-back mode (A/D D/A), jumper pins should following.
JP30 SDTI JP26 4631_SDTI
DAC/LOOP
<KM077301>
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[AKD4631-VN]
Evaluation loop-back mode (A/D D/A) PLL, Slave Mode (PLL Reference CLOCK: BICK pin) jumper pins MCKI clock "MCKPD bit" AK4631VN should "1". (MCKI) should open. jumper pins BICK clock When external clock through connector (EXT/BICK) supplied, select JP19 (MCLK_SEL) short JP17 (XTE). JP23 (EXT1) should properly selected order match output impedance clock generator.
JP17
JP21 MCLK_SEL
JP20 BICK
JP27 BICK
JP29 BICK_INV
this evaluation mode, selected clock from JP21 (MCLK_SEL) supplied divider (U3: 74VHC4040), BICK clocks generated divider. Input frequency master clock turn "256fs", "512fs", "1024fs" from left.
JP18 MKFS
JP18 MKFS
JP18 MKFS
256fs 512fs 1024fs MCKO
256fs 512fs 1024fs MCKO
256fs 512fs 1024fs MCKO
input frequency BICK turn "16fs", "32fs", "64fs" from left.
JP19 BICK_SEL
JP19 BICK_SEL
JP19 BICK_SEL
64fs 32fs 16fs
64fs 32fs 16fs
64fs 32fs 16fs
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jumper pins clock When external clock through connector (FCK) supplied, select JP22 (FCK_SEL). JP24 (EXT2) should properly selected order match output impedance clock generator.
JP22 FCK_SEL
JP28
jumper pins DATA When AK4631VN evaluated loop-back mode (A/D D/A), jumper pins should following.
JP30 SDTI
JP26 4631_SDTI
DAC/LOOP
<KM077301>
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[AKD4631-VN]
Evaluation using AK4114 (opt-connector) EXT, Slave Mode jumper pins MCKI clock "MCKPD bit" AK4631VN should "0".
MCKI
JP17
JP21 MCLK_SEL
JP18 MKFS
256fs 512fs 1024fs
jumper pins BICK clock
JP20 BICK
JP27 BICK
JP29 BICK_INV
JP19 BICK_SEL
64fs 32fs 16fs
jumper pins clock JP24 (EXT2) should properly selected order match output impedance clock generator.
JP28
JP22 FCK_SEL
jumper pins DATA When converter AK4631-VN evaluated using AK4114, jumper pins should following.
JP30 SDTI
JP26 4631_SDTI
DAC/LOOP
<KM077301>
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[AKD4631-VN]
Evaluation using AK4114 (opt-connector) EXT, Slave Mode jumper pins MCKI clock "MCKPD bit" AK4631-VN should "0".
MCKI
JP17
JP21 MCLK_SEL
JP18 MKFS
256fs 512fs 1024fs
jumper pins BICK clock
JP20 BICK
JP27 BICK
JP29 BICK_INV
JP19 BICK_SEL
64fs 32fs 16fs
jumper pins clock JP24 (EXT2) should properly selected order match output impedance clock generator.
JP28
JP22 FCK_SEL
jumper pins DATA When converter AK4631-VN evaluated using AK4114, jumper pins should following.
JP30 SDTI
JP26 4631_SDTI
DAC/LOOP
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[AKD4631-VN]
Switch
[SW3] (MODE) Mode Setting AK4631-VN AK4114 "H", "L". Name ("H") ("L") DIF0 AK4114 Audio Format Setting DIF1 Table Clock Operation Mode select Table OCKS0 Master Clock Frequency Select Table OCKS1 Master mode Slave mode Note. When AK4631-VN evaluated Master mode, "No.8 SW3" "H". Table Mode Setting AK4631-VN AK4114
Resistor setting AK4631-VN Audio Interface Format
Setting AK4114 Audio Interface Format
DIF1
DIF0
DIF0
DIF1
DIF2
DAUX 24bit, Left justified 24bit, Left justified 24bit,
SDTO 16bit, Right justified 24bit, Left justified 24bit,
Default
Note. When AK4631-VN evaluated using DIR/DIT AK4114, "No.8 SW3" "L". Table Setting AK4114 Audio Interface Format UNLOCK X'tal Clock source SDTO ON(Note) X'tal DAUX Default X'tal DAUX X'tal DAUX Oscillation (Power-up), OFF: STOP (Power-down) Note When X'tal used clock comparison detection (i.e. XTL1,0= "1,1"), X'tal off. Default setting recommended. Table Clock Operation Mode select OCKS1 MCKO1 256fs 512fs MCKO2 256fs 256fs X'tal 256fs 512fs Mode
Default
Table Master Clock Frequency Select (Stereo mode)
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[AKD4631-VN]
Other jumper pins
(GND) OPEN SHORT (AIN) OPEN SHORT Analog ground Digital ground Separated. Common. (The connector "DGND" open.) <Default> Connection between MICOUT AK4631VN. connection. Connection. <Default>
(AVDD_SEL) AVDD AK4631VN AVDD supplied from regulator ("AVDD" jack should open). Default AVDD AVDD supplied from "AVDD jack. (DVDD_SEL) DVDD AK4631VN AVDD DVDD supplied from "AVDD". Default DVDD DVDD supplied from "DVDD jack. JP10 (LVC_SEL) Logic block selected supply line. DVDD Logic block supplied from "DVDD". Default Logic block supplied from "VCC jack. JP11 (VCC_SEL) Logic block selected supply line. Logic supplied from supply line LVC. Default Logic block supplied from "VCC jack. (SVDD_SEL) SVDD AK4631VN SVDD supplied from regulator ("SVDD" jack should open). Default SVDD SVDD supplied from "SVDD jack. (MCKO_SEL) Master Clock Frequency selected clock from MCKO1 MCKO2 AK4114. MCKO1 check from MCKO1 AK4114 provided MCKI AK4631VN. Default MCKO2 check from MCKO2 AK4114 provided MCKI AK4631VN.
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[AKD4631-VN]
function toggle
[SW1] (DIR) Power control AK4114. Keep during normal operation. Keep when AK4114 used. Power control AK4631VN. Keep during normal operation.
[SW2] (PDN)
Indication
[LED1] (ERF): Monitor INT0 AK4114. turns when some error occurred AK4114.
Serial Control
AK4631-VN controlled printer port (parallel port) IBM-AT compatible Connect PORT2 (CTRL) with wire flat cable packed with AKD4631-VN
Connect
CCLK AKD4631-VN CDTI
wire flat cable
10pin Connector
10pin Header
Figure Connect wire flat cable
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[AKD4631-VN]
Analog Input Output Circuits
Input Circuits Input Circuit
MIC-JACK
AVSS
JACK
JP12 MIC_SEL
MR-552LS AVSS
Figure Input Circuit (a-1) Analog signal input connector.
JP12 MIC_SEL
JACK
(a-2) Analog signal input connector.
JP12 MIC_SEL
JACK
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[AKD4631-VN]
Output Circuits AOUT Output Circuit
AOUT
AVSS
AOUT
MR-552LS
AVSS
Figure AOUT Output Circuit
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[AKD4631-VN]
Output Circuit Note. When mini-jack inserted pulled (SPK-JACK) connector, JP13 (SPP_SEL) JP14 (SPN_SEL) should open, "PMSPK bit" AK4631-VN should "0".
JP31 Dynamic SPK-JACK
JP13
SVSS
Dynamic(EXT) Piezo(EXT) Dynamic Dynamic(EXT) Piezo(EXT) Dynamic
SPK1 020S16
SVSS
DIODE ZENER
SPP_SEL JP14
SVSS
DIODE ZENER
SPN_SEL
Figure Output Circuit (b-1) external dynamic speaker evaluated using (SPK-JACK) connector.
JP13 SPP_SEL JP14 SPN_SEL
JP31 Dynamic
Dynamic
Dynamic(EXT)
Piezo(EXT)
Dynamic Dynamic(EXT) Piezo(EXT)
(b-2) external Piezo speaker evaluated using (SPK-JACK) connector.
JP13 SPP_SEL JP14 SPN_SEL
JP31 Dynamic
Dynamic
Dynamic(EXT)
Piezo(EXT)
Dynamic Dynamic(EXT) Piezo(EXT)
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[AKD4631-VN]
(b-3) Analog signal SPP/SPN pins output from "Dynamic Speaker" evaluation (SPK1).
JP13 SPP_SEL JP14 SPN_SEL
JP31 Dynamic
Dynamic
Dynamic(EXT)
Piezo(EXT)
Dynamic Dynamic(EXT) Piezo(EXT)
BEEP/MIN/MOUT Input Output Circuit
BEEP/MIN/MOUT MR-552LS AVSS
JP15 MIN/MOUT
MOUT 0.1u
AVSS
JP16
MOUT BEEP
BEEP
AVSS
BEEP/MIN/MOUT
Figure BEEP/MIN/MOUT Input Output Circuit (3-1) Analog signal input from connector. JP16 JP15 BEEP/MIN/MOUT MIN/MOUT
MOUT BEEP
(3-2) Analog signal MOUT output from connector.
JP15 MIN/MOUT JP16 BEEP/MIN/MOUT MOUT BEEP
<KM077301>
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[AKD4631-VN]
(3-3) Analog signal MOUT input pin. JP16 JP15 BEEP/MIN/MOUT MIN/MOUT
MOUT BEEP
(3-4) Analog signal input BEEP from connector. JP16 JP15 BEEP/MIN/MOUT MIN/MOUT
MOUT BEEP
assumes responsibility trouble when using above circuit examples.
<KM077301>
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[AKD4631-VN]
Control Software Manual Set-up evaluation board control software
AKD4631-VN according previous term. Connect IBM-AT compatible with AKD4631VN 10-line type flat cable (packed with AKD4631-VN). Take care direction 10pin header. (Please install driver CD-ROM when this control software used Windows 2000/XP. Please refer "Installation Manual Control Software Driver device control software". case Windows95/98/ME, this installation needed. This control software does operate Windows NT.) Insert CD-ROM labeled "AK4631VN Evaluation Kit" into CD-ROM drive. Access CD-ROM drive double-click icon "akd4631.exe" control program. Then please evaluate according follows.
Operation flow
Keep following flow. control program according explanation above. Click "Write default" button. Then dialog input data.
Explanation each buttons
[Port Setup] [Write default] [All Write] [Function1] [Function2] [F3] [SAVE] [OPEN] [Write] printer port. Initialize register AK4631-VN. Write registers that currently displayed. Dialog write data keyboard operation. Dialog write data keyboard operation. Dialog sequential writing. Save current register setting. Write saved values register. Dialog write data mouse operation.
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Explanation each dialog
[Function1 Dialog] Dialog write data keyboard operation Address Box: Data Box: Input registers address figures hexadecimal. Input registers data figures hexadecimal.
want write input data AK4631VN, click "OK" button. not, click "Cancel" button. [Function2 Dialog] Dialog evaluate IVOL Address Box: Input registers address figures hexadecimal. Start Data Box: Input starts data figures hexadecimal. Data Box: Input data figures hexadecimal. Interval Box: Data written AK4631VN this interval. Step Box: Data changes this step. Mode Select Box: check this check box, data reaches data, returns start data. [Example] Start Data Data Data flow: check this check box, data reaches data, does return start data. [Example] Start Data Data Data flow: want write input data AK4631VN, click "OK" button. not, click "Cancel" button. [Write Dialog] Dialog write data mouse operation There dialogs corresponding each register. Click "Write" button corresponding each register dialog. check check box, data becomes "1". not, "0". want write input data AK4631VN, click "OK" button. not, click "Cancel" button.
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[AKD4631-VN]
Indication data
Input data indicated register map. letter indicates blue indicates "0". Blank part that defined datasheet.
Attention operation
Function1 Function2 dialog, input data boxes. Attention dialog indicated input data address that specified datasheet click "OK" button before input data. that case dialog input data once more again. These operations does need click "Cancel" button check check box.
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[AKD4631-VN]
MEASUREMENT RESULTS EXAMPLE 1.AK4631 Mode: mode (Slave)
[Measurement condition] Measurement unit: ROHDE SCHWARZ, UPD05 MCKI: 256fs, 512fs BICK: 64fs Bit: 16bit Sampling Frequency: 8kHz 16kHz Measurement Frequency: 3.4kHz (fs=8kHz), 8kHz (fs=16kHz) Power Supply: AVDD=DVDD=3.3V,SVDD=3.3V/5.0V Temperature: Room Input Frequency: 1kHz [Measurement Results] 1.ADC characteristics (MIC Gain +20dB, IPGA=0dB, ALC1 OFF, Result MCKI clock Sampling Frequency S/(N+D) (-1dBFS) D-Range (-60dBFS) characteristics (AOUT) (DAC MCKI clock Sampling Frequency S/(N+D) (0dBFS) D-Range (-60dBFS) 512fs 8kHz 84.6dB 86.1dB 86.1dB 16kHz 84.1dB 85.0dB 85.0dB 8kHz 85.2dB 88.6dB 88.6dB 256fs 16kHz 84.1dB 84.9dB 85.0dB IPGA ADC)
AOUT, DVOL 0dB) Result 512fs 8kHz 89.7dB 93.5dB 94.1dB 16kHz 89.0dB 91.1dB 92.2dB 8kHz 86.0dB 93.7dB 94.5dB 256fs 16kHz 91.9dB 95.3dB 95.3dB
Speaker-Amp characteristics (DAC MOUT S/(N+D) SVDD=3.3V RL=8 SVDD=5.0V RL=50 SVDD=3.3V RL=8 SVDD=5.0V RL=50
SPP/SPN, ALC2=OFF) Result SPKG1-0 "00" (-0.5dBFS) 65.8dB SPKG1-0 "01" (-0.5dBFS) 67.8dB SPKG1-0 "10" (-0.5dBFS) 74.5dB SPKG1-0 "11" (-0.5dBFS) 78.1dB SPKG1-0 "00" 90.2dB SPKG1-0 "01" 90.4dB SPKG1-0 "10" 90.3dB SPKG1-0 "11" 90.4dB
Loop-back (MIC
AOUT) Result
MCKI clock Sampling Frequency S/(N+D) (-1dBFS) D-Range (-60dBFS)
512fs 8kHz 84.4dB 85.9dB 86.0dB 16kHz 84.0dB 84.8dB 84.8dB 8kHz 84.7dB 87.8dB 87.9dB
256fs 16kHz 84.0dB 84.5dB 84.6dB
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[AKD4631-VN]
2.AK4631 Mode: SLAVE mode
[Measurement condition] Measurement unit: ROHDE SCHWARZ, UPD05 Bit: 16bit Sampling Frequency: 8kHz 16kHz Measurement Frequency: 3.4kHz (fs=8kHz), 8kHz (fs=16kHz) Power Supply: AVDD=DVDD=SVDD=3.3V Temperature: Room Input Frequency: 1kHz [Measurement Results] 2-1. Reference clock BICK Loop-back (MIC AOUT) Result Reference clock Sampling Frequency S/(N+D) (-1dBFS) D-Range (-60dBFS) (FCK pin) 8kHz 16kHz 65.1dB 72.2dB 86.3dB 85.0dB 86.4dB 85.0dB 16fs (BICK pin) 8kHz 16kHz 85.0dB 83.6dB 87.8dB 85.0dB 87.9dB 85.0dB
2-2. Reference clock MCKI
Loop-back (MIC AOUT) Result 12.288MHz 8kHz 16kHz 84.5dB 83.4dB 86.3dB 85.1dB 86.6dB 85.2dB
Reference clock Sampling Frequency S/(N+D) (-1dBFS) D-Range (-60dBFS)
3.AK4631 Mode: MASTER mode
[Measurement condition] Measurement unit: ROHDE SCHWARZ, UPD05 MCKI: 12.288 BICK: 16fs Bit: 16bit Sampling Frequency: 8kHz 16kHz Measurement Frequency: 3.4kHz (fs=8kHz), 8kHz (fs=16kHz) Power Supply: AVDD=DVDD=SVDD=3.3V Temperature: Room Input Frequency:1kHz [Measurement Results] Loop-back (MIC AOUT) Result 8kHz 84.4dB 86.1dB 86.4dB
S/(N+D) (-1dBFS) D-Range (-60dBFS)
16kHz 83.9dB 85.3dB 85.3dB
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4.PLOT DATA (EXT Slave mode) 4-1.ADC (MIC ADC) PLOT DATA
Figure THD+N Input Level
Figure THD+N Input Frequency (Input Level -1dBFS) <KM077301> 2005/01
[AKD4631-VN]
Figure Linearity
Figure Frequency Response
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Figure Plot Input level=-1.0dBFS)
Figure Plot Input level=-60.0dBFS
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Figure Plot data input
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4-2. (DAC
AOUT) PLOT DATA
Figure THD+N Input Level
Figure THD+N Input Frequency (Input Level 0dBFS) <KM077301> 2005/01
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Figure Linearity
Figure Frequency Response
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Figure Plot Input level=0dBFS
Figure Plot Input level=-60.0dBFS
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Figure Plot data input
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Revision History
Date 04/01/25 Manual Revision KM077300 Board Revision Reason First Edition Contents
IMPORTANT NOTICE These products their specifications subject change without notice. Before considering application, consult Asahi Kasei Microsystems Co., Ltd. (AKM) sales office authorized distributor concerning their current status. assumes liability infringement patent, intellectual property, other right application information contained herein. export these products, devices systems containing them, require export license other official approval under regulations country export pertaining customs tariffs, currency exchange, strategic materials. products neither intended authorized critical components safety, life support, other hazard related device system, assumes responsibility relating such use, except with express written consent Representative Director AKM. used here: hazard related device system designed intended life support maintenance safety applications medicine, aerospace, nuclear energy, other fields, which failure function perform reasonably expected result loss life significant injury damage person property. critical component whose failure function perform reasonably expected result, whether directly indirectly, loss safety effectiveness device system containing which must therefore meet very high standards performance reliability. responsibility buyer distributor product distributes, disposes otherwise places product with third party notify that party advance above content conditions, buyer distributor agrees assume responsibility liability hold harmless from claims arising from said product absence such notification.
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REG_IN TA48033F
AVSS 0.1u AVSS SVSS 32pin_4
MOUT
AOUT
BEEP
T45_R
AVDD T45_O
DVDD T45_O
AVSS T45_BK
SVDD T45_BU
SVSS T45_BK
DGND T45_BK
0.1u
TP27 TP26 TP25 BEEP AOUT MOUT
AVSS 2.2k 0.22u
REG_IN
AVDD
DVDD
AVSS
SVDD
SVSS
TP31 TP30 TP29 MICOUT
TP28
TP32 VCOM
AVDD
MICOUT
BEEP
AOUT
AVDD_SEL AVDD
AVSS
MOUT
AVSS
2.2u
0.1u 0.1u
TP24
SVSS SVDD
(short)
AVDD AVSS
AVDD 4.7n AVSS
VCOC
AVDD VCOC CCLK DVDD SDTO DVSS CDTI BICK SDTI
0.1u (short)
AK4631VN
MCKO MCKI
AVSS
(short)
(open)
4631_MCKO 4631_MCKI SVSS
TP21 TP19 MCKO
32pin_1
MCKI MCKI TP18
AVSS 32pin_3
0.1u
AVDD AVDD DVDD_SEL
TP10 TP11 CCLK CDTI
TP12 SDTI
TP13 TP14 SDTO
TP15 BICK
DVDD
R1410 DVDD
TP16 DVDD
AVSS
(short)
DVDD
(short)
DVDD
JP10 LVC_SEL
AVSS VCC(3.3V)
JP11 VCC_SEL
D3.3V
32pin_2
(short)
4631_SDTO
4631_BICK
4631_SDTI
4631_FCK
CCLK
DVDD
CDTI
VCOM AVSS
TP23 SVSS
SVSS TP22 SVDD
SVDD_SEL SVSS SVDD
SVDD
TP20
(short)
Title Size Document Number
AKD4631-VN
AK4631-VN
Date:
Wednesday, December 2004 Sheet
MIC-JACK
JP31 Dynamic SPK-JACK
AVSS
JACK
JP12 MIC_SEL
SVSS
JP13
MR-552LS AVSS
Dynamic(EXT) Piezo(EXT) Dynamic Dynamic(EXT) Piezo(EXT) Dynamic
SPK1 020S16
SVSS MOUT 0.1u SVSS
DIODE ZENER
SPN_SEL JP14
BEEP/MIN/MOUT MR-552LS
JP15 MIN/MOUT
AVSS
DIODE ZENER
SPP_SEL
AVSS
JP16 MOUT BEEP BEEP/MIN/MOUT BEEP
AVSS
AOUT
AVSS
AOUT
MR-552LS
AVSS
Title Size Document Number
AKD4631-VN
Input/Output
Date:
Wednesday, December 2004 Sheet
D3.3V 12.288MHz
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
74HCU04 JP17
74HCU04
EXT_MCLK
JP18 MKFS
74AC74
74AC74
DIR_MCLK
JP21
short
256fs 512fs 1024fs MCKO
64fs 32fs 16fs
JP19 BICK_SEL
JP20 BICK EXT_BICK
MCLK_SEL
74HC14 JP22
74VHC4040 MCKO
EXT_FCK FCK_SEL
EXT/BICK
MR-552LS AVSS
JP23 EXT1
MR-552LS AVSS
JP24 EXT2
Title Size Document Number
AKD4631-VN
CLOCK
Sheet
Date:
Wednesday, December 2004
0.1u 0.1u D3.3V
D3.3V (short)
PORT1
0.1u
0.1u
0.1u
TORX141
D3.3V
74HC14
74HC14
HSU119
0.47u
DIF0 DIF1 DIF2 OCKS0 OCKS1
AVSS
VCOM
TEST1
AVDD
INT1
INT0
LED1
IPS0
D3.3V
74HC04
OCKS0
OCKS0
DIF0 OCKS1
OCKS1
OCKS0 OCKS1
TEST2
DIF1
DIF2
AK4114
11.2896MHz
IPS1
P/SN
DAUX
DAUX
XTL0
MCKO2
XTL1
BICK
DIR_BICK
MCKO1 COUT UOUT DVDD BOUT VOUT TVDD DVSS DVSS LRCK
SDTO
DIR_SDTI
0.1u
0.1u
DIR_FCK
JP25 MCKO_SEL MCKO2 MCKO1 DIR_MCLK
D3.3V PORT2
D3.3V
D3.3V 0.1u
Title Size Document Number
TOTX141
AKD4631-VN
DIR/DIT
Date:
Wednesday, December 2004 Sheet
0.1u
MCKO
4631_MCKO
4631_MCKI
EXT_MCLK
DAUX
4631_SDTO JP26 4631_SDTI DAC/LOOP
4631_SDTI
JP27 BICK
EXT_BICK DIR_BICK
4631_BICK
0.1u
4631_FCK
JP28
EXT_FCK DIR_FCK
74LVC541
74LVC245
U10A
JP29 BICK_INV
74HC14
CCLK CDTI
4631_MCKI MCLK BICK SDTI
PORT3
PORT4
CCLK CDTI
CTRL
74HC541
DAUX
HSU119
JP30 SDTI
DIR_SDTI
74HC14
74HC14
U10B
74HCU04 0.1u
74HCU04
74HC04
74HC14 U10C
U10E
74HCU04
74HC04
74HC04
74HC14 U10D
74HC14 U10F
Title Size Document Number
74HCU04
74HC04
74HC04
74HC14
74HC14
AKD4631-VN
LOGIC
Date:
Wednesday, December 2004 Sheet
AKD4631-VNL1 SILK
AKD4631-VNL2 SILK
AKD4631-VN
AKD4631-VNL2
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