AK4101A Quad Outputs 192kHz 24-Bit GENERAL DESCRIPTION AK410

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AK4101A Quad Outputs 192kHz 24-Bit GENERAL DESCRIPTION AK410

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[AK4101A]
AK4101A
Quad Outputs 192kHz 24-Bit
GENERAL DESCRIPTION AK4101A four outputs digital audio transmitter (DIT) which supports data rate 192kHz sample rate operation. AK4101A supports AES3, IEC60958, S/PDIF EIAJ CP1201 interface standards. AK4101A accepts audio data auxiliary information data etc, which then biphase-encoded driven cable. audio serial port supports eight formats. FEATURES
Sampling Rate 192kHz Support AES3, IEC60958, S/PDIF EIAJ CP1201 professional consumer formats Generates CRCC codes parity bits Four on-chip RS422 line drivers 64-byte on-chip buffer memory Channel Status User bits Supports synchronous/asynchronous access Channel Status User bits Supports multiple clock frequencies: 128fs, 256fs, 384fs 512fs Supports Left/Right justified audio formats Easy wire, Serial Host Interface Audio Routing Mode (Transparent Mode) Power supply: 4.75 5.25V level Small Package: 44pin LQFP Temperature range
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[AK4101A]
Block Diagram
TRANS Drivers DIF1 Drivers DIF0 Drivers Drivers CKS0 Drivers Drivers TXP1 TXN1 TXP2 TXN2 TXP3 TXN3 TXP4 TXN4 MCLK CKS1
DIF2
BICK LRCK SDTI1 SDTI2 SDTI3 SDTI4 Audio Serial Interface
Prescaler
Biphase Encoder
CRCC Generator
Register
Host Serial Interface
CDTI
CDTO
CCLK
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[AK4101A]
Ordering Guide
AK4101AVQ +85°C 44pin LQFP (0.8mm pitch)
Layout
TRANS
DIF2
DIF1
MCLK SDTI1 SDTI2 SDTI3 SDTI4 BICK LRCK FS0/CSN
View
DIF0
TXP1 TXN1 TXP2 TXN2 TXP3 TXN3 TXP4 TXN4 CKS1
AK4101AVQ
FS3/CDTO
FS2/CCLK
FS1/CDTI
CKS0
Comparison AK4101 with AK4101A
Function Ambient Temperature CRCC generation FS3-0 pins CRCC generation FS3-0 bits AK4101 70°C Synchronous mode Asynchronous mode Input data reflected CRCC. Input data ignored CRCC. AK4101A 85°C
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[AK4101A]
PIN/FUNCTION
Name Function Power Down Reset (Pull-up Pin) When "L", AK4101A powered-down, TXP/N pins control registers reset default values. Master Clock Input Audio Serial Data Input Audio Serial Data Input (Pull-down Pin) Audio Serial Data Input (Pull-down Pin) Audio Serial Data Input (Pull-down Pin) Power Supply Pin, 4.75V5.25V Ground Pin, Audio Serial Data Clock Input/Output Serial Clock SDTI pins which configured output based DIF2-0 inputs. Input/Output Channel Clock Indicates left right channel, configured output based DIF2-0 inputs. Sampling Frequency Select Synchronous mode (Pull-down Pin) Host Interface Chip Select Asynchronous mode (Pull-down Pin) AK4112B Mode Audio routing mode (Pull-down Pin) Non-AKM receivers mode, AK4112B mode Sampling Frequency Select Synchronous mode (Pull-down Pin) Host Interface Data Input Asynchronous mode (Pull-down Pin) Sampling Frequency Select Synchronous mode (Pull-down Pin) Host Interface Clock Input Asynchronous mode (Pull-down Pin) Sampling Frequency Select Synchronous mode (Pull-down Pin) Host Interface Data Output Asynchronous mode (Pull-down Pin) Channel Status Input Channel Channel Status Input Channel (Pull-down Pin) Channel Status Input Channel (Pull-down Pin) Channel Status Input Channel (Pull-down Pin) Asynchronous/Synchronous Mode Select (Pull-up Pin) Asynchronous mode, Synchronous mode Block Start Input/Output (Pull-down Pin) normal mode, channel status block output first four bytes. audio routing mode, configured input. When "L", goes Normal mode. Clock Mode Select (Pull-up Pin) Ground Pin,
MCLK SDTI1 SDTI2 SDTI3 SDTI4 BICK
LRCK
AKMODE CDTI CCLK CDTO
CKS0
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ASAHI KASEI Name CKS1 TXN4 TXP4 TXN3 TXP3 TXN2 TXP2 TXN1 TXP1 DIF0 DIF1 DIF2 TRANS
[AK4101A] Description Clock Mode Select (Pull-down Pin) Negative Differential Output Channel Positive Differential Output Channel Negative Differential Output Channel Positive Differential Output Channel Power Supply Pin, 4.75V5.25V Ground Pin, Negative Differential Output Channel Positive Differential Output Channel Negative Differential Output Channel Positive Differential Output Channel Audio Serial Interface Select (Pull-down Pin) Power Supply Pin, 4.75V5.25V Audio Serial Interface Select (Pull-down Pin) Audio Serial Interface Select (Pull-down Pin) User Data Input Channel (Pull-down Pin) User Data Input Channel (Pull-down Pin) User Data Input Channel (Pull-down Pin) User Data Input Channel (Pull-down Pin) Validity Input Channel Channel Validity Input Channel Channel (Pull-down Pin) Audio Routing Mode (Transparent Mode) Synchronous mode Normal mode, Audio routing mode (Transparent mode)
Notes: Internal pull-up pull-down resistors connected on-chip. value resistors (typ). input pins except internal pull-down/pull-up pins should left floating.
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[AK4101A]
ABSOLUTE MAXIMUM RATINGS
(VSS=0V; Note Parameter Power Supply Input Current (All pins except supply pins) Input Voltage Ambient Operating Temperature Storage Temperature Notes: voltages with respect ground. Symbol Tstg -0.3 -0.3 VDD+0.3 Units
WARNING: Operation beyond these limits result permanent damage device. Normal operation guaranteed these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=0V; Note Parameter Power Supply Symbol 4.75 5.25 Units
*AKM assumes responsibility usage beyond conditions this datasheet.
CHARACTERISTICS
(Ta=25°C; VDD=4.75~5.25V) Parameter Symbol Units Power Supply Current (fs=108kHz, Note High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (Except TXP/N pins: Iout=-400µA) VDD-1.0 (TXP/N pins: Iout= -8mA) VDD-0.8 Low-Level Output Voltage (Except TXP/N pins: Iout= 400µA) (TXP/N pins: Iout= 8mA) Input Leakage Current Notes: Power supply current (IDD) 4mA(typ)@fs=48kHz 12mA(typ)@fs=192kHz. increases 20mA(typ) channel with professional output driver circuit. 90mA(typ) four channels have professional output driver circuit. 150µA(typ) "L", TRANS other input pins except internal pull-up/pull-down pins held VSS.
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[AK4101A]
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD=4.75~5.25V; CL=20pF) Parameter Symbol Master Clock Timing 3.584 fCLK Frequency Duty Cycle dCLK LRCK Timing Frequency Duty Cycle Slave Mode dLCK Duty Cycle Master Mode Audio Interface Timing Slave Mode BICK Period tBCK BICK Pulse Width tBCKL Pulse Width High tBCKH tLRB LRCK Edge BICK (Note tBLR BICK LRCK Edge (Note tSDH SDTI Hold Time tSDS SDTI Setup Time Master Mode BICK Frequency fBCK BICK Duty dBCK tMBLR BICK LRCK tSDH SDTI Hold Time tSDS SDTI Setup Time Control Interface Timing CCLK Period tCCK CCLK Pulse Width tCCKL Pulse Width High tCCKH CDTI Setup Time tCDS CDTI Hold Time tCDH Time tCSW tCSS CCLK tCSH CCLK tDCD CDTO Delay tCCZ CDTO Hi-Z (Note Power-down Reset Timing Pulse Width tPDW Notes: BICK rising edge must occur same time LRCK edge. CDTO internally connected pull-down resistor. 27.648 Units
64fs
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[AK4101A]
Timing Diagram
1/fCLK tCLKH tCLKL dCLK tCLKH fCLK tCLKL fCLK
MCLK
1/fs
LRCK
tBCK tBCKH tBCKL
BICK
Clock Timing
tBLR tLRB tSDS tSDH
LRCK
BICK
SDTI
Audio Interface Timing (Slave Mode)
LRCK
50%VDD
tMBLR BICK 50%VDD
tSDS
tSDH
SDTI
Audio Interface Timing (Master Mode)
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[AK4101A]
tCSS tCCKL tCCKH CCLK tCDH tCDS
CDTI
CDTO
Hi-Z (with pull-down resistor)
WRITE/READ Command Input Timing
tCSW tCSH
CCLK
CDTI
Hi-Z (with pull-down resistor)
CDTO
WRITE Data Input Timing
CCLK
CDTI
tDCD
CDTO
Hi-Z (with pull-down resistor)
50%VDD
READ Data Output Timing
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tCSW tCSH CCLK
[AK4101A]
CDTI
tCCZ
CDTO
50%VDD
READ Data Output Timing
tPDW
Power-down Reset Timing
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[AK4101A]
OPERATION OVERVIEW General Description
AK4101A monolithic CMOS circuit that biphase-encodes transmits audio data, auxiliary information data according AES3, IEC60958, S/PDIF EIAJ CP1201 interface standards. There four sets stereo channels that transmitted simultaneously. chip accepts audio data auxiliary information data separately, multiplexes biphase-mark encodes data internally, drives directly through transformer transmission line. There modes operation: asynchronous synchronous. section "Asynchronous Mode/ Synchronous Mode".
Initialization
AK4101A takes clock cycles initialize after goes inactive. Also, correct synchronization, MCLK should synchronized with LRCK phase critical.
MCLK LRCK Relationship
correct synchronization, MCLK LRCK should derived from same clock signal either directly through frequency divider) indirectly (for example, through DSP). relationship BICK LRCK fixed should change. MCLK LRCK move such that they shifted (128fs more cycles from their initial conditions, chip will reset internal frame counters. However, control registers initialized. following frequencies supported MCLK. CKS1 CKS0 MCLK 128fs 256fs 384fs 512fs 28k-192kHz 28k-108kHz 28k-54kHz 28k-54kHz
Table MCLK Frequency
Asynchronous Mode/ Synchronous Mode
Asynchronous Mode (software controlled) AK4101A configured asynchronous mode connecting logic "L". this mode 24-bit audio samples accepted through configured audio serial port, channel status user data through serial control host interface (SCI). allows access internal buffer memory control registers which used store channel status user data. 4bytes channel user channel status stored. This data multiplexed with audio data from audio serial port, parity generated, stream biphase-mark encoded driven through RS422 line drivers. CRCC code channel status also generated according professional mode definition AES3 standards. This mode also allows software control mute, reset, audio format selection, clock frequency settings output enables, serial host interface.
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[AK4101A]
Synchronous Mode (hardware controlled) AK4101A when configured synchronous mode accepts audio samples through audio serial port provides dedicated pins control data allows channel status, user data validity bits serially input through port pins. This data multiplexed, parity generated, stream biphase-mark encoded driven through RS422 line driver. four channels have individual channel status user data pins. 2-1. Audio Routing Mode (Transparent Mode) AK4101A configured audio routing mode (transparent mode) TRANS "1". this mode, channel status(C), user data(U) validity(V) bits must pass through unaltered. Block Start(B) signal configured input, allowing transmit block structure slaved block structure receiver. transmitted with current audio sample. audio routing mode, CRCC bytes generated bits pass through unaltered. audio routing mode, FS0/CSN changes definition AKMODE pin. When AK4101A configured directly with AK4112B receiver. When "L", used with other nonAKM receivers. Setting part with TRANS illegal places chip into test mode. TRANS Modes Synchronous/Asynchronous Asynchronous mode Source bits ORed Control Register ORed Control Register ORed Control Register
Audio Routing Normal mode (Test mode) Normal mode Audio routing mode
Synchronous mode
Table Mode setting
U,V)
C(R191)
C(L0)
C(R0)
C(L1)
C(L31)
C(R31) C(L32)
LRCK (except LRCK SDTI R191
Figure Audio routing mode timing (AKMODE "0")
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[AK4101A]
U,V)
C(R191)
C(L0)
C(R0)
C(L1)
C(L31)
C(R31) C(L32)
LRCK SDTI (except SDTI
R190
L191
R191
L191
R191
Figure Audio routing mode timing (AKMODE "1")
Block Start Timing
Normal mode normal mode (TRANS "0"), block start signal output. goes cycle after beginning channel frame each block, stays first frames. Audio routing mode (transparent mode) audio routing mode (transparent mode) (ANS TRANS "1"), block start becomes input. Except mode, block start signal sampled time from first positive BICK edge previous left channel positive BICK edge preceding transition LRCK indicating left channel will result current left channel being taken first frame current block. Figure below.
LRCK (except LRCK BICK (n-1)th channel channel
(n-1)th channel
channel
Figure Block start timing audio routing mode block start signal arriving during "(1)" period will result usage "nth channel first sub-frame block.
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[AK4101A]
Serial Ports
Normal mode normal mode (TRANS "0"), bits captured (either from pins, synchronous mode, control registers, asynchronous mode) frame following audio data. zero indicate audio data suitable conversion. indicates validity Channels indicates validity Channels respectively. Figure Figure Audio routing mode (transparent mode) audio routing mode (transparent mode) (ANS TRANS "1"), bits captured with same sub-frame data which bits correspond. modes except bits captured first, rising edge BICK after LRCK transition. modes (I2S), bits captured second rising edge. Figure Figure
LRCK BICK C,U,V
Channel1
Channel
Channel C,U,V Previous Channel
Figure Normal, modes
LRCK BICK C,U,V
Channel
Channel
Channel Previous Channel
Figure Normal, modes (I2S)
LRCK BICK C,U,V
Channel
Channel
Channel
Channel
Figure Audio routing, modes
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[AK4101A]
LRCK BICK C,U,V
Channel
Channel
Channel
Channel
Figure Audio routing, modes (I2S)
Audio Serial Interface
audio serial interface used input audio data consists pins: Clock (BICK), Word Clock (LRCK) four Data pins (SDTI 1-4). LRCK indicates particular channel, left right. pins synchronous mode control registers asynchronous mode select particular input mode. asynchronous mode, DIF2-0 bits logically ORed with DIF2-0 pins. Audio data format supports 16-24 bits, right justified left justified modes. mode also supported. AK4101A configured master slave modes. Mode DIF2 DIF1 DIF0 SDTI 16bit, Right justified 18bit, Right justified 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, 24bit, Left justified 24bit, Master Slave Slave Slave Slave Slave Slave Slave Master Master LRCK BICK 32fs-128fs 36fs-128fs 40fs-128fs 48fs-128fs 48fs-128fs 50fs-128fs 64fs 64fs
Table Audio Data Format Modes [NOTE; (I): Input, (O): Output]
LRCK(i)
BICK(i)
SDTI(i)
15:MSB, 0:LSB Data Data
Figure Mode Timing
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[AK4101A]
LRCK(i)
BICK(i)
SDTI(i)
17:MSB, 0:LSB Data Data
Figure Mode Timing
LRCK(i)
BICK(i)
SDTI(i)
19:MSB, 0:LSB Data Data
Figure Mode Timing
LRCK(i)
BICK(i)
SDTI(i)
23:MSB, 0:LSB Data Data
Figure Mode Timing
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[AK4101A]
LRCK
BICK
SDTI(i)
23:MSB, 0:LSB Data Data
Figure Mode Timing Mode LRCK, BICK: Input Mode LRCK, BICK: Output
LRCK
BICK
SDTI(i)
23:MSB, 0:LSB Data Data
Figure Mode Timing Mode LRCK, BICK: Input Mode LRCK, BICK: Output
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[AK4101A]
Sampling frequency setting
Bits Channel Status Byte consumer mode FS3-0 pins. Also bits Channel Status Byte bits Channel Status Byte professional mode FS3-0 pins. FS[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Sampling Frequency 44.1kHz Indicated 48kHz 32kHz 22.05kHz Reserved 24kHz Reserved 88.2kHz Reserved 96kHz Reserved 176.4kHz Reserved 192kHz Reserved Byte Bits 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Table Sampling frequency setting (Consumer mode)
FS[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Sampling Frequecny Defined 44.1kHz 48kHz 32kHz Defined Defined Defined Defined vectoring 22.05kHz 88.2kHz 176.4kHz 192kHz 24kHz 96kHz Defined
Byte Bits
Byte Bits 0000 0000 0000 0000 0000 0000 0000 0000 1000 1001 1010 1011 0011 0001 0010 1111
Table Sampling frequency setting (Professional mode)
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[AK4101A]
Data Transmission Format
Data transmitted outputs formatted blocks shown Figure Each block consists frames. frame data contains sub-frames. sub-frame consists bits information. Each data received coded using bi-phase mark encoding binary state symbol. preambles violate bi-phase encoding they differentiated from data. bi-phase encoding, first state input symbol always inverse last state previous data symbol. logic "0", second state symbol same first state. "1", second state opposite first. Figure illustrates sample stream data bits encoded symbol states.
Channel Channel Channel Channel Channel Channel Sub-frame Frame Sub-frame Frame
Frame Figure Block format
Figure biphase-encoded stream sub-frame defined Figure below. Bits sub-frame represent preamble synchronization. There three preambles. block preamble, contained first sub-frame Frame channel preamble, contained first sub-frame other frames. channel preamble, contained second subframes. Table below defines symbol encoding each preambles. Bits 4-27 sub-frame contain audio sample complement format with most significant bit. mode, Bits 4-11 validity flag. This audio sample unreliable. user data bit. Frame contains first user data word. Frame contains last user data word. channel status bit. Again frame contains first word with last frame 191. even parity bits 4-31 sub-frame.
Sync
Audio sample
Figure Sub-frame format
block data contains consecutive frames transmitted state-bit rate times sample frequency, stereophonic audio, left channel data channel while right data channel monophonic audio, channel contains audio data. Preamble Preceding state 11101000 11100010 11100100 Preceding state 00010111 00011101 00011011
Table Sub-frame preamble encoding
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[AK4101A]
Line Drivers
There four RS422 line drivers chip. AES3 specification states that line driver shall have balanced output with internal impedance ohms ±20% also requires balanced output drive capability volts peak-to-peak into load. internal impedance RS422 driver along with series resistors ohms realizes this requirement. consumer use(S/PDIF), specifications require output impedance ohms ±20% driver level 0.5±20% volts peak peak. combination ohms parallel with ohms realizes this requirement. outputs ground resetting device software mute. Connector Figure Professional Output Driver Circuit Figure Consumer Output Driver Circuit Phono Connector 0.1u Transformer 0.1u Transformer
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[AK4101A]
Serial Control Interface
asynchronous mode, four dual function pins become CSN, CCLK, CDTI CDTO, wire microprocessor interface. internal byte control register then read written. contents control register define, part, mode operation AK4101A. Figure illustrates serial data flow associated with read write operations. C1-0 bits chip address. AK4101A looks C1-0 bits "11" before responding incoming data. Read/Write which read operation write operation. register address contained A7-0 bits decoded select particular byte control register. D7-0 bits CDTI control data coming from microprocessor during write operation. D7-0 bits CDTO contents addressed byte from control register requested during read operation. address data bits framed "0". During write operation, each address data sampled rising edge CCLK. During read operation, address bits sampled rising edge CCLK while data CDTO output falling edge CCLK. CCLK maximum frequency MHz.
CCLK
CDTI WRITE CDTO CDTI READ CDTO
Hi-Z (with pull-down resistor)
Hi-Z (with pull-down resistor)
Hi-Z
C1-C0: R/W: A7-A0: D7-D0:
Chip Address (Fixed "11") READ/WRITE (0:READ, 1:WRITE) Don't care Register Address Control Data
Figure Control Timing
AK4101A
CCLK CDTI CDTO
CSN1 CCLK CDTI CDTO CSN2
AK4101A
CCLK CDTI CDTO
Figure Typical connection with Note: External pull-up resistor should attached CDTO pins since CDTO internally connected pull-down resistor.
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[AK4101A]
Register
Addr 06H09H 0AH0DH 0EH11H 12H15H 16H19H 1AH1DH 1EH21H 22H25H 26H29H 2AH2DH 2EH31H 32H35H 36H39H 3AH3DH 3EH41H Register Name Clock/Format Control Validity/fs Control A-channel C-bit buffer Byte A-channel C-bit buffer Byte A-channel C-bit buffer Byte A-channel C-bit buffer Byte B-channel C-bit buffer Byte A-channel U-bit buffer Byte B-channel U-bit buffer Byte A-channel C-bit buffer Byte B-channel C-bit buffer Byte A-channel U-bit buffer Byte B-channel U-bit buffer Byte A-channel C-bit buffer Byte B-channel C-bit buffer Byte A-channel U-bit buffer Byte B-channel U-bit buffer Byte A-channel C-bit buffer Byte B-channel C-bit buffer Byte A-channel U-bit buffer Byte B-channel U-bit buffer Byte Table Register Notes: stereo mode, indicates Left Channel indicates Right Channel. asynchronous mode, DIF2-0 CKS1-0 bits logically "ORed" with DIF2-0 CKS1-0 pins. addresses from FFH, data written. resets registers their default values. CRCE CA15 CA23 CA31 CB31 UA31 UB31 DIF2 CA14 CA22 CA30 DIF1 CA13 CA21 CA29 DIF0 CA12 CA20 CA28 CKS1 CA11 CA19 CA27 CKS0 CA10 CA18 CA26 MUTEN CA17 CA25 RSTN CA16 CA24 CB24 UA24 UB24
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[AK4101A]
Register Definitions
Addr Register Name Clock/Format Control Default CRCE DIF2 DIF1 DIF0 CKS1 CKS0 MUTEN RSTN
RSTN: Timing Reset. Resets internal frame counters. Control registers initialized. "L". normal mode, "H". Normal operation. (Default) MUTEN: Power Down Mute Asynchronous Mode. Power Down Command. Control registers initialized. pins "L". normal mode, "H". Normal operation. (Default) CKS1-0: Master Clock Frequency Select. (See Table Default: "00" (Mode MCLK=128fs) CKS1-0 bits logically ORed with CKS1-0 pins. DIF2-0: Audio Data Format. (See Table Default: "000" (Mode 16bit right justified) DIF2-0 bits logically ORed with DIF2-0 pins. CRCE: CRCC Enable professional mode. CRCC generated. CRCC generated professional mode. consumer mode, CRCC generated. (Default)
Addr
Register Name Validity/fs Control Default
FS3-0: Sampling Frequency Select. (See Table Table Default: "0000" ("44.1kHz" consumer mode; "Not defined" professional mode. V1-4: Validity Flag each channel. Valid (Default) Invalid
Table setting asynchronous mode
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[AK4101A]
Addr
Register Name A-channel C-bit buffer Byte B-channel C-bit buffer Byte A-channel C-bit buffer Byte B-channel C-bit buffer Byte A-channel C-bit buffer Byte B-channel C-bit buffer Byte A-channel C-bit buffer Byte B-channel C-bit buffer Byte Default C0-7: Channel Status Byte Default: "00100000"
Addr
Register Name A-channel C-bit buffer Byte B-channel C-bit buffer Byte A-channel C-bit buffer Byte B-channel C-bit buffer Byte A-channel C-bit buffer Byte B-channel C-bit buffer Byte A-channel C-bit buffer Byte B-channel C-bit buffer Byte Default C8-15: Channel Status Byte Default: "00000000"
CA15 CB15 CA15 CB15 CA15 CB15 CA15 CB15
CA14 CB14 CA14 CB14 CA14 CB14 CA14 CB14
CA13 CB13 CA13 CB13 CA13 CB13 CA13 CB13
CA12 CB12 CA12 CB12 CA12 CB12 CA12 CB12
CA11 CB11 CA11 CB11 CA11 CB11 CA11 CB11
CA10 CB10 CA10 CB10 CA10 CB10 CA10 CB10
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[AK4101A]
Addr
Register Name A-channel C-bit buffer Byte A-channel C-bit buffer Byte A-channel C-bit buffer Byte A-channel C-bit buffer Byte Default
CA23 CA23 CA23 CA23
CA22 CA22 CA22 CA22
CA21 CA21 CA21 CA21
CA20 CA20 CA20 CA20
CA19 CA19 CA19 CA19
CA18 CA18 CA18 CA18
CA17 CA17 CA17 CA17
CA16 CA16 CA16 CA16
CA16-23: Channel Status Byte A-channel Default: "00001000"
Addr
Register Name B-channel C-bit buffer Byte B-channel C-bit buffer Byte B-channel C-bit buffer Byte B-channel C-bit buffer Byte Default
CB23 CB23 CB23 CB23
CB22 CB22 CB22 CB22
CB21 CB21 CB21 CB21
CB20 CB20 CB20 CB20
CB19 CB19 CB19 CB19
CB18 CB18 CB18 CB18
CB17 CB17 CB17 CB17
CB16 CB16 CB16 CB16
CB16-23: Channel Status Byte B-channel Default: "00000100"
Addr
Register Name A-channel C-bit buffer Byte B-channel C-bit buffer Byte A-channel C-bit buffer Byte B-channel C-bit buffer Byte A-channel C-bit buffer Byte B-channel C-bit buffer Byte A-channel C-bit buffer Byte B-channel C-bit buffer Byte Default
CA31 CB31 CA31 CB31 CA31 CB31 CA31 CB31
CA30 CB30 CA30 CB30 CA30 CB30 CA30 CB30
CA29 CB29 CA29 CB29 CA29 CB29 CA29 CB29
CA28 CB28 CA28 CB28 CA28 CB28 CA28 CB28
CA27 CB27 CA27 CB27 CA27 CB27 CA27 CB27
CA26 CB26 CA26 CB26 CA26 CB26 CA26 CB26
CA25 CB25 CA25 CB25 CA25 CB25 CA25 CB25
CA24 CB24 CA24 CB24 CA24 CB24 CA24 CB24
C24-31: Channel Status Byte Default: "01000000"
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[AK4101A]
Addr 0AH0DH 0EH11H 1AH1DH 1EH21H 2AH2DH 2EH31H 3AH3DH 3EH41H
Register Name A-channel U-bit buffer Byte B-channel U-bit buffer Byte A-channel U-bit buffer Byte B-channel U-bit buffer Byte A-channel U-bit buffer Byte B-channel U-bit buffer Byte A-channel U-bit buffer Byte B-channel U-bit buffer Byte Default U0-31: User Data Default:
UA31 UB31 UA31 UB31 UA31 UB31 UA31 UB31
UA24 UB24 UA24 UB24 UA24 UB24 UA24 UB24
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[AK4101A]
Default values control registers
Bits CRCE DIF2-0 CKS1-0 V4-1 FS3-0 MUTEN RSTN Channel Status Byte0 Bit0 Bit1 Bit2 Bit3-5 Bit6-7 Byte1 Bit0-7 Byte2 Bit0-3 Bit4-7 Default 0000 0000
CRCC generated. 16bit, Right justified MCLK=128fs Valid data fs=44.1kHz Normal Operation Normal Operation
Consumer Mode Audio Mode Copyright Emphasis Mode 00000000 General Category Code 0000 Source Number: Don't care 1000 Channel Source channel 0100 Channel Source channel Byte3 Bit0-3 0100 fs=48kHz Bit4-5 Standard Clock Accuracy Bit6-7 User Data zeros Table Default Values Control Register
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[AK4101A]
PACKAGE
44pin LQFP (Unit:
12.80±0.30 1.70max 00.2 10.00
12.80±0.30 10.00
0.80 0.37±0.10
0.17±0.05 0°10°
0.60±0.20 0.15
Package Lead frame material
Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Solder plate free)
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[AK4101A]
MARKING
AK4101AVQ XXXXXXX
indication Date Code: XXXXXXX(7 digits) Marking Code: AK4101AVQ Asahi Kasei Logo
IMPORTANT NOTICE These products their specifications subject change without notice. Before considering application, consult Asahi Kasei Microsystems Co., Ltd. (AKM) sales office authorized distributor concerning their current status. assumes liability infringement patent, intellectual property, other right application information contained herein. export these products, devices systems containing them, require export license other official approval under regulations country export pertaining customs tariffs, currency exchange, strategic materials. products neither intended authorized critical components safety, life support, other hazard related device system, assumes responsibility relating such use, except with express written consent Representative Director AKM. used here: hazard related device system designed intended life support maintenance safety applications medicine, aerospace, nuclear energy, other fields, which failure function perform reasonably expected result loss life significant injury damage person property. critical component whose failure function perform reasonably expected result, whether directly indirectly, loss safety effectiveness device system containing which must therefore meet very high standards performance reliability. responsibility buyer distributor product distributes, disposes otherwise places product with third party notify that party advance above content conditions, buyer distributor agrees assume responsibility liability hold harmless from claims arising from said product absence such notification.
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AK4101A Quad Outputs 192kHz 24-Bit GENERAL DESCRIPTION AK410

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