NTSC/P Digital Video Decoder With Macrovision Detection 2001
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TVP5040
NTSC/P Digital Video Decoder With Macrovision
Detection
2001
MSDS Multimedia
SLAS257D
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Copyright 2001, Texas Instruments Incorporated
Contents
Section Title Page 2-10 2-10 2-12 2-12 2-13 2-13 2-14 2-15 2-17 2-17 2-17 2-19 2-19 2-21 2-22 2-23 Introduction Features Applications Related Products Functional Block Diagram Terminal Assignments Ordering Information Terminal Functions Strapping Terminals Description Functional Description Analog Video Processing Converters 2.1.1 Video Input Selection 2.1.2 Analog Input Clamping Automatic Gain Control Circuits 2.1.3 Converters Digital Processing 2.2.1 Digital Input Selection 2.2.2 Decimation Filter 2.2.3 Separation 2.2.4 Luminance Processing 2.2.5 Chrominance Processing 2.2.6 Clock Circuits Genlock Control Video Output Format 2.4.1 Sampling Frequencies Patterns 2.4.2 Video Port 20-Bit 16-Bit 4:2:2 Output Format Timing 2.4.3 Video Port 10-Bit 8-Bit 4:2:2 ITU-R BT.656 Output Format Timing Synchronization Signals Host Interface Host Interface 2.7.1 Host Port Select 2.7.2 Write Operation 2.7.3 Read Operation 2.7.4 Microcode Write Operation 2.7.5 Microprocessor CLEAR-RESET 2.7.6 Microcode Read Operation
2.10 2.11 2.12 2.13
Host Interface Port 2.8.1 Host Port Terminal Description 2.8.2 Phases 2.8.3 Commands Address Space 2.8.4 Command Byte 2.8.5 Microcode Write Operation (FIFO 2.8.6 Microcode Read Operation (FIFO 2.8.7 Parallel Host Interface 2.8.8 Parallel Host Interface 2.8.9 Parallel Host Interface 2.8.10 Parallel Host Interface Register 2.8.11 Parallel Host Interface Microcode Write Operation 2.8.12 Parallel Host Interface Microcode Read Operation Data Processor 2.9.1 Teletext Data Byte Order 2.9.2 Teletext Ancillary Data Video Stream Video Data Output Reset Initialization Internal Control Registers Register Definitions 2.13.1 Vendor 2.13.2 Device 2.13.3 Subsystem Vendor 2.13.4 Subsystem Device 2.13.5 Power State 2.13.6 Power Support 2.13.7 Revision 2.13.8 Video Input Source Selection 2.13.9 Analog Channel Controls 2.13.10 Operation Mode Controls 2.13.11 Miscellaneous Control 2.13.12 Software Reset 2.13.13 Color Killer Threshold Control 2.13.14 Luminance Processing Control 2.13.15 Luminance Processing Control 2.13.16 Brightness Control 2.13.17 Color Saturation Control 2.13.18 Control 2.13.19 Contrast Control 2.13.20 Outputs Data Rates Select 2.13.21 Luminance Control 2.13.22 Horizontal Sync HSYN Start NTSC/PAL 2.13.23 Vertical Blanking VBLK Start 2.13.24 Vertical Blanking VBLK Stop
2-24 2-24 2-25 2-26 2-27 2-32 2-32 2-33 2-34 2-36 2-37 2-38 2-39 2-39 2-40 2-41 2-42 2-42 2-43 2-46 2-46 2-46 2-47 2-47 2-47 2-48 2-48 2-48 2-49 2-50 2-51 2-52 2-52 2-52 2-53 2-54 2-54 2-54 2-54 2-55 2-56 2-56 2-57 2-57
2.13.25 2.13.26 2.13.27 2.13.28 2.13.29 2.13.30 2.13.31 2.13.32 2.13.33 2.13.34 2.13.35 2.13.36 2.13.37 2.13.38 2.13.39 2.13.40 2.13.41 2.13.42 2.13.43 2.13.44 2.13.45 2.13.46 2.13.47 2.13.48 2.13.49 2.13.50 2.13.51 2.13.52 2.13.53 2.13.54 2.13.55 2.13.56 2.13.57 2.13.58 2.13.59 2.13.60 2.13.61 2.13.62 2.13.63 2.13.64 2.13.65 2.13.66 2.13.67 2.13.68
Chrominance Control Chrominance Control Interrupt Reset Register Interrupt Enable Register Interrupt Configuration Register Video Input Source Selection Lock Speed Select Crystal Frequency Video Standard NonVIP Program Write Microprocessor Reset Clear Major Software Revision Number Status Register Status Register Status Register Status Register Interrupt Status Register Interrupt Active Register Minor Software Revision Number Status Register Vertical Line Count Vertical Line Count Analog Digital NonVIP Program Read Filter Parameters Filter Parameters Error Filtering Enables Transaction Processing Enables Control Register Line Enable Registers Sync Pattern Register Teletext FIFO Closed Caption Data Buffer Status Interrupt Threshold Interrupt Line Number FIFO Control FIFO Test Interrupt Status Register Interrupt Enable Register Interrupt Configuration Register Teletext FIFO Program Write
2-58 2-59 2-59 2-60 2-60 2-61 2-61 2-61 2-62 2-62 2-62 2-63 2-63 2-64 2-64 2-65 2-65 2-65 2-66 2-66 2-66 2-67 2-67 2-67 2-67 2-68 2-69 2-70 2-70 2-71 2-71 2-72 2-72 2-72 2-73 2-73 2-73 2-74 2-74 2-75 2-75 2-76 2-76 2-76
2.13.69 Program Read 2-77 2.13.70 Parallel Host Interface Teletext FIFO 2-77 2.13.71 Parallel Host Interface Status/Interrupt 2-78 Electrical Specifications Absolute Maximum Ratings Recommended Operating Conditions 3.2.1 Crystal Specifications Electrical Characteristics Over Recommended Voltage Temperature Ranges, DVDD AVDD 70°C 3.3.1 Electrical Characteristics 3.3.2 Analog Processing Converters Timing 3.4.1 Clocks, Video Data, Sync Timing 3.4.2 Host Port Timing 3.4.3 Host Port Timing 3.4.4 Parallel Host Interface 3.4.5 Parallel Host Interface 3.4.6 Parallel Host Interface Application Information Microcode Download 4.1.1 Timing Requirement Start Download 4.1.2 General Microcode Download Procedure 4.1.3 Microprocessor Restart Operation 4.1.4 Microcode Data File 4.1.5 Default Values Designing With PowerPAD Mechanical Data
List Illustrations
Figure Title Analog Video Processors Converters Digital Video Signal Processing Block Diagram Digital Input Multiplexer Decimation Filter Frequency Response Separation Block Diagram Color Low-Pass Filter Frequency Response Color Low-Pass Filter With Notch Filter Frequency Response (NTSC PAL-M Square Pixel Sampling) Color Low-Pass Filter With Notch Filter Characteristics (13.5 Sampling) Color Low-Pass Filter With Notch Filter Frequency Response (PAL Square Pixel Sampling) 2-10 3-Line Adaptive Comb Filtering 2-11 Comb Filters Frequency Response 2-12 Chroma Trap Filter Frequency Response (NTSC Square Pixel Sampling) 2-13 Chroma Trap Filter Frequency Response (13.5 Sampling) 2-14 Chroma Trap Filter Frequency Response (PAL Square Pixel Sampling) 2-15 Luminance Edge-Enhancer Peaking Block Diagram 2-16 Peaking Filter Response, NTSC PAL-M Square Pixel Sampling 2-17 Peaking Filter Response, 13.5 Sampling Rate 2-18 Peaking Filter Response, Square Pixel 2-19 Clock Circuit Diagram 2-20 Example Reference Clock Configurations 2-21 GLCO Timing 2-22 4:2:2 Sampling 2-23 20-Bit 4:2:2 Output Format 2-24 20-Bit 4:2:2 Output Format 2-25 Vertical Synchronization Signals 2-26 Horizontal Synchronization Signals 2-27 Data Transfer 2-28 Transfer 2-29 Reading From Registers With Wait States Page 2-10 2-11 2-11 2-12 2-13 2-13 2-14 2-15 2-16 2-18 2-25 2-28
2-30 Writing Registers With Wait States (Burst Write) 2-31 Reading From FIFO With Wait States 2-32 Slave Termination 2-33 Parallel Host Interface Timing 2-34 Parallel Host Interface Timing 2-35 Parallel Host Interface Timing 2-36 Address Register 2-37 Video Input Source Selection Clocks, Video Data, Sync Timing Host Port Timing Host Port Timing Parallel Host Interface Timing Parallel Host Interface Timing Parallel Host Interface Timing TVP5040 Microcode Hex-ASCII Format
2-28 2-29 2-29 2-34 2-35 2-36 2-37 2-48
List Tables
Table Title Summary Line Frequencies, Data Rates, Pixel Counts Host Port Select Host Port Terminal Description Host Port Terminal Description Host Port Phase Description Summary Commands Address Spaces Parallel Host Interface Terminal Description Parallel Host Interface Terminal Description Parallel Host Interface Terminal Description 2-10 NABTS 525/625-Line Ancillary Data Sequence 2-11 Dummy Timing Ancillary Data Sequence 2-12 Ancillary Data 2-13 Reset Sequence 2-14 Registers Summary 2-15 Analog Channel Video Mode Selection 2-16 Digital Output Control 2-17 Vertical Blanking Interval Start 2-18 Chrominance Comb Filter Selection Default Values Page 2-13 2-17 2-17 2-24 2-26 2-26 2-33 2-34 2-36 2-41 2-41 2-42 2-42 2-44 2-49 2-51 2-57 2-58
viii
Introduction
TVP5040 high-quality single-chip digital video decoder that converts base-band analog National Television System Committee (NTSC) phase alternating line (PAL) video into digital component video. Both composite S-video inputs supported. TVP5040 includes 10-bit converters with sampling. Sampling square-pixel ITU-R BT.601 MHz) line-locked correct pixel alignment. output formats 8-bit, 10-bit, 16-bit, 20-bit 4:2:2, 8-bit 10-bit ITU-R BT.656 with embedded synchronization. TVP5040 utilizes Texas Instruments patented technology locking weak, noisy, unstable signals, chroma frequency control output generated synchronizing downstream video encoders. Complementary three-line adaptive (2-H delay) comb filtering available both luma chroma data paths reduce both cross-luma cross-chroma artifacts; chroma trap filter also available. Video characteristics including hue, contrast, saturation programmed using five supported host port interfaces; I2C, three parallel host interface (PHI) modes, VIP. TVP5040 generates synchronization, blanking, field, lock clock signals, addition digital video outputs. TVP5040 includes methods advanced vertical blanking interval (VBI) data retrieval. data processor slices, parses, performs error checking teletext data several formats. built-in FIFO stores lines teletext data, with proper host port synchronization full-screen teletext retrieval possible. data processor also retrieves closed-caption data. TVP5040 also pass through double-sampled composite data host-based software processing. main blocks TVP5040 include: Analog processors converters separation Chrominance processor Luminance processor Clock/timing processor power-down control Output formatter Host port interface data processor Macrovision detection
Features
Accepts NTSC composite video, S-video Four analog video inputs four composite inputs S-video inputs fully differential CMOS analog preprocessing channels with clamping automatic gain control (AGC) best performance Dual high-speed over-sampling 10-bit converters Patented architecture locking weak, noisy, unstable signals Single 14.31818-MHz reference crystal standards Line-locked clock sampling square-pixel 27-MHz rates Programmable output data rates: 12.2727 square-pixel (NTSC) 14.7500 square-pixel (PAL) 13.5 ITU-R BT.601 (NTSC PAL) Optional automatic switching between NTSC standards
Macrovision trademark Macrovision Corporation. Other trademarks property their respective owners.
This device requires microcode downloaded order operate (see Note) Complementary 3-line (2-H delay) adaptive comb filters both cross-luminance cross-chrominance noise reduction Subcarrier genlock output synchronizing color subcarrier external encoder Standard programmable video output formats: 16-bit 4:2:2 YCbCr 20-bit 4:2:2 YCbCr 8-bit 4:2:2 YCbCr 10-bit 4:2:2 YCbCr ITU-R BT.656 8-bit 4:2:2 with embedded syncs ITU-R BT.656 10-bit 4:2:2 with embedded syncs
Advanced programmable video output formats: oversampled data during active video Sliced data ancillary data video stream
Teletext (NABTS, WST) closed-caption decode with FIFO Macrovision copy protection detection Supports ITU-R BT.601 standard Programmable host port options including I2C, three parallel host interface (PHI) modes, Brightness, contrast, saturation, control through host port tolerant digital ports 80-pin TQFP package
Applications
Digital image processing Video conferencing Multimedia Digital video Desktop video Video capture Video editing Intercast teletext applications Security applications
Related Products
TVP5031 NTSC/PAL Digital Video Decoder, Literature Number SLAS267B TVP6000 NTSC/PAL Digital Video Encoder, Literature Number SLAS184 NOTE: obtain device software from site, click development tools link from TVP5040 product page.
Functional Block Diagram
VI_1A VI_1B Channel Luma/Chroma Separation VI_2A VI_2B Channel
Luminance Processing Output Formatter Chrominance Processing
Y[9:0] UV[9:0]
D[7:0] INTREQ
Interface
Interface
Interface Macrovision Detection HSYN VSYN PALI GPCL RSTINB
XTAL1 XTAL2 SCLK PCLK PREF GLCO
Line Chroma PLLs
Sync Processor
Terminal Assignments
TQFP PACKAGE (TOP VIEW)
DGND DVDD DGND DVDD DVDD DGND DVDD INTREQ
GPCL DGND XTAL2 XTAL1 DVDD PALI GLCO HSYN VSYN AVID PCLK PREF SCLK RSTINB RSTOUTB DGND PLL_AGND
Ordering Information
DEVICE: PFP: TVP5040CPFP Plastic flat-pack with PowerPAD
NOTE: PowerPAD package requires special board layout considerations. Please Texas Instruments Literature Number SLMA004 more information.
PowerPAD trademark Texas Instruments.
REFM REFP CH2_AV VI_2A VI_2B CH2_AGND CLAMP2 AFE_GND NSUB AFE_V PLL_AV
CLAMP1 CH1_AGND VI_1B VI_1A CH1_AV
Terminal Functions
TERMINAL NAME Analog Video VI-1A VI-1B VI-2A VI-2B Clock Signals PCLK PREF SCLK XTAL1 XTAL2 Pixel clock output. frequency 12.2727 square-pixel NTSC, 14.75 square-pixel PAL, 13.5 ITU-R.BT.601 sampling modes. Clock phase reference signal. This signal qualifies clock edges when SCLK used clock data that changing pixel clock rate. System clock output with twice frequency pixel clock (PCLK). External clock reference. user connect XTAL1 TTL-compatible oscillator terminal crystal oscillator. user connect XTAL2 other terminal crystal oscillator connect XTAL2 all. single 14.31818-MHz crystal oscillator needed square pixel sampling ITU-R BT.601 sampling. Analog video inputs. four composite inputs S-video inputs combination two. inputs must ac-coupled. recommended coupling DESCRIPTION
Digital Video UV[9:0] 10-bit digital chrominance outputs. These terminals also configured output data from channel converter. vendor modifiable subsystem initialized configuring UV[9:0] terminals with pullup/pulldown resistors. Terminals UV[7:0] used lower byte subsystem terminals UV[9:8] used During reset, UV[9:0] terminals used device configuration registers. 10-bit digital luminance outputs, 10-bit multiplexed luminance chrominance outputs. These terminals also configured output data from channel converter. vendor modifiable subsystem initialized configuring Y[9:0] terminals with pullup/pulldown resistors. Terminals Y[7:0] used upper byte subsystem terminals Y[9:8] used During reset, Y[9:0] terminals used device configuration registers.
Y[9:0]
HOST PORT-Bus A[1:0] mode: address port. mode: During reset A[1:0] terminals input used device configuration registers. A[1:0] used bits subsystem device Pull each terminal during reset will corresponding Leaving terminal undriven pulldown terminal during reset will internal weak pulldown remains after reset. mode: data port-bit [7:0] mode: During reset, D[7:0] terminals input used device configuration registers. D[7:0] used lower byte subsystem device Pull each terminal during reset will corresponding Leaving terminal undriven pulldown terminal during reset will internal weak pulldown remains after reset. mode: Interrupt request (INTREQ) Pullup required configured open drain. mode: Interrupt request (INTREQ) Pullup required configured open drain. mode: Interrupt request (VIRQ) internal weak pulldown. pullup resistor required. mode: port data acknowledgement ready signal (DTACK) mode: Serial clock (SCL) Pullup required. mode: Hardware address (HAD[0]) mode: port read-write write (RW/WR) mode: Serial data (SDA) Pullup required. mode: Hardware address HAD[1] 10-K pullup resistor required. mode: port data strobe read signal (DS/RD) mode: Hardware control (HCTL) 10-K pullup resistor required. mode: port chip select (VC) mode: Slave address select (I2CA) mode: VIPCLK
D[7:0]
INTREQ
Terminal Functions (Continued)
TERMINAL NAME RSTOUTB RSTINB GLCO Miscellaneous Signals Reset output, active Reset input, active Output enable terminals. Output enable also controllable host port. When this terminal logic forces output terminals high impedance states (active low). This serial output carries color information. slave device decode information allow chroma frequency control TVP5040. Data transmitted SCLK rate. Additionally, this terminal, conjunction with PALI FID, used determine host port mode configuration during initial power General-purpose control logic. This terminal three functions: General-purpose output. this mode state GPCL directly programmed host port. Vertical blank output. this mode GPCL terminal used indicate vertical blanking interval output video. beginning times this signal programmable host port control. Sync lock control input. this mode when GPCL high, output clock frequencies sync timing forced nominal values. Clamp voltage outputs. Connect 0.1-µF decoupling capacitor from each terminal analog ground connection Connect 1-µF capacitor from this terminal CH1_AGND CH2_AGND DESCRIPTION
GPCL
CLAMP1, CLAMP2 Power Supplies AFE_VDD AFE_GND CH1_AGND CH2_AGND CH1_AVDD CH2_AVDD DGND PLL_AGND PLL_AVDD DVDD NSUB REFP REFM Sync Signals AVID
Analog supply. Connect 3.3-V analog supply Analog ground Analog grounds Analog supply. Connect 3.3-V analog supply. Digital grounds ground. Connect analog ground. supply. Connect 3.3-V analog supply. Digital supply. Connect Susbstrate ground. Connect analog ground. reference supply. Connect 4.7-µF capacitor from each terminal analog ground. Connect 1-µF capacitor across REFM REFP terminals.
Active video indicator. This signal high during horizontal active time video output terminals. AVID continues toggle during vertical blanking intervals. This terminal placed high-impedance state. During reset, AVID input, used program behavior Y[9:0], UV[9:0], HSYN, VSYN, AVID, immediately after completion reset. AVID pulled during reset, Y[9:0], UV[9:0], HSYN, VSYN, AVID, PALI, actively drive after reset. AVID pulled down during reset, Y[9:0], UV[9:0], HSYN, VSYN, AVID, PALI, remain high-impedance state after reset.
Odd/even field indicator vertical lock indicator. odd/even indicator, logic indicates field. vertical lock indicator, logic indicates internal vertical locked state. Additionally, this terminal conjunction with GLCO PALI used determine host port configuration during initial power reset.
Terminal Functions (Continued)
TERMINAL NAME HSYN PALI Sync Signals (Continued) Horizontal sync signal with respect digital video data output. rising edge time programmable host port. line indicator horizontal lock indicator. line indicator, logic indicates noninverted line, logic indicates inverted line. horizontal lock indicator, logic indicates internal horizontal locked state. This terminal input terminal during reset used conjunction with GLCO select mode host interface. During reset, this terminal pulled pulled down VSYN Vertical sync signal with respect digital video data output. DESCRIPTION
Strapping Terminals Description
following terminals have reset strapping options. states these terminals sampled during reset configure TVP5040 various modes operation. These terminals temporarily turned into inputs with weak internal pulldown (approximately 40-K resistor) during reset return their normal operation after reset. Each following terminals pulled with 10-K resistor corresponding left undriven during reset, relying internal pulldown resistor pull terminal corresponding bit.
TERMINAL NAME UV[7:0] Y[7:0] D[7:0] UV[9:8] Y[9:8] HSYN VSYN A[1:0] AVID PREF PALI GLCO DESCRIPTION Lower byte subsystem vendor (VIP register 004) Upper byte subsystem vendor (VIP register 005) Lower byte subsystem device (VIP register 006) Bits upper byte subsystem device (VIP register 007) Bits upper byte subsystem device (VIP register 007) upper byte subsystem device (VIP register 007) upper byte subsystem device (VIP register 007) Bits upper byte subsystem device (VIP register 007) output enable (bit HSYN, VSYN, AVID, FID, PALI output enable (bit miscellaneous control register Clock enable (bit miscellaneous control (register Host interface mode (see Table 2-2) Host interface mode (see Table 2-2) Host interface mode (see Table 2-2)
Functional Description
Analog Video Processing Converters
Figure shows functional diagram analog video preprocessors converters. This block provides analog interface video inputs. accepts four inputs performs source selection, video clamping, video amplification, analog-to-digital conversion, fine gain offset adjustments center digitized video signal.
TVP5040 ANALOG FRONT
CH1_CLAMP_MODE CH1_MUX_CTRL VI_1A VI_1B CLAMP CH1_GAIN_OFFSET CH1_FINE_ADJUST BITS BITS CH1_OUT
FINE GAIN, OFFSET ADJUST
BANDGAP REFM
BUFFER
CLAMP1
CLAMP BUFFER
CLAMP2
SCLK REFP
VI_2A VI_2B CLAMP CH2_MUX_CTRL CH2_GAIN_OFFSET BITS FINE GAIN, OFFSET ADJUST CH2_OUT BITS
CH2_FINE_ADJUST
CH2_CLAMP_MODE
Figure 2-1. Analog Video Processors Converters
2.1.1
Video Input Selection
TVP5040 analog channels that accept four video inputs ac-coupled through 0.1-µF capacitors. internal video multiplexers configured host port. four analog video inputs connected follows: Four selectable individual composite video inputs S-video input composite video inputs S-video inputs
2.1.2
Analog Input Clamping Automatic Gain Control Circuits
internal clamping circuit restores ac-coupled video signal fixed level. clamping circuit provides line-by-line restoration video sync level fixed reference voltage. modes clamping provided: coarse fine. coarse mode, most negative portion input signal (typically sync tip) clamped fixed level. Fine clamp mode enabled prevent spurious level shifting caused noise more negative than sync input signal. fine clamp mode selected, clamping only enabled during sync period. S-video requires fine clamp mode chroma channel proper operation. External capacitors 0.1-µF terminal CLAMP1 CLAMP2 required store filter clamp voltage. input video signal amplitude vary significantly from nominal level Vpp. automatic gain control circuit (AGC) adjusts signal amplitude utilize maximum range converter without clipping. adjusts gain achieve desired sync amplitude. Some nonstandard video signals contain peak white levels that saturate converter. these cases, automatically cuts back gain avoid clipping. digital data path, scaling applied output data reach CCIR601 levels. This scaling introduces distortion digitized sync back porch levels precise. fine gain offset adjustment block precisely controls sync back porch levels achieve best linearity performance.
2.1.3
Converters
TVP5040 contains 10-bit oversampling converters that digitize analog video inputs. inputs digitized greater than times Nyquist sampling rate, only simple external antialiasing pass filters needed prevent out-of-band frequencies. converter reference voltages terminals REFP REFM require external capacitor network filtering, shown Figure 2-1.
Digital Processing
Figure block diagram TVP5040 digital video decoder processing. This block receives digitized composite S-video signals from converters. performs separation, signal enhancements. also generates horizontal vertical syncs. digital outputs programmed into various formats: 20-bit, 16-bit, 10-bit, 8-bit 4:2:2, 10-bit 8-bit ITU-R BT.656 parallel interface standard. This block also retrieves data stores FIFO. data from FIFO read either through host port output ancillary data video port. This block also detects pseudosync pulses, pulses color striping copy protected material accordance with Macrovision specification. TVP5040 DIGITAL PROCESSING
Luma Composite Decimation Filter
Chroma Decimation Filter
GAIN CLAMP CTRL INPUT FINE CTRL
Analog Processor Control
Macrovision Detection Host Port Data Slicer
INTREQ VC[3:0] A[1:0] D[7:0]
AVID VSYN HSYN PALI GLCO
Synchronization Separation
Luma/Chroma Processing XTAL1 XTAL2 SCLK PCLK PREF RSTOUTB RSTINB Clock Signals Generation Power Control
Data bypass
Output Formatter
Y[9:0] UV[9:0]
Figure 2-2. Digital Video Signal Processing Block Diagram
2.2.1
Digital Input Selection
digital processing block takes digitized composite S-video from internal converters running PCLK rate. data from converters appropriately multiplexed shown Figure downstream separation processing luma chroma. Input Multiplexer
Decimation Filter
Luma Composite
Decimation Filter
Chroma
Figure 2-3. Digital Input Multiplexer
2.2.2
Decimation Filter
Digitized composite S-video PCLK rate first passes through decimation filters that reduce data rate from PCLK. decimation filter half-band filter whose frequency response shown Figure 2-4. applications that tolerate high frequency roll off, decimation filters bypassed host port. oversampling decimation filtering effectively increase overall signal-to-noise ratio This advantage lost decimation filter bypassed.
Amplitude CCIR 6.10 NTSC 5.54 Frequency
6.66
Figure 2-4. Decimation Filter Frequency Response
2.2.3
Separation
Figure illustrates luminance/chrominance (Y/C) separation process TVP5040. 10-bit composite video multiplied subcarrier signals quadrature demodulator generate color difference signals then into low-pass filter achieve desired bandwidth. adaptive 3-line comb filter separates from based unique property color phase shifts from line line. chroma remodulated through quadrature modulator subtracted from line-delayed composite video generate luma. This form separation completely complementary, thus there loss information. However some applications, desirable limit bandwidth avoid crosstalk. that case, notch filters turned accommodate some viewing preferences, peaking filter also available luma path. separation bypassed S-video input. Contrast, brightness, hue, saturation programmable host port.
TVP5040 SEPARATION
Composite Line Delay
Peaking Quadrature Modulation
Subcarrier Generation
Contrast Brightness Saturation Control Notch Filter
Color 3-Line Adaptive Comb Filter
Notch Filter
Quadrature Demodulation
Burst Accumulator
Notch Filter Notch Filter
Delay
Color
Delay
Burst Accumulator
Sync Block
Figure 2-5. Separation Block Diagram
2.2.3.1 Color Low-Pass Filter
Color low-pass filter frequency responses shown Figures 2-9. High filter bandwidth preserves sharp color transitions produces crisp color boundaries. However, nonstandard video sources that have asymmetrical side bands, desirable limit filter bandwidth avoid crosstalk. Color low-pass filter bandwidth programmable enabling three notch filters.
Amplitude Frequency NTSC 1.11 CCIR 1.22 1.33 Amplitude Frequency Notch1 Filter Notch2 Filter Notch Filter 1.11 Notch3 Filter
Figure 2-6. Color Low-Pass Filter Frequency Response
Figure 2-7. Color Low-Pass Filter With Notch Filter Frequency Response (NTSC PAL-M Square Pixel Sampling)
Amplitude Frequency Notch2 Filter Notch Filter 1.22 Amplitude Notch3 Filter Notch1 Filter
Notch2 Filter Notch Filter 1.33 Notch3 Filter Notch1 Filter
Frequency
Figure 2-8. Color Low-Pass Filter With Notch Filter Characteristics (13.5 Sampling)
Figure 2-9. Color Low-Pass Filter With Notch Filter Frequency Response (PAL Square Pixel Sampling)
2.2.3.2 Adaptive Comb Filter
separation done using adaptive 3-line (2-H delay), fixed 3-line, fixed 2-line comb filters, chroma trap filter shown Figure 2-10. Adaptive comb filtering available both luminance chrominance. adaptive comb filter algorithm computes vertical horizontal contours color based block pixels. there sharp color transition, comb filtering applied lines that have fewer color changes. there color transition, 3-line comb filtering used with choice filter coefficients [1/4, 1/2, 1/4] [1/2, 1/2] programmable host port. Characteristics 2-line 3-line comb filters shown Figure 2-11. filter frequency plots show that both 2-line 3-line (with filter coefficients [1/4,1/2,1/4] comb filters have zeros horizontal line frequency separate interleaved spectrum NTSC. 3-line comb filter less cross-luma cross-chroma noise slightly sharper filter off. 3-line comb filter with filter coefficients[1/2, 1/2] zeros horizontal line frequency. This should used only because degrees phase shifting from line line. comb filter selectively bypassed luma chroma path. comb filter bypassed luma path, then chroma trap filters used which shown Figures 2-12 2-14. TI's patented adaptive comb filter algorithm reduces artifacts such hanging dots color boundary detects properly handles false colors high frequency luminance images such multiburst pattern circle pattern. Adaptive comb filtering recommended mode operation. ADAPTIVE COMB FILTER
Adap_EN Comb_EN Adaptive Comb Filter Algorithm Filter Select
Comb12 Luma Comb
Line Delay
Comb123
Comb23
Line Delay
Comb13 Comb Bypass
Chroma Comb
Figure 2-10. 3-Line Adaptive Comb Filtering
Amplitude Amplitude 0.25, 0.5, 0.25 Frequency 0.5, 0.5, 0.5,
Frequency Notch Filter Notch1 Filter Notch3 Filter Notch2 Filter
Figure 2-11. Comb Filters Frequency Response
Figure 2-12. Chroma Trap Filter Frequency Response (NTSC Square Pixel Sampling)
Amplitude Amplitude Frequency Notch Filter Notch1 Filter Notch3 Filter Notch2 Filter
Notch Filter Notch1 Filter Notch3 Filter
Notch2 Filter
Frequency
Figure 2-13. Chroma Trap Filter Frequency Response (13.5 Sampling)
Figure 2-14. Chroma Trap Filter Frequency Response (PAL Square Pixel Sampling)
2.2.4
Luminance Processing
digitized composite video signal passes through either luminance comb filter chroma trap filter, either which removes chrominance information from composite signal generate luminance signal. luminance signal then input peaking circuit. Figure 2-15 illustrates basic functions luminance data path. High frequency components luminance signal enhanced peaking filter (edge-enhancer). Figure 2-16, Figure 2-17, Figure 2-18 show characteristics peaking filter four different gain settings programmable host port.
Gain
Bandpass Filter
Peaking Filter
Delay
Figure 2-15. Luminance Edge-Enhancer Peaking Block Diagram
2.40 Gain Amplitude Amplitude Gain Frequency Frequency Gain Gain Gain Gain Gain Gain 2.64
Figure 2-16. Peaking Filter Response, NTSC PAL-M Square Pixel Sampling
Figure 2-17. Peaking Filter Response, 13.5 Sampling Rate
2.89 Gain Gain Amplitude Gain Gain Frequency
Figure 2-18. Peaking Filter Response, Square Pixel
2.2.5
Chrominance Processing
quadrature demodulator extracts components from composite signal. signals then pass through gain control stage chroma saturation adjustment. comb filter applied both eliminate cross-chrominance noise. control achieved with phase shift digitally controlled oscillator. automatic color killer (ACK) circuit also included this block. will suppress chroma processing when color burst video signal weak present.
2.2.6
Clock Circuits
internal line-locked generates system pixel clocks. Figure 2-19 shows simplified clock circuit diagram. digital control oscillator (DCO) generates reference signal horizontal PLL. 14.318-MHz clock required drive DCO. This input TVP5040 level XTAL1 terminal, crystal 14.318 fundamental resonant frequency connected across terminals XTAL1 XTAL2. Figure 2-20 shows reference clock configurations. example crystal circuit shown Figure 2-20 parallel-resonant crystal with 14.31818 fundamental frequency), external capacitors must have following relationship: C(stray) where C(stray) terminal capacitance with respect ground. Note that with crystal oscillator, external 4.53-K resistor required across XTAL1 XTAL2 terminals.
2-10
Digitized Video
Lowpass Filter Sync Detector
Phase Detector
Loop Filter
Digital Control Oscillator
Crystal Clock Generator
XTAL1 XTAL2
Clock Generation Circuit
Line-Locked Clock
SCLK PCLK
Figure 2-19. Clock Circuit Diagram
14.31818 Crystal XTAL2 XTAL2
TVP5040 14.31818 Clock
TVP5040
XTAL1
XTAL1
Figure 2-20. Example Reference Clock Configurations TVP5040 generates three signals PCLK, SCLK, PREF used clocking data. PCLK, pixel clock, used clocking data 20-bit 16-bit 4:2:2 output formats. SCLK twice PCLK frequency used clocking data 10-bit 8-bit 4:2:2 well ITU-R BT.656 formats. PREF used clock qualifier with SCLK clock data 20-bit 16-bit 4:2:2 formats.
2-11
Genlock Control
frequency control word internal color subcarrier digital control oscillator (DCO) sub-carrier phase reset transmitted GLCO terminal. frequency control word 23-bit binary number. frequency calculated from following equation:
Fctrl
sclk
where Fdco frequency DCO, Fctrl 23-bit frequency control Fsclk frequency SCLK. last (bit frequency control always write chrominance control register host port sub-address causes sub-carrier phase reset sent next scan line GLCO. active reset occurs SCLKs after transmission last frequency control. Upon transmission reset bit, phase TVP5040 internal subcarrier reset zero. genlocking slave device connected GLCO terminal information GLCO synchronize internal color phase achieve clean line color lock. Figure 2-21 shows timing GLCO.
SCLK
GLCO
>128 SCLK
SCLK
SCLK
SCLK Start 23-Bit Frequency Control
SCLK Reset
Figure 2-21. GLCO Timing
Video Output Format
TVP5040 supports both square-pixel ITU-R BT.601 sampling formats multiple Y-UV output formats: 20-bit 4:2:2 16-bit 4:2:2 10-bit 4:2:2 8-bit 4:2:2 10-bit ITU-R BT.656 8-bit ITU-R BT.656
2-12
2.4.1
Sampling Frequencies Patterns
sampling frequencies that control number pixels line differ depending video format standards. Table shows summary sampling frequencies. TVP5040 outputs data 4:2:2 sampling pattern. Every second sample both luminance chrominance sample. remainder luminance-only samples. Table 2-1. Summary Line Frequencies, Data Rates, Pixel Counts
STANDARDS NTSC, square-pixel NTSC, ITU-R BT.601 PAL(B,D,G,H,I), square-pixel PAL(B,D,G,H,I),ITU-R BT.601 PAL(M),square-pixel PAL(M),ITU-R BT.601 PAL(Combination-N), square-pixel PAL(Combination-N), ITU-R BT.601 HORIZONTAL LINE RATE (kHz) 15.73426 15.73426 15.625 15.625 15.73426 15.73426 15.625 15.625 PIXELS LINE ACTIVE PIXELS LINE Y716 U358 V358 PCLK FREQUENCY (MHz) 12.2727 13.50 14.75 13.50 12.2727 13.50 14.75 13.50 Y717 Y718 U359 V359 SCLK FREQUENCY (MHz) 24.54 27.00 29.50 27.00 24.54 27.00 29.50 27.00 Y719
Luminance-Only Sample Luminance Chrominance Sample Numbering shown 13.5-MHz sampling
Figure 2-22. 4:2:2 Sampling
2.4.2
Video Port 20-Bit 16-Bit 4:2:2 Output Format Timing
SCLK
PREF
PCLK
Y[9:0]
Y716
Y717
Y718
Y719
UV[9:0]
U358
V358
U359
V359
Numbering shown 13.5-MHz sampling
Figure 2-23. 20-Bit 4:2:2 Output Format
2-13
2.4.3
Video Port 10-Bit 8-Bit 4:2:2 ITU-R BT.656 Output Format Timing
SCLK
Y[9:0]
U359
Y718
V359
Y719
UV[9:0]
HIGH
Numbering shown 13.5-MHz sampling
Figure 2-24. 20-Bit 4:2:2 Output Format
2-14
Synchronization Signals
525-Line Composite Video Field GPCL/VBLK
Composite Video Even Field GPCL/VBLK
625-Line Composite Video Field
GPCL/VBLK
Composite Video Even Field GPCL/VBLK
Note: Line numbering conforms ITU-R
Horizontal Detail (default HSYN timing)
Figure 2-25. Vertical Synchronization Signals
2-15
10-bit 4:2:2 timing with pixel clock (SCLK) reference. ITU-R BT.656 timing also shown. NTSC Datastream NTSC Datastream Datastream 1436 1436 1276 1532 1437 1437 1438 1439 1440 1441 1438 1439 1440 1441 1471 1463 1472 1464 1599 1591 1600 1592 1711 1712 1713 1714 1715 1723 1724 1725 1726 1727
1277 1278
1279 1280 1281 1535
1323 1324
1451
1452 1555 1556 1557 1558 1559
1533 1534
1536 1537
1579 1580
1707
1708
1883 1884 1885 1886 1887
HSYN AVID
Note: AVID rising edge occurs SCLK cycles early when ITU656 output mode
HSYN timing shown valid when HSYN start (register default value 80h.
20-bit 4:2:2 timing with pixel clock (PCLK) reference. NTSC NTSC
HSYN
AVID
HSYN timing shown valid when HSYN start (register default value 80h. Figure 2-26. Horizontal Synchronization Signals
2-16
Host Interface
host interface used initialize internal microprocessor, read write status registers, access sliced data. interface modes supported TVP5040 I2C, three parallel interface modes, mode. host interface configured power reset using GLCO, PALI, terminals shown Table 2-2. Table 2-2. Host Port Select
TERMINALS Parallel Parallel Parallel GLCO PALI
Host Interface
TVP5040 host interface configured operation attaching external pullup pulldown resistors GLCO, PALI, terminals. following combination resistors required select host mode pullup pulldown).
GLCO Host Port Enabled PALI
2.7.1
Host Port Select
standard consists signals, serial input/output data (VC1) line input/output clock line (VC0), which carry information between devices connected bus. third signal (VC3) used slave address selection. Although system multimastered, TVP5040 functions slave device only. Both bidirectional lines connected positive supply voltage pullup resistor. When free, both lines high. slave address select terminal (VC3) enables TVP5040 devices tied same bus. Table summarizes terminal functions I2C-mode host interface. Table 2-3. Host Port Terminal Description
SIGNAL (I2CA) (SCL) (SDA) (open drain) (open drain) TYPE DESCRIPTION Slave address selection Input/output clock line Input/output data line
2-17
VC1(SDA)
VC0(SCL) ADDRESS DATA DATA
Start Condition
VC0(SCL)
DATA
DATA
Stop Condition
Figure 2-27. Data Transfer data transfer rate kbits/s. number interfaces connected dependent capacitance limit data line must stable during high period clock. high state data line only change with clock signal line being low. multiple bytes transferred during read write operation, internal subaddress automatically incremented. high transition line while high indicates start condition. high transition line while high indicates stop condition. Acknowledge (SDA low) Not-Acknowledge (SDA high)
Every byte placed line must 8-bits long. number bytes that transferred unrestricted. Each byte must followed acknowledge bit. slave receive another complete byte data until performed another function, hold clock line (SCL) force master into wait state. Data transfer then continues when slave ready another byte data releases clock line (SCL). data transfer with acknowledgement obligatory. acknowledge related clock pulse generated master. master releases line high during acknowledge clock pulse. slave must pull down line during acknowledge clock pulse that remains stable during high period this clock pulse. When slave does acknowledge slave address, data line must left high slave. master then generate stop condition abort transfer. slave does acknowledge slave address some time later transfer cannot receive more data bytes, master must again abort transfer. This indicated slave generating acknowledge first byte follow. slave leaves data line high master generates stop condition. master-receiver involved transfer, must signal data slave-transmitter generating acknowledge last byte that clocked slave. slave-transmitter must release data line allow master generate stop repeated start condition.
2-18
2.7.2
Write Operation
data transfers occur utilizing following illustrated formats. master initiates write operation TVP5040 generating start condition followed TVP5040s address 101110X TVP5040 address when terminal tied when terminal tied high, first order, followed indicate write cycle. After receiving acknowledge from TVP5040, master presents subaddress register, first block registers wants write, followed more bytes data, first. TVP5040 acknowledges each byte after completion each transfer. master terminates write operation generating stop condition.
STEP Start (master) STEP General address (master) STEP Acknowledge (slave) STEP Write register address (master) STEP Acknowledge (slave) STEP Write data (master) STEP Acknowledge (slave) STEP Stop (master) addr Data Data Data Data Data Data Data Data addr addr addr addr addr addr addr
Repeat steps until data been written.
2.7.3
Read Operation
read operation consists phases. first phase address phase. this phase, master initiates write operation TVP5040 generating start condition followed TVP5040s address 101110X, first order, followed indicate write cycle. After receiving acknowledge from TVP5040, master presents subaddress register, first block registers wants read. After cycle acknowledged, master terminates cycle immediately generating stop condition. second phase data phase. this phase, master initiates read operation TVP5040 generating start condition followed TVP5040s address 101110X, first order, followed indicate read cycle. After acknowledge from TVP5040, master receives more bytes data from TVP5040. master acknowledges transfer each byte. After last data byte desired been transferred from TVP5040 master, master generates acknowledge followed stop.
2-19
2.7.3.1 Read Phase
STEP Start (master) STEP General address (master) STEP Acknowledge (slave) STEP Read register address (master) STEP Acknowledge (slave) STEP Stop (master) addr addr addr addr addr addr addr addr
2.7.3.2 Read Phase
STEP Start (master) STEP General address (master) STEP Acknowledge (slave) STEP Read data (slave) STEP Acknowledge (master) STEP Read data (slave) STEP acknowledge (master) STEP Stop (master) Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data
Repeat steps last byte read.
2-20
2.7.4
Microcode Write Operation
microcode write operation required down load microcode TVP5040 program after power-up reset. During write cycle internal microprocessors program counter resets points location zero program remains reset. Upon completion write operation, microprocessor CLEAR-RESET operation required. This performed writing into register clear reset resume microprocessor function. (There specific data requirement written into register, data will resume microprocessor function.)
STEP Start (master) STEP General address (master) STEP Acknowledge (slave) STEP Write register address (master)
Write program address=7E
STEP Acknowledge (slave) STEP Write data (master) STEP Acknowledge (slave) STEP Stop (master) Data Data Data Data Data Data Data Data
Repeat steps until data been written.
2-21
2.7.5
Microprocessor CLEAR-RESET
STEP Start (master) STEP General address (master) STEP Acknowledge (slave) STEP Write register address (master)
Write microprocessor clear reset address=7F
STEP Acknowledge (slave) STEP Write data (master) Data Data Data Data Data Data Data Data
data written starts microprocessor.
STEP Acknowledge (slave) STEP Stop (master)
2-22
2.7.6
Microcode Read Operation
data written during microcode write operation read from TVP5040 program RAM. During read cycle, internal microprocessors program counter resets points location zero program remains reset. Upon completion read operation, microprocessor CLEAR-RESET operation required. This performed writing into register clear reset resume microprocessor function. (There specific data requirement written into register, data resumes microprocessor function.)
STEP Start (master) STEP General address (master) STEP Acknowledge (slave) STEP Read register address (master)
Read address=8E
STEP Acknowledge (slave) STEP Stop (master)
2.7.6.1 Read Phase
STEP Start (master) STEP General address (master) STEP Acknowledge (slave) STEP Read data (slave) STEP Acknowledge (master) Data Data Data Data Data Data Data Data
Repeat STEP STEP last byte read from program RAM.
STEP Read data (slave) STEP acknowledge (master) STEP Stop (master) Data Data Data Data Data Data Data Data
2-23
Host Interface Port
TVP5040 host interface configured video interface port (VIP) operation attaching external pullup pulldown resistors GLCO, PALI, terminals. following combination resistors required select host mode, where 0=pulldown 1=pullup.
GLCO host port enabled PALI
video interface port standard interface, conforming Video Electronics Standards Association (VESA) specification version between video enabled graphics device more video devices. video port transports various types real-time signal streams. Signal names parenthesis denote signal name referenced specification. Five terminals required host port transfers: VC3, VC0, VC1, VC2, INTREQ. Table summarizes terminal functions VIP-mode host interface.
2.8.1
Host Port Terminal Description
Table 2-4. Host Port Terminal Description
SIGNAL TYPE host clock (25-33 MHz) Host address/data (HAD_0) (HAD_1) Host control. This includes symbolic signals VFRAME, DTACK VSTOP. Interrupt request DESCRIPTION
(VIPCLK) VC0,VC1 (HAD[0:1] (HCTL) INTREQ (VIRQ)
(open drain) (nominal open drain)
(VIPCLK) host port clock, specified from 25-33 MHz. VIPCLK from source. (HAD[0:1]) wire bus, used transfer commands, addresses data between master slave devices. (HCTL) shared control terminal. driven master initiate terminate data transfers. driven slave terminate wait states data transfers. Because shared control signal, special attention must given generation avoid conflicts. INTREQ nominally open drain terminal used signal interrupts host controller. This terminal configured conventional CMOS buffer (non-open drain) desired using interrupt configuration register subaddress Contention possible multiple devices connected INTREQ signal configured non-open drain mode. Upon power module outputs remain high impedance state until request from motherboard signals module begin driving bus.
VESA trademark Video Electronics Standards Association.
2-24
2.8.2
Phases
Figure 2-28 illustrates example typical transfer Table describes sequence phases involved data transfer.
Zero Wait State COMMAND PHASE ADDRESS PHASE RETRY PHASE DATA PHASE PHASE
(VIPCLK) Decode phase allows slave decode address turnaround phase
VC0(HAD0) VC1(HAD1)
don't care
don't care
don't care
don't care
don't care
Master drive HCTL high start transfer
Slave drives DTACK signal that data ready next phase
must drive this during idle
VC2(HCTL) Master 3-states, (HCTL) floats high Master drives during idle VSTOP drive terminate transfer. terminated there will data phase Slave drives high transfer terminated cycle Slave 3-states, (HCTL) remains high
Slave drive DTACK next byte. irrelevant transfer already terminated
FRAME and/or VSTOP drive terminate transfer
Figure 2-28. Transfer
2-25
Table 2-5. Host Port Phase Description
PHASE Command EXPLANATION host port transfers start with command phase. 8-bit command/address byte multiplexed onto (HAD[1:0]) during command phase. command byte selects between devices, read, write cycles, register FIFO transfers contains most significant four bits register address. During register transfers command phase followed address extension phase. least significant 8-bits register address multiplexed onto (HAD[1:0]) during address extension phase. This phase present during FIFO transfers. Following command command/address phase(s), clock delay required allow slave devices decode address determine they able respond within wait phase requirement active operation. four clock cycles immediately following decode phase constitute retry phase. During retry phase, slave indicates desire terminate operation without transferring data (retry), wait phase transfer first byte data. When slave asserts VSTOP, transfer ends with retry phase. When slave neither terminates transfer accepts byte, retry phase followed wait phase. During second cycle decode, retry wait phase, slave indicates ability transfer next byte data driving (HCTL) low. When slave does drive (HCTL) transfer terminated, current phase followed wait phase. During wait phases, current owner (master writes, slave reads) continues drive however data transferred. slave allowed wait phase byte register accesses without compromising system timing. Additional wait phases prevented overall system reliability compromised. When (HCTL) deasserted during cycle retry, wait data phase, current phase followed data phase. Data transferred between master slave devices during data phases, multiplexed onto (HAD[1:0]). Immediately following last transfer phase read transfer, cycle delay required giving slave time 3-state (HAD) bus. master free begin transfer, driving (HAD) (HCTL) immediately following phase.
Address
Decode Retry
Wait
Data
2.8.3
Commands Address Space
Table summarizes supported commands address space mapping. Note that only three four FIFO channels used TVP5040. data FIFO mapped FIFO program memory write operation mapped FIFO program memory read operation mapped FIFO FIFO used TVP5040 therefore indicated present status register. Table 2-6. Summary Commands Address Spaces
COMMAND [7:4] Cmd/Addr [3:0] 0000 0001 0010 0011 0000 0001 0100 0101 0110 REGISTER ADDRESS [7:0] 00000000 through 11111111 00000000 through 11111111 00000000 through 11111111 Address previously written address phase address phase address phase address phase address phase DATA [7:0] dddddddd dddddddd xxxxxxxx ddddddd xx0/1xxx0/1 xxxxxx11 dddddddd dddddddd dddddddd configuration registers General TVP5040 registers latency read access phase latency read access phase FIFO status read FIFO status read FIFO data read (FIFO FIFO program memory write (FIFO FIFO program memory read (FIFO COMMENT
2-26
2.8.4
Command Byte
During command phase, hardware control line(VC2) transitions high hardware address lines (VC0 VC1) transmit command byte from host TVP5040. command byte determines nature data transfer TVP5040 address space which affected.
Command NAME DEVSEL1:0 A11:8 1=Read 1=FIFO 0=Write 0=Register access DEVSEL1 DEVSEL0
DESCRIPTION Device select. Always TVP5040
Address upper bits register accesses: 0000 VIP-specific configuration registers 0001 General TVP5040 registers 0010 latency read access phase 0011 latency read access phase FIFO accesses: 0000 FIFO status 0001 FIFO status 0100 FIFO 0101 Program memory write FIFO 0110 Program memory read FIFO
2.8.4.1 Access Latency Wait States
accesses registers FIFO require TVP5040 insert more wait states into access sequence. register accesses wait states total normal writes release host port immediately internal wait states continue generated until operation completes. attempt access host port while write operation completed results slave termination TVP5040. burst writes, TVP5040 inserts wait states that total Reads (except no-latency reads detailed section 2.8.4.2) hold host port until completion. Figure 2-29 through Figure 2-32 illustrate examples accesses with wait states slave termination TVP5040.
2-27
COMMAND
ADDRESS
WAIT
WAIT
LAST WAIT
VC0/VC1
Wait states last DATA WAIT WAIT LAST WAIT DATA
VC0/VC1
Wait states last
Figure 2-29. Reading From Registers With Wait States
COMMAND ADDRESS WAIT DATA WAIT
VC0/VC1
Wait states last WAIT WAIT WAIT WAIT DATA
VC0/VC1
Wait states last
Figure 2-30. Writing Registers With Wait States (Burst Write)
2-28
Write commands require wait state before data phase. burst writes, subsequent data phases require wait states Wait states before second subsequent data phases fixed.
COMMAND WAIT WAIT WAIT
VC0/VC1
DATA
WAIT
WAIT
WAIT
DATA
VC0/VC1
Figure 2-31. Reading From FIFO With Wait States Read commands from FIFO typically require three wait states when running full speed (VIPCLK MHz).
COMMAND ADDRESS WAIT COMMAND
VC0/VC1
Slave Termination
Figure 2-32. Slave Termination Configuration Registers: TVP5040 supports configuration registers which accessible only host mode. Information register functions available section 2.13, subaddresses 000-0FF. configuration registers read-only.
COMMAND PHASE configuration register read ADDRESS PHASE DATA PHASE (from TVP5040)
2-29
General TVP5040 Registers: bulk TVP5040 register space consists status control registers that available host I2C, VIP, modes. Information register functions available section 2.14 subaddresses 100-1FF.
COMMAND PHASE General TVP5040 register read ADDRESS PHASE DATA PHASE (from TVP5040)
COMMAND PHASE General TVP5040 register write
ADDRESS PHASE
DATA PHASE TVP5040)
2.8.4.2 Latency Read
order avoid holding host port extended wait states normal read operation, special latency read mode implemented TVP5040. NOTE:This special mode part specification. latency read consists zero wait-state phases separated idle period, during which host perform other operations. first phase identifies register address read. response first phase read, TVP5040 outputs data immediately from internal intermediate buffer. Note that data intermediate data buffer from register currently being addressed. Following completion first phase, host must wait ensure that data requested first phase available intermediate data buffer. attempt host port during this time results slave termination TVP5040. host then initiates second phase read data from intermediate buffer.
COMMAND PHASE latency read Phase ADDRESS PHASE DATA PHASE (from TVP5040)
COMMAND PHASE latency read Phase
ADDRESS PHASE
DATA PHASE (from TVP5040)
pipelined read several registers done having host initiate series back-to-back phase reads, with each phase read occurring least from previous phase read. With this, every phase read, TVP5040 returns data previous phase read. Finally, end, host must initiate phase read data last read transaction.
COMMAND PHASE latency read (pipelined) Phase ADDRESS PHASE DATA PHASE (from TVP5040)
COMMAND PHASE latency read (pipelined) Phase
ADDRESS PHASE
DATA PHASE (from TVP5040)
COMMAND PHASE latency read (pipelined) Phase
ADDRESS PHASE
DATA PHASE (from TVP5040)
2-30
2.8.4.3 FIFO Status Register
FIFO status register returns bits which report status unused bits.
Undefined Undefined Undefined DREQA Undefined Undefined Undefined VIRQ
DREQA: request FIFO This same teletext threshold (bit interrupt status register subaddress 1C0). section 2.14 definition this bit. VIRQ: This returns status INTREQ terminal. Reading this does clear terminal.
COMMAND PHASE FIFO status read DATA PHASE
There address phase associated with reading FIFO status register.
2.8.4.4 FIFO Status Register
FIFO status register returns status FIFO channels TVP5040.
Undefined PRESENT-D R/W-C PRESENT-C R/W-B PRESENT-B R/W-A PRESENT-A
R/W: This FIFO read port. PRESENT: This FIFO present, otherwise
COMMAND PHASE FIFO status read DATA PHASE
There address phase associated with reading FIFO register. This register read-only always 0x37.
2.8.4.5 FIFO (FIFO
FIFO stores sliced data format described section 2.9.1. Data read from FIFO average rate data byte cycles data cycles, wait cycles) when VIPCLK maximum speed.
COMMAND PHASE FIFO read DATA PHASE
There address phase associated with reading FIFO. FIFO polling implemented.
2-31
2.8.5
Microcode Write Operation (FIFO
microcode write operation required download microcode TVP5040 program after power-up reset. During write cycle, internal microprocessors program counter resets points location zero program remains reset. Upon completion write operation, microprocessor CLEAR-RESET operation required. This performed writing into 017F register clear reset resume microprocessor function. (There specific data requirement written into 017F register; data resumes microprocessor function.)
COMMAND PHASE Microcode write Program FIFO write COMMAND PHASE Clear reset ADDRESS PHASE DATA PHASE TVP5040) DATA PHASE (toTVP5040)
There address phase associated with writing program RAM.
2.8.6
Microcode Read Operation (FIFO
data written during microcode write operation read from TVP5040 program RAM. During read cycle, internal microprocessors program counter resets points location zero program remains reset. Upon completion read operation, microprocessor CLEAR-RESET operation required. This performed writing into 017F register clear reset resume microprocessor function. (There specific data requirement written into 017F register; data resumes microprocessor function.)
COMMAND PHASE Microcode read Program FIFO Read COMMAND PHASE Clear reset ADDRESS PHASE DATA PHASE (from TVP5040) DATA PHASE (from TVP5040)
There address phase associated with reading program RAM.
2-32
2.8.7
Parallel Host Interface
Parallel host interface compatible with video module interface (VMI) proposal version mode terminal descriptions defined Table 2-7. Table 2-7. Parallel Host Interface Terminal Description
TERMINAL A[1:0] D[7:0] INTREQ SIGNAL HA[1:0] HD[7:0] RD/WR DTACK INTREQ TYPE Address from host Bidirectional data Chip select, active Data strobe, active Read, active high Write, active Data acknowledge Interrupt request, active open drain default, external pullup resistor required-can configured conventional CMOS buffer, active high with external pullup resistor. DESCRIPTION
Parallel host interface timing shown Figure 2-33. cycle initiated host when VC2-DS transitions low. TVP5040 responds pulling VC0-DTACK indicate data been received that requested data present bus. host then completes cycle pulling VC2-DS high. Once host completed cycle, TVP5040 sets VC0-DTACK high impedance. pullup required pull VC0-DTACK high indicate operation complete.
PARAMETER tsu(1) td(1) th(1) td(2) td(3) td(4) tsu(2) th(2) A[1:0],D[0:7], RD/WR setup until Delay DTACK after A[1:0], D[0:7], RD/WR hold after high Delay high after DTACK Delay DTACK high after high Delay low(next cycle) after DTACK high (Read cycle) D[7:0] setup until DTACK (Read cycle) D[7:0] hold after high TEST CONDITIONS UNIT
2-33
A[1:0]
D[7:0] WRITE
Write Data
(VC3)
RD/WR (VC1)
tsu(1)
th(1)
(VC2)
td(2) td(1) DTACK (VC0) tsu(2) D[7:0] READ
td(3) td(4)
th(2) Read Data
Figure 2-33. Parallel Host Interface Timing
2.8.8
Parallel Host Interface
Parallel host interface compatible with video module interface (VMI) proposal version mode terminal descriptions defined Table 2-8. Table 2-8. Parallel Host Interface Terminal Description
TERMINAL A[1:0] D[7:0] INTREQ SIGNAL HA[1:0] HD[7:0] TYPE Address from host Bidirectional data Chip select, active Read, active Write, active Ready, active high Interrupt request, active open drain default, external pullup resistor required-can configured conventional CMOS buffer, active high with external pullup resistor. DESCRIPTION
2-34
parallel host interface timing shown Figure 2-34. cycle initiated host when VC2-RD VC1-WR transitions low. TVP5040 responds pulling VC0-RDY low. TVP5040 then sets VC0-RDY high impedance. pullup resistor required indicate data received that requested data present bus. host then completes cycle pulling asserted signal, VC2-RD VC1-WR high.
PARAMETER tsu(3) th(3) td(5) tsu(4) th(4) tw(1) tw(2) tsu(5) th(5) td(6) tw(3) A[1:0], setup until active A[1:0], hold after inactive Delay after active D[7:0] setup until active D[7:0] hold after inactive inactive pulse width inactive until command active (Read cycle) D[7:0] setup until active (Read cycle) D[7:0] hold after inactive Delay inactive after active command pulse width TEST CONDITIONS UNIT
A[1:0]
(VC3) tsu(3) (VC1) (VC2) td(5) (VC0) D[7:0] WRITE td(6) tw(1) tw(2) tw(3) th(3)
tsu(4)
Write Data tsu(5)
th(5) Read Data
D[7:0] READ
Figure 2-34. Parallel Host Interface Timing
th(4)
2-35
2.8.9
Parallel Host Interface
terminal descriptions defined Table 2-9. Table 2-9. Parallel Host Interface Terminal Description
TERMINAL A[1:0] D[7:0] INTREQ SIGNAL HA[1:0] HD[7:0] RD/WR TYPE Address from host Bidirectional data Chip select, active Data strobe, active Read, active high-Write, active Ready, active high Interrupt request, active open drain default, external pullup resistor required-can configured conventional CMOS buffer, active high with external pullup resistor. DESCRIPTION
Parallel host interface timing shown Figure 2-35. cycle initiated host when VC2-DS transitions low. TVP5040 responds pulling VC0-RDY low. TVP5040 will then VC0-RDY high impedance, pullup resistor required indicate data received that requested data present bus. host then completes cycle pulling VC2-DS high.
PARAMETER tsu(6) th(6) td(7) tsu(7) th(7) A[1:0],D[7:0], RD/WR, setup until A[1:0],D[7:0], RD/WR, hold after high Delay after (Read cycle) D[7:0] setup until high (Read cycle) D[7:0] hold after high (VC3) TEST CONDITIONS UNIT
A[1:0]
RD/WR (VC1)
D[7:0] WRITE
Write Data
tsu(6)
(VC2)
td(7) (VC0) tsu(7) Read Data
D[7:0] READ
Figure 2-35. Parallel Host Interface Timing
2-36
th(6) th(7)
2.8.10 Parallel Host Interface Register
parallel host interface (PHI) module contains only four registers that directly accessible host (see Figure 2-36). address register holds indirect address internal register access. When host accesses data register module reads writes internal register selected indirect address register. other registers provided direct access. FIFO register provides direct access FIFO. other direct access register status/interrupt register. This register contains state interrupt sources.
A[1:0] Address Register Data Register FIFO Status Register
Figure 2-36. Address Register Normally, read write operations require accesses. read FIFO register, A[1:0] 2'b10, perform read cycle. FIFO read data placed D[7:0] bus. read/write status/interrupt register, A[1:0] 2'b11 perform read/write cycle. read/write data appropriately muxed to/from external data bus. Indirect register read/write accesses except FIFO status/interrupt register require two-step operation. access indirect register, desired internal address must first written address register PHI. This done setting A[1:0] performing write cycle with D[7:0] indirect register address. write indirect register, second step consists writing desired data address read indirect register, second step consists reading requested data from address Read Indirect Register
Step Write register address Step Read register data Register address
Data from register
Write Indirect Register
Step Write register address Step Write register data Register address
Data register
Latency accesses indirect addresses 00-8F require special consideration response latencies these addresses. Latency occurs between steps read operation, following step write operation. avoid violating cycle time requirements host poll cycle complete status register following step read step write. Alternatively, cycle complete enable interrupt enable register (indirect address generate interrupt host when access been completed. accesses indirect addresses 90-CF occur with minimal latency interrupts generated completion access cycles these addresses.
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FIFO FIFO containing sliced data read directly host.
Read FIFO Data from FIFO
Status/Interrupt Register status/interrupt register provides host with information regarding source interrupt. After interrupt condition reset writing appropriate status/interrupt register. Section 2.14 contains description status/interrupt register.
Access status/interrupt register Data from status/interrupt register
2.8.11 Parallel Host Interface Microcode Write Operation
microcode write operation required down load microcode TVP5040 program after power-up reset. During write cycle, internal microprocessors program counter resets points location zero program remains reset. Upon completion write operation, microprocessor CLEAR-RESET operation required. This performed writing into register clear reset resume microprocessor function. (There specific data requirement written into register, data will resume microprocessor function.) avoid violating cycle time requirements during microcode write operation host poll cycle complete status register after writing each byte data data register. Alternatively, cycle complete enable interrupt enable register (indirect address generate interrupt host when write been completed.
Write microcode register address Write microcode register data Write microcode register data Write microcode register data
First byte microcode data (Wait cycle complete status interrupt.) Second byte microcode data (Wait cycle complete status interrupt.) Last byte microcode data (Wait cycle complete status interrupt.)
Write clear-reset register address Write clear-reset dummy data
Dummy data (Wait cycle complete status interrupt.)
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2.8.12 Parallel Host Interface Microcode Read Operation
data read from indirect register read from TVP5040 program RAM. During read cycle, internal microprocessors program counter resets points location zero program remains reset. Upon completion read operation, microprocessor CLEAR-RESET operation required. This performed writing into register clear reset resume microprocessor function. (There specific data requirement written into register, data will resume microprocessor function.) avoid violating cycle time requirements during microcode read operation host poll cycle complete status register after writing address register. Alternatively, cycle complete enable interrupt enable register (indirect address generate interrupt host when read data available data register.
Step Write program read address
(Wait cycle complete status interrupt) Step Read program read data data
NOTE: Repeat Steps until program data been read. Step Write clear-reset register address Step Write clear-reset register data
Dummy data (Wait cycle complete status interrupt)
Data Processor
TVP5040 data processor slices, parses, performs error checking teletext data contained vertical blanking interval during active lines. Teletext formats supported North American Basic Teletext Specification (NABTS) equivalent ITU-R BT.653 system World System Teletext (WST) equivalent ITU-R BT.653 system Data stored internal FIFO read host port transmitted ancillary data digital video stream BT.656 mode. data FIFO holds lines NABTS lines data. Interrupts generated data processor configurable enable host synchronization retrieval full-field teletext data. Closed caption data also sliced data processor stored register accessible host port.
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2.9.1
Teletext Data Byte Order
NABTS LINE SYSTEM Video Line [7:0] Hamming error, parity error, error, match match video line Packet address Packet address Packet address Continuity index Packet structure Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block 27/suffix Data block 28/suffix Padding byte LINE SYSTEM Video Line [7:0] Hamming error, parity error, match match video line Magazine address Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte LINE SYSTEM Video Line [7:0] Hamming error, parity error, match match video line Magazine address Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte
following table shows order which teletext data read from FIFO.
BYTE NUMBER
padding byte used ensure even number writes. This byte does contain useful information. read pointer automatically advances past this byte user does have read padding byte.
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2.9.2
Teletext Ancillary Data Video Stream
Sliced teletext data output ancillary data video stream ITU-R BT.656 mode. Teletext data output Y7:0 terminals during horizontal blanking period following line from which data retrieved. Dummy ancillary data blocks with special timing header information inserted during certain horizontal blanking periods provide data synchronization information. Table 2-10 Table 2-11 show format sequence ancillary data inserted into video stream. Table 2-10. NABTS 525/625-Line Ancillary Data Sequence
BYTE Hamming error Parity error error DID2 Match DID1 Match DID0 Video line Data Secondary data Number 32-bit data words Internal data Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Checksum Fill byte Fill byte Ancillary data preamble DESCRIPTION
Video line number Packet address Packet address Packet address Continuity index Packet structure Teletext data Teletext data Teletext data Teletext data 27/suffix Teletext data 28/suffix Checksum
Table 2-11. Dummy Timing Ancillary Data Sequence
BYTE DID2 DID1 DID0 Data Secondary data Number 32-bit data words Ancillary data preamble DESCRIPTION
tables above, even parity lower bits negated even parity. checksum teletext data blocks LSBs data bytes. data byte provides timing information. Table 2-12 shows possible values data byte their meanings.
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Table 2-12. Ancillary Data
DATA EVENT SOURCE STREAM Start first, field Sliced data lines 1-23 first field nominal first field, line Sliced data line first field Start second, even field Sliced data lines 1-23 second field nominal second field, line Sliced data line second field DATA TYPE Dummy timing block data Dummy timing block Full field teletext data Dummy timing block data Dummy timing block Full field teletext data
dummy timing block inserted into video stream during horizontal blanking period following line each field. teletext data available from line inserted into video stream prior dummy timing block.
2.10 Video Data Output
TVP5040 output samples ITU-656 video stream desired order process data externally. data occurs pixel rate. data preceded preamble sequence preamble sequence occurs immediately following start active video (SAV) sequence.
2.11 Reset Initialization
Reset initiated power time RSTINB terminal brought low. Table 2-13 describes status TVP5040s terminals during immediately after reset. Following power-up reset, host must download microcode TVP5040s program memory internal microprocessor. Table 2-13. Reset Sequence
SIGNAL NAMES Y[9:0], UV[9:0], HSYN, VSYN, FID, PALI AVID SCLK, PCLK PREF GLCO mode mode D[7:0] A[1:0] mode RSTINB, SDA, SCL, I2CA, OEB, GPCL Input Input High-impedance PREF pulled down during reset. Active PREF pulled during reset. Input Input Output High impedance Input Input Input DURING RESET RESET COMPLETED High-impedance AVID pulled down during reset. Active output AVID pulled during reset. High-impedance AVID pulled down during reset. Active output AVID pulled during reset. Active output Active output Active High impedance High impedance High impedance Input Input
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2.12 Internal Control Registers
TVP5040 initialized controlled internal registers which device operating parameters. Communication between external controller TVP5040 through standard host port interface. Table 2-14 shows summary these registers. reserved bits must written with detailed programming information each register described following sections. NOTE: general, registers residing address space through host interface modes, 0100 through 018F host interface mode accessed only after microcode been down loaded TVP5040s internal program CLEAR-RESET operation been issued internal microprocessor. only exceptions registers involved microcode down load, read back, CLEAR-RESET operations. These registers addresses respectively host interface modes 017F (CLEAR-RESET operation only) host interface mode. (Note that host interface mode program write read FIFOs mapped addresses 1500 1600 respectively.)
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Table 2-14. Registers Summary
REGISTER FUNCTION vendor device subsystem vendor subsystem Device power state Reserved power support Reserved revision Reserved Video input source selection Analog channel controls Operation mode controls Miscellaneous controls Reserved Software reset Color killer threshold control Luminance processing control Luminance processing control Brightness control Color saturation control Color control Contrast control Outputs data rate select Luminance processing control Reserved Horizontal sync HSYN start NTSC/PAL Reserved Vertical blanking start Vertical blanking stop Chroma processing control Chroma processing control Interrupt reset Interrupt enable Interrupt configuration Reserved Video input source selection Reserved Lock speed select 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 00FF 0100 0101 0102 0103 0104 0105 0106 0107 0108 0109 010A 010B 010C 010D 010E 010F 0115 0116 0117 0118 0119 011A 011B 011C 011D 011E 011F 0120 0121-0124 0125 0F-15 001C 001D 001E 21-24 0F-15 21-24
NOTE: Read only interfaces Write only interfaces Read write host interfaces (where applicable) Read write host interfaces. Write only host interfaces.
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Table 2-14. Registers Summary (Continued)
REGISTER FUNCTION Crystal frequency Reserved Video standard Reserved Reserved NonVIP program write Microprocessor reset clear Major software revision Status Status Status Status Interrupt status Interrupt active Minor software revision Status Vertical line count Vertical line count Analog Digital Reserved Reserved NonVIP program read Reserved filter parameters filter parameters error filtering enable transaction processing enables Reserved control register Line enable register Line enable register Custom sync pattern Reserved Reserved NonVIP teletext FIFO Reserved data Buffer status Interrupt threshold Interrupt line number FIFO control FIFO test 0126 0127 0128 0129 017D 017E 017F 0180 0181 0182 0183 0184 0185 0186 0187 0188 0189 018A 018B 018C 018D 018E 018F 0190 0194 0195 0199 019A 019B 019C 019F 01A0 01A1 01A2 01A3 01A4 01AF 01B0 01B1 01B2 01B3 01B4 01B5 01B6 01B7 29-7D 9C-9F 29-7D 9C-9F
NOTE: Read only interfaces Write only interfaces Read write host interfaces (where applicable) Read write host interfaces. Write only host interfaces.
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Table 2-14. Registers Summary (Continued)
REGISTER FUNCTION Reserved Interrupt status register Interrupt enable Interrupt configuration Reserved No-latency read access No-latency read access status status Reserved teletext FIFO program write FIFO program read FIFO Reserved teletext FIFO status/interrupt 01B8 01BF 01C0 01C1 01C2 01C3 01FF 02xx 03xx 1000 1100 1200 1300 1400 1500 1600 1700- 1F00
NOTE: Read only interfaces Write only interfaces Read write host interfaces (where applicable) Read write host interfaces. Write only host interfaces.
2.13 Register Definitions
2.13.1 Vendor
address address address 001h
Address
This field identifies manufacturer device. Address MSB. This field constant 104C.
2.13.2 Device
address address address 003h
Address
This field identifies particular device. Address MSB. This field constant 5140H.
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2.13.3 Subsystem Vendor
address address address 005h
Address
Loaded from [7:0] pins powerup reset Loaded from [7:0] pins powerup reset
This field identifies subsystem manufacturer (for example, board manufacturer). Address MSB. values this field device power reset sampling state Y[7:0] UV[7:0] terminals. Y[7:0] UV[7:0] terminals tied pullup pulldown resisters determine fixed value subsystem vendor default overwritten writing different value register first access this register after reset. This register read-only after first write read.
2.13.4 Subsystem Device
address address address 007h
Address
Loaded from [7:0] pins powerup reset Loaded from A[1:0], VSYN, HSYN, Y[9:8], UV[9:8] pins powerup reset.
This field identifies subsystem device. Address MSB. This field time writeable, similar subsystem vendor
2.13.5 Power State
address address address 008h
Power state
This register both readable writable. When read, this register indicates current power state TVP5040. define four possible power states.
state. Fully This normal operation mode. (default) state. supported state. supported. converters turned internal clock reduced minimum. Power removed.
Writing these bits forces TVP5040 four power states defined above.
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2.13.6 Power Support
address address address 00Ah
this read-only register defines power states that TVP5040 supports. indicates TVP5040 does support optional state defined specification.
2.13.7 Revision
address address address 00Dh
Address
This identifies device hardware revision. Address MSB. This field constant 0101.
2.13.8 Video Input Source Selection
address address address 100h Channel source selection Channel source selection
Reserved
Channel source selection: VI1A selected (default) VI1B selected
Channel V1_1A V1_1B ADC1
Channel source selection: VI2A selected (default) VI2B selected
Luma/Composite Data path
Register Register
Channel V1_2A V1_2B ADC2
Chroma Data path Register
Register Register Bits
Figure 2-37. Video Input Source Selection
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Table 2-15. Analog Channel Video Mode Selection
ADDRESS INPUT(S) SELECTED Composite S-video luma, chroma luma, chroma luma, chroma luma, chroma luma, chroma luma, chroma luma, chroma luma, chroma ADDRESS
2.13.9 Analog Channel Controls
address address address 101h
Reserved
Automatic offset control, channel
Automatic offset control, channel
Automatic gain control
Automatic offset control, channel Automatic offset control disabled Automatic offset control enabled (default) Reserved Offset control frozen Automatic offset control, channel Automatic offset control disabled Automatic offset control enabled (default) Reserved Offset control frozen Automatic gain control: Disabled (fixed gain value) enabled using luma input reference (default) Reserved frozen
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2.13.10 Operation Mode Controls
address address address Reserved 102h Reserved Reserved Color subcarrier frozen Reserved Powerdown mode
TV/VCR mode
TV/VCR mode: Automatic, mode determined internal detection circuit (default) Reserved (nonstandard video) mode (standard video) mode With automatic detection enabled, unstable nonstandard syncs input video will force device into mode. This turns luminance chrominance comb filters turns chroma trap filter.
TV/VCR MODE CM[2:0] XXX/000 1XX/000 10/00 01/00 11/00 11/00 NTSC NTSC STANDARD NTSC NOTE Autodetection switching between VCR/TV Manual programming mode mode
Adaptive comb filter enable. Chrominance comb filter enable. CM[2:0] Chrominance comb filter mode. Luminance filter select. Chrominance filter select. Luminance filter select. change
Chrominance control register Chrominance control register Chrominance control register 7-5. Luminance processing control Register Chrominance control register Luminance control register
Color subcarrier frozen: Color subcarrier increments internally-generated phase increment. (default) GLCO terminal outputs phase increment. Color subcarrier forced nominal value Powerdown mode: Normal operation (default) Power-down mode. A/Ds turned internal clocks reduced minimum.
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2.13.11 Miscellaneous Control
address address address 103h PALI terminal terminal function select output enable HSYN, VSYN, AVID, FID, PALI output enable Reserved Vertical blanking on/off Clock output enable
GPCL terminal function select
GPCL terminal function select: GPCL logic output (default) GPCL logic output GPCL vertical blank output GPCL external sync lock control input When GPCL configured vertical blank output, vertical blanking on/off used activate output. When GPCL configured sync lock control, used force internal PLLs their normal settings. This causes clocks synchronization signals assume nominal values. sync lock control input active high. PALI terminal terminal function select: PALI outputs indicator signal terminal outputs field signal (default) PALI outputs horizontal lock indicator (HLK) terminal outputs vertical lock indicator (VLK) output enable: high impedance (default) active Horizontal sync (HSYN), vertical sync (VSYN), active video indicator (AVID), PALI, output enables: HSYN, VSYN, AVID, PALI, high impedance HSYN, VSYN, AVID, PALI, active This default after reset AVID terminal pulled down during reset default AVID terminal pulled during reset. Vertical blanking on/off control: Vertical blanking (default) Vertical blanking Clock enable: SCLK PCLK outputs high impedance SCLK PCLK outputs enabled This default after reset PREF terminal pulled down during reset default AVID pulled during reset. Table 2-16. Digital Output Control
AVID during reset during reset (TVPOE) (VDPOE) OUTPUT High impedance Active after reset High impedance after reset High impedance High impedance Active times After reset before output enable bits programmed. TVPOE defaults VDPOE defaults After reset before output enable bits programmed. TVPOE defaults VDPOE defaults After both output enable bits programmed After both output enable bits programmed After both output enable bits programmed NOTES
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2.13.12 Software Reset
address address address 105h Reserved Software reset
Software reset: software reset (default) Software reset device software reset applies only microcode internal variables.
2.13.13 Color Killer Threshold Control
address address address Reserved 106h Color killer threshold
Automatic color killer
Automatic color killer: Automatic mode (default) Reserved Color killer enabled. terminals forced zero color state. Color killer disabled Color killer threshold (ref. nominal burst amplitude): 11111 10000 (default) 00000
2.13.14 Luminance Processing Control
address address address Luma bypass mode 107h Pedestal present Reserved Luma bypass during vertical blank
Luminance signal delay with respect chrominance signal
Luma bypass mode select: Input video bypasses chroma trap comb filters. Chroma outputs forced zero. (default) Input video bypasses whole luma processing. data output alternatively data data SCLK rate. output data properly clipped comply CCIR601 coding range. Only valid 10-bit output format (YUV output format register
2-52
Pedestal present: pedestal present analog video input signal (default) Pedestal present analog video input signal Luminance bypass mode during vertical blanking: (default) When luminance bypass enabled, luminance comb notch filters turned chrominance components output video sent zero color state. Luminance bypass occurs duration vertical blanking defined register This feature used prevent distortion test data signals present during vertical blanking interval. Luma signal delay with respect chroma signal pixel clock increments (range pixel clocks): 1111 pixel clocks delay 1011 pixel clocks delay 1000 pixel clocks delay 0000 pixel clocks delay (default) 0011 pixel clocks delay 0111 pixel clocks delay
2.13.15 Luminance Processing Control
address address address Reserved 108h Luminance filter select Reserved Peaking gain Reserved
Luminance filter select: Luminance comb filter enabled (default) Luminance chroma trap filter enabled Peaking gain: Peaking disabled (default) Peaking frequency: Square-pixel sampling rate: NTSC (Combination-N)
ITU-R BT.601 sampling rate: standards Refer Figures 2-16, 2-17 2-18.
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2.13.16 Brightness Control
address address address 109h
Brightness control
Brightness: (bright) (ITU-R BT.601 level) (default) (dark)
2.13.17 Color Saturation Control
address address address 10Ah
Saturation control
Saturation: (maximum) (default) color)
2.13.18 Control
address address address 10Bh control
Hue: 01111111= 00000000= 10000000= degrees degrees (default) -180 degrees
2.13.19 Contrast Control
address address address 10Ch Contrast control
Contrast: (maximum contrast) (default) (minimum contrast)
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2.13.20 Outputs Data Rates Select
address address address Sampling rate 10Dh output code range code format output format
data path bypass
Sampling rate: ITU-R BT.601 sampling rate Square pixel sampling rate (This only applies when video standard autoswitch microcode running) output code range: ITU-R BT.601 coding range ranges from 235. range from 240) Extended coding range range form 254) (default) code format: Offset binary code complement 128) (default) Straight binary code complement) data path bypass: Normal operation. (default) output pins connected decimation filter output, decoder function bypassed. Both busses output data PCLK rate. output pins connected output, decoder function bypassed, video data output. Both busses output data SCLK rate. Reserved output format: 20-bit 4:2:2 (default) Reserved Reserved Reserved 10-bit 4:2:2 UYVYUYVY Reserved Reserved 10-Bit ITU-R interface
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2.13.21 Luminance Control
address address address 10Eh Reserved
Luminance filter select
Luminance filter stopband bandwidth (MHz):
NTSC CCIR601 1.2129 0.8701 0.7383 0.5010 NTSC Square pixel 1.1026 0.7910 0.6712 0.4554 CCIR601 1.2129 0.8701 0.7383 0.5010 Square pixel 1.3252 0.9507 0.8066 0.5474
Luminance filter select[1:0] selects four chroma trap filters produce luminance signal removing chrominance signal from composite video signal. stop band chroma trap filter centered chroma subcarrier frequency with stopband bandwidth controlled control bits. Refer Figure 2-12, 2-13, 2-14 frequency responses filters. control default mode.
2.13.22 Horizontal Sync HSYN Start NTSC/PAL
address address address 116h HSYN start
HSYN Start: -127 pixel clocks -126 pixel clocks -125 pixel clocks 10000000= pixel clocks (defaults) pixel clocks pixel clocks pixel clocks
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2.13.23 Vertical Blanking VBLK Start
address address address 118h VBLK start
VBLK start: lines after start vertical blanking interval line after start vertical blanking interval same time start vertical blanking interval (default) line before start vertical blanking interval lines before start vertical blanking interval Vertical blanking adjustable with respect standard vertical blanking intervals shown Table 2-17. setting this register determines timing GPCL signal when configured output vertical blank(see register 03). setting this register also used determine duration luma bypass function (see register 07). Table 2-17. Vertical Blanking Interval Start
STANDARD NTSC MPAL (Combination-N) (Combination FIELD even even even even START LINE NUMBER 263.5 623.5 260.5 623.5 LINE NUMBER 284.5 23.5 284.5 23.5
2.13.24 Vertical Blanking VBLK Stop
address address address 119h VBLK
VBLK End: lines after vertical blanking interval line after vertical blanking interval same time vertical blanking interval (default) line before vertical blanking interval lines before vertical blanking interval Vertical blanking adjustable with respect standard vertical blanking intervals shown Table 2-17. setting this register determines timing GPCL signal when configured output vertical blank(see register 03). setting this register also used determine duration luma bypass function (see register 07).
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2.13.25 Chrominance Control
address address address 11Ah Color reset Chrominance adaptive comb filter enable (ACE) Chrominance comb filter enable (CE)
Chrominance comb filter mode [2:0] (CM[2:0])
Automatic color gain control
Table 2-18. Chrominance Comb Filter Selection
CM[2] CM[1] CM[0] COMB FILTER SELECTION Comb filter disabled Fixed 3-line comb filter with (1/4, 1/2, 1/4) coefficients Fixed 3-line comb filter with coefficients Fixed 2-line comb filter Adaptive between 3-line (1/4,1/2,1/4) comb filter 2-line comb filter Adaptive between 3-line (1/4,1/2,1/4) comb filter comb filter (default NTSC-M NTSC-443) Adaptive between 3-line (1,0,1) comb filter 2-line comb filter Adaptive between 3-line (1,0,1) comb filter comb filter (default PAL, M-PAL, combination-N PAL)
Color reset: Color subcarrier reset. (default) Color subcarrier reset Color subcarrier reset zero color subcarrier then immediately returns zero. When this set, subcarrier phase reset transmitted GCLO terminal next occurrence specified line (NTSC PAL). Automatic color gain control: enabled (default) Reserved disabled frozen
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2.13.26 Chrominance Control
address address address 11Bh Reserved
Chrominance filter select
Chrominance output bandwidth (MHz):
NTSC CCIR601 1.2129 0.8701 0.7383 0.5010 NTSC Square Pixel 1.1026 0.7910 0.6712 0.4554 CCIR601 1.2129 0.8701 0.7383 0.5010 Square Pixel 1.3252 0.9507 0.8066 0.5474
Refer Figures 2-6, 2-7, frequency responses filters. control default mode.
2.13.27 Interrupt Reset Register
address address address Software init reset Software Init Macrovision Detect Changed Reset Command Ready Reset Field Rate Changed Reset Line Alternation Changed Reset Color Lock Changed Reset Lock Changed Reset TV/VCR Changed Reset 11Ch Macrovision detect changed reset command ready reset Field rate changed reset Line alternation changed reset Color lock changed reset lock changed reset TV/VCR changed reset
effect interrupt register (default) effect interrupt register (default) effect interrupt register (default) effect interrupt register (default) effect interrupt register (default) effect interrupt register (default) effect interrupt register (default) effect interrupt register (default)
Reset software init Reset Macrovision detect changed Reset command ready Reset field rate changed Reset line alternation changed Reset color lock changed Reset lock changed Reset TV/VCR changed
interrupt reset register used external processor reset interrupt status bits interrupt register Bits loaded with allows corresponding interrupt status reset Bits loaded with have effect interrupt status bits.
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2.13.28 Interrupt Enable Register
address address address Software init occurred 11Dh Macrovision detect changed command ready Field rate changed Line alternation changed Color lock changed lock changed TV/VCR changed
Software init Macrovision Detect Changed Command Ready Field Rate Changed Line Alternation Changed Color Lock Changed Lock Changed TV/VCR Changed
Software init interrupt source masked (default) Macrovision detect interrupt source masked (default) command interrupt source masked (default) Field rate interrupt source masked (default) Line alternation interrupt source masked (default) Color lock interrupt source masked (default) lock interrupt source masked (default) TV/VCR interrupt source masked (default)
Software init interrupt source enabled Macrovision detect interrupt source enabled command interrupt source enabled Field rate interrupt source enabled Line alternation interrupt source enabled Color lock interrupt source enabled lock interrupt source enabled TV/VCR interrupt source enabled
interrupt enable register used external processor mask unnecessary interrupt sources interrupt Bits loaded with allows corresponding interrupt condition generate interrupt external pin. Conversely bits loaded with masks corresponding interrupt condition from generating interrupt external pin. Note this register only affects external terminal, does affect bits interrupt status register. given condition appropriate status register cause interrupt external pin. determine this device driving interrupt terminal, either perform logical interrupt status register with interrupt enable register check state interrupt interrupt active register.
2.13.29 Interrupt Configuration Register
address address address 11Eh Reserved Interrupt Polarity Interrupt active low. Interrupt active high. (default) Interrupt polarity Must same interrupt polarity interrupt configuration register address
interrupt configuration register used configure polarity interrupt external interrupt terminal. Note that when interrupt configured active low, terminal driven when active 3-state when inactive (open-collector). Conversely, when interrupt configured active high, driven high active driven inactive.
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2.13.30 Video Input Source Selection
address address address Reserved 120h Reserved Decimation filter bypass enable Reserved Reserved Reserved Chroma channel select Luma/composite channel select
Decimation filter bypass: Bypass disabled (default) Bypass enabled Chroma Channel Select: ADC1 selected (default) ADC2 selected Luma/composite channel select: ADC1 selected (default) ADC2 selected also: Video input source selection register, address
2.13.31 Lock Speed Select
address address address 125h Reserved Lock speed
Lock speed: Fast lock disabled (default) Fast lock enabled
2.13.32 Crystal Frequency
address address address 126h Reserved Crystal frequency
Crystal frequency: 14.31818 (default)
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2.13.33 Video Standard
address address address 128h Reserved Video Standard
Video standard: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Autoswitch mode NTSC square pixel NTSC ITU-R BT.601 square pixel ITU-R BT.601 square pixel ITU-R BT.601 (Combination-N) square pixel (Combination-N) ITU-R BT.601 NTSC 4.43 square pixel NTSC 4.43 ITU-R BT.601
With autoswitch code running, user force device operate particular video standard mode sampling rate writing appropriate value into this register.
2.13.34 NonVIP Program Write
address address address
Program Write Data
host interface enabled, program written nonVIP program write register address host interface enabled, program written FIFO location FIFO address space.
2.13.35 Microprocessor Reset Clear
address address address 17Fh Data
write with data this register must performed restart internal microprocessor after completion microcode download program after microcode upload from program RAM.
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2.13.36 Major Software Revision Number
address address address 180h
Microcode major revision number
This register contains major software revision number microcode.
2.13.37 Status Register
address address address Peak white detect status 181h Line-alternating status Field rate status Lost lock detect status Color subcarrier lock status Vertical sync lock status Horizontal sync lock status TV/VCR status
Peak white detect status: Peak white detected. Peak white detected. Line-alternating status: line-alternating Line alternating Field rate status: Lost lock detect status: lost lock since status register last read. Lost lock since status register last read. Color subcarrier lock status: Color subcarrier locked. Color subcarrier locked. Vertical sync lock status: Vertical sync locked. Vertical sync locked. Horizontal sync lock status: Horizontal sync locked. Horizontal sync locked. TV/VCR status:
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2.13.38 Status Register
address address address 182h switch polarity Field sequence status offset status Reserved
Reserved
Macrovision detection
switch polarity first line field: switch zero Color burst phase degree) switch (Color burst phase degree) Field sequence status: Even field field Automatic gain offset status: Automatic gain offset frozen. Automatic gain offset frozen. Macrovision detection: copy protection pulses/pseudosyncs present pulses/pseudosyncs present 2-line color striping present pulses/pseudosyncs present 4-line color striping present
2.13.39 Status Register
address address address 183h gain
gain (step size 0.831%):
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2.13.40 Status Register
address address address 184h
Subcarrier horizontal (SCH) phase
(color subcarrier phase falling edge horizontal sync line field; step size deg/256): 0.00 degree 1.41 degree 2.81 degree 357.2 degree 358.6 degree
2.13.41 Interrupt Status Register
address address address Software init 185h Macrovision detect changed command ready Field rate changed Line alternation changed Color lock changed lock changed TV/VCR changed
Software init Macrovision detect changed command ready Field rate changed Line alternation changed Color lock changed lock changed TV/VCR changed
Software init completed (default) Macrovision detect status changed (default) ready accept command (default) Field rate changed (default) Line alternation changed (default) Color lock status changed (default) lock status changed (default) TV/VCR status changed (default)
Software init completed Macrovision detect status changed. ready accept command Field rate changed Line alternation changed Color lock status changed lock status changed TV/VCR mode detect changed
interrupt status register polled external processor determine interrupt source interrupt After interrupt condition set, reset writing interrupt reset register subaddress with appropriate bit.
2.13.42 Interrupt Active Register
address address address 186h Interrupt
Interrupt
Interrupt active.
Interrupt active (default).
interrupt status register polled external processor determine interrupt active.
2-65
2.13.43 Minor Software Revision Number
address address address 187h
Microcode minor revision number
This register contains minor revision number TVP5040 microcode. This number from
2.13.44 Status Register
address address address Autoswitch mode 188h Reserved Reserved Video Standard Sampling Rate
This register contains information about detected video standard sampling rate which device currently operating. When autoswitch code running, this register must tested determine which video standard been detected. Autoswitch mode: Stand-alone (forced video standard) mode Autoswitch mode Video standard: NTSC (Combination-N) NTSC 4.43 101-111 Reserved Sampling rate: Squire pixel ITU-BT.601
2.13.45 Vertical Line Count
address address address 189h Reserved
Vertical Line Count
Vertical line count MSB: Vertical line count bits [9:8]
2-66
2.13.46 Vertical Line Count
address address address 18Ah
Vertical Line Count
Vertical line count LSB: Vertical line count bits [7:0] These registers read combined extract current vertical line count. This used with nonstandard video signals such fast-forward rewind modes synchronize downstream video circuitry.
2.13.47 Analog
address address address 018Bh Analog
This register identifies analog
2.13.48 Digital
address address address 018Ch Digital
This register identifies digital
2.13.49 NonVIP Program Read
address address address
Program Read Data
program read nonVIP program read register address host interface enabled FIFO location FIFO address space host interface enabled.
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2.13.50 Filter Parameters
address address address 190h 194h ADDRESS
Filter Mask_1[3:0] Filter Mask_2[3:0] Filter Mask_3[3:0] Filter Mask_4[3:0] Filter Mask_5[3:0]
Filter Pattern_1[3:0] Filter Pattern_2[3:0] Filter Pattern_3[3:0] Filter Pattern_4[3:0] Filter Pattern_5[3:0]
NABTS system, packet prefix consists five bytes: Each byte contains four data bits interlaced with four Hamming protection bits. Pattern_1[3:0] corresponds P1[7], P1[5], P1[3], P1[1] Pattern_2[3:0] corresponds P2[7], P2[5], P2[3], P2[1] Pattern_3[3:0] corresponds P3[7], P3[5], P3[3], P3[1] Pattern_4[3:0] corresponds CI[7], CI[5], CI[3], CI[1] Pattern_5[3:0] corresponds PS[7], PS[5], PS[3], PS[1] (Packet Address) (Packet Address) (Packet Address) (Continuity Index) (Packet Structure)
system (PAL NTSC), magazine address group consists bytes. bytes contain three bits magazine number (M[2:0]) bits address (R[4:0]), interlaced with eight Hamming protection bits. Pattern_1[3:0] corresponds R[0], M[2], M[1], M[0] Pattern_2[3:0] corresponds R[4], R[3], R[2], R[1] Pattern_3[3:0] ignored Pattern_4[3:0] ignored Pattern_5[3:0] ignored (Magazine LSBit) (Upper bits address)
mask bits enable filtering using corresponding pattern register. example, Mask_1 means that module compares Nibble_1 pattern register first data transaction. Mask_1 means that module ignores first data transaction. NOTE: filter parameters only written read when both filter filter enable bits register 9Bh) When reading values, values must read consecutively, starting with first value. These registers hold search parameters filter parameters used parse first five bytes NABTS Teletext transactions first bytes transactions. These bytes teletext expected always contain four data bits interlaced with four Hamming protection bits. protection bits ignored filter.
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2.13.51 Filter Parameters
address address address 195h 199h ADDRESS
Filter Mask_1[3:0] Filter Mask_2[3:0] Filter Mask_3[3:0] Filter Mask_4[3:0] Filter Mask_5[3:0]
Filter Pattern_1[3:0] Filter Pattern_2[3:0] Filter Pattern_3[3:0] Filter Pattern_4[3:0] Filter Pattern_5[3:0]
NABTS system, packet prefix consists five bytes: Each byte contains four data bits interlaced with four Hamming protection bits. Pattern_1[3:0] corresponds P1[7], P1[5], P1[3], P1[1] Pattern_2[3:0] corresponds P2[7], P2[5], P2[3], P2[1] Pattern_3[3:0] corresponds P3[7], P3[5], P3[3], P3[1] Pattern_4[3:0] corresponds CI[7], CI[5], CI[3], CI[1] Pattern_5[3:0] corresponds PS[7], PS[5], PS[3], PS[1] (Packet address) (Packet address) (Packet address) (Continuity index) (Packet structure)
system (PAL NTSC), magazine address group consists bytes. bytes contain three bits magazine number (M[2:0]) five bits address (R[4:0]), interlaced with eight Hamming protection bits. Pattern_1[3:0] corresponds R[0], M[2], M[1], M[0] Pattern_2[3:0] corresponds R[4], R[3], R[2], R[1] Pattern_3[3:0] ignored Pattern_4[3:0] ignored Pattern_5[3:0] ignored (Magazine LSBit) (Upper bits address)
mask bits enable filtering using corresponding pattern register. example, Mask_1 means that module compares Nibble_1 pattern register first data transaction. Mask_1 means that module ignores first data transaction. NOTE: Filter parameters only written read when both Filter Filter enable bits register 9Bh) When reading values, values must read consecutively, starting with Filter parameter values. These registers hold search parameters Filter parameters used parse first five bytes NABTS teletext transactions first bytes transactions. These bytes teletext expected always contain four data bits interlaced with four Hamming protection bits. protection bits ignored filter.
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2.13.52 Error Filtering Enables
address address address 19Ah Error Enable Parity Error Enable Teletext Parity Error Enable Hamming Error Enable
Reserved
error enable parity error enable Teletext parity error enable Hamming error enable
disable (default) disable (default) disable (default) disable (default)
enable enable enable enable
These bits allow module discard transactions based errors. Hamming error enable allows error correction detection Hamming encoded bytes. teletext parity error enable allows discard teletext transactions with parity errors. parity error enable allows discard closed caption transactions with parity errors. error enable allows discard teletext transactions with longitudinal parity errors.
2.13.53 Transaction Processing Enables
address address address Reserved 19Bh Filter enable Filter enable field enable even field enable Teletext enable
Filter enable Filter enable field enable even field enable Teletext enable
disable (default) disable (default) disable (default) disable (default) disable (default)
enable enable enable enable enable
These bits used enable disable certain features. teletext enable allows module receive teletext data. this outputs from remain idle while teletext data present. even field enable field enable allow receive closed caption data. filter enable allows module parse data based values filter parameters register. filter enable allows module parse data based values filter parameters register.
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2.13.54 Control Register
address address address 1A0h Full-Field Enable Custom Framing Code Enable Mode
Reserved
Full field enable Custom sync enable mode
search after area default sync pattern Closed caption DISABLED NABTS
search lines after sync pattern register Closed caption ENABLED
control register allows operating parameters controlled. Note that mode selection independent PAL/NTSC mode. This effectively controls default framing code data rate. Closed caption affected lines lines (but NABTS/WST). NTSC data search Line combination-N Line custom framing code affects teletext data only-closed caption data always uses default sync pattern.
2.13.55 Line Enable Registers
address address address 1A1h 1A2h Enable line 17/280 (14/327) Enable line 25/288 (22/335) Enable line 16/279 (13/326) Enable line 24/287 (21/334) Enable line 15/278 (12/325) Enable line 23/286 (20/333) Enable line 14/277 (11/324) Enable line 22/285 (19/332) Enable line 13/276 (10/323) Enable line 21/284 (18/331) Enable line 12/275 (9/322) Enable line 20/283 (17/330) Enable line 11/274 (8/321) Enable line 19/282 (16/329) Enable line 10/273 (7/320) Enable line 18/281 (15/328)
Line Enable Register
Line Enable Register
NOTE: Line numbers parenthesis refer Line systems
Line enable
Search line
Search line data
both only full field modes, vertical interval lines individually enabled disabled. Only lines that enabled searched selected type teletext data. This allows some amount filtering physical location basis. closed caption data enabled, this overrides enable/disable line (22). full field mode enabled, lines after vertical interval searched selected type teletext data. registers initialized 0x00 reset.
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2.13.56 Sync Pattern Register
address address address 1A3h
Framing Code [7:0]
custom sync control register, sync comparator uses contents sync pattern register pattern teletext framing code. Otherwise, default sync patterns used. Relative sync pattern register, inc
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