Low-power supply. +125 industrial temperature range. 272-pin ball grid

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Low-power supply. +125 industrial temperature range. 272-pin ball grid

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TTSV02622 STS-24 Backplane Transceiver
Low-power supply. +125 industrial temperature range. 272-pin ball grid array (PBGA) package.
Allows wide range applications SONET network termination application well generic data moving high-speed backplane data transfer. Clock/data recovery (CDR) function high-speed serial backplane data transfer. function uses Agere Systems Inc. proven Mbits/s serial interface core. Two-channel function provides Mbits/s serial interface channel total chip bandwidth 1.24 Gbits/s (full duplex). Low-voltage differential signaling (LVDS) I/Os reference clock signals. data multiplexing/demultiplexing (MUX/ deMUX) 77.76 byte-wide data processing. meets jitter tolerance specification ITU-T recommendation G.958. Powerdown option receiver perchannel basis. Pseudo-SONET protocol including A1/A2 framing. SONET scrambling descrambling required ones density (optional). Selected transport overhead (TOH) bytes insertion detection interdevice communication serial link. Streamlined pointer processor (pointer mover) frame alignment. FIFOs alignment incoming data reference clock. FIFOs optionally align incoming data across channels synchronous transport signal STS-24 operation dual STS-12 format). Independent data stream enables pseudoSONET processor. Supports STS-12/STS-24 redundancy either software hardware control protection switching applications.
Description
TTSV02622 support 1.24 Gbits/s interface backplane connections. 1.24 Gbits/s interface implemented dual Mbits/s LVDS links. macrocell used clock/data recovery (CDR) MUX/deMUX between 77.76 bytewide internal data buses Mbits/s external serial links. Each Mbits/s serial link uses pseudo-SONET protocol. SONET A1/A2 framing used link locating frame location. link also scrambled using standard SONET scrambler definition ensure proper transitions link improved performance. Selectable transport overhead (TOH) bytes insertable transmit direction. bytes transparently passed through device, bytes inserted serial link. addition, certain microprocessor unit (MPU) selectable bytes passed through transparently while insert mode. Elastic buffers (FIFOs) used align each incoming STS-12 link core 77.76 clock frame. These FIFOs will absorb delay variations between Mbits/s links timing skews between cards along backplane traces. greater variations, streamlined pointer processor (pointer mover) within device will align frames regardless their incoming frame position. TTSV02622 supports dual STS-12 mode operation input/output ports. STS-24 also supported, must received dual STS-12 format. When operating dual STS-12 mode, each independent byte streams carries entire STS-12 within Figure page reveals byte ordering individual STS-12 streams.
TTSV02622 STS-24 Backplane Transceiver
Description (continued)
STS-12 STS-12
STS-24 DUAL STS-12 FORMAT
DUAL STS-12
STS-12 STS-12
Figure Byte Ordering Input/Output Interface STS-12 Mode
Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
Table Contents
Contents Page
Features Description. Information Synchronization Block Interface. Line Interface. Architecture Powerdown Mode. Supervisory Features Test Features Transmit Direction (Line Backplane) Transport Overhead Serial Link A1/A2 Frame Insert Corruption Calculation Insertion Stream Disable Scrambler. Receiver Block. Framer Subblock (Backplane Line). Calculate Descramble (Backplane Line) Internal Parity Generation FIFO Subblock (Backplane Line) Pointer Mover Subblock (Backplane Line). Miscellaneous Functions K1/K2, A1/A2 Handling C1J1 Outputs. Registers Definition Register Types. Register Map. Register Descriptions Absolute Maximum Ratings. Handling Precautions Recommended Operating Conditions Thermal Characteristics. Power Consumption (Advance). Electrical Characteristics Propagation Delay Specifications. LVDS LVDS Receiver Buffer Capabilities Clock Data Recovery (CDR). Input Data Jitter Tolerance Generated Output Jitter PLL. Input Reference Clock Timing Characteristics Interface Timing. Outline Diagram. 272-Pin PBGA. Ordering Information.
Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
List Figures
Contents Page
Figure Byte Ordering Input/Output Interface STS-12 Mode Figure Diagram 272-Pin PBGA (Bottom View). Figure Suggested Schematic Reference Voltages. Figure Alignment STS-12 Streams Figure Interior View TTSV02622 Figure Interconnect Streams FIFO Alignment. Figure Transmitter Block Figure Receiver Block Figure Framer State Machine. Figure Pointer Mover State Machine Figure LVDS Driver Receiver Associated Internal Components Figure LVDS Driver Receiver Figure LVDS Driver Figure Input Parallel Port Timing Figure Transmitter Transport Delay. Figure Output Parallel Port Timing Figure Protection Switch Timing. Figure Input Serial Port Timing. Figure Output Serial Port Timing Figure Write Transaction Figure Read Transaction
Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
List Tables
Contents Page
Table Assignments 272-Pin PBGA Number Order Table Assignments 272-Pin PBGA Signal Name. Table Descriptions Table Valid Starting Positions STS-MC. Table C1J1 Functionality. Table Register Table Register Description Table Absolute Maximum Ratings. Table Handling Precautions Table Recommended Operating Conditions Table Thermal Resistance-Junction Ambient Table Power Consumption (Advance). Table LVTTL Electrical Characteristics Table LVDS Receiver Data* Table LVDS Receiver Data* Table LVDS Driver Data*. Table LVDS Driver Data*. Table LVDS Driver Reference Data Table Jitter Tolerance. Table Input Parallel Port Timing Requirements. Table Transmitter Transport Delay Timing Requirements. Table Output Parallel Port Timing Requirements Table Protection Switch Timing Requirements. Table Input Serial Port Timing Requirements. Table Output Serial Port Timing Requirements. Table Write Transaction Timing Requirements Table Read Transaction Timing Requirements
Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
Information
BALL CORNER
Figure Diagram 272-Pin PBGA (Bottom View)
Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
Information (continued)
Table Assignments 272-Pin PBGA Number Order Signal Name PROT_SWITCH_A TOH_INA TOH_OUTA DOUTA7 DOUTA4 DOUTA0 DOUTA_C1J1 DOUTB7 DOUTB6 Signal Name TRSTN TSTMD SCANEN PROT_SWITCH_C TOH_INB TOH_OUTB DOUTA6 DOUTA3 DOUTA_PAR DOUTB5 DOUTB4 DOUTB3 Signal Name LVDS_EN TX_TOH_CKEN TOH_CLK RX_TOH_CKEN RX_TOH_FP DOUTA5 DOUTA2 DOUTA_SPE DOUTB2 DOUTB1 DOUTB0 Signal Name DOUTA1 DOUTB_PAR DOUTB_SPE DOUTB_C1J1
Note: refers connect. connect pins designated.
Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
Information (continued)
Table Assignments 272-Pin PBGA Number Order (continued) Signal Name STS_INA_P STS_INA_N CTAP_REFA STS_INB_P STS_INB_N CTAP_REFB Signal Name STS_OUTA_P STS_OUTA_N PLL_VDDA PLL_VSSA Signal Name STS_OUTB_P STS_OUTB_N REF10 REF14 LVDS_RESH LVDS_RESL SYS_CLK SYS_FP LINE_FP Signal Name DINA7 DINA6 DINA5 DINA4 DINA3 DINA2 DINA1 DINB7 DINA0 DINA_PAR TSTMODE BYPASS RESETRN RESETTN DINB6 DINB5 DINB4 DINB3
Note: refers connect. connect pins designated.
Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
Information (continued)
Table Assignments 272-Pin PBGA Number Order (continued) Signal Name TSTCLK TSTSHFTLD ETOGGLE TSTMUX3S CPU_ADDR6 CS_N CPU_DATA7 CPU_DATA3 DIND4 DINB2 DINB1 DINB0 Signal Name MRESET ECSEL LOOPBKEN TSTMUX6S TSTMUX2S CPU_ADDR5 CPU_ADDR2 RD_WRN INT_N CPU_DATA6 CPU_DATA2 DINB_PAR Signal Name EXDNUP TSTPHASE TSTMUX8S TSTMUX5S TSTMUX1S CPU_ADDR4 CPU_ADDR1 RST_N CPU_DATA5 CPU_DATA1 Signal Name TSTMUX7S TSTMUX4S TSTMUX0S CPU_ADDR3 CPU_ADDR0 HIZ_N CPU_DATA4 CPU_DATA0
Note: refers connect. connect pins designated.
Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
Information (continued)
Table Assignments 272-Pin PBGA Signal Name Signal Name BYPASS CPU_ADDR0 CPU_ADDR1 CPU_ADDR2 CPU_ADDR3 CPU_ADDR4 CPU_ADDR5 CPU_ADDR6 CPU_DATA0 CPU_DATA1 CPU_DATA2 CPU_DATA3 CPU_DATA4 CPU_DATA5 CPU_DATA6 CPU_DATA7 CS_N CTAP_REFA CTAP_REFB DINA_PAR DINA0 DINA1 DINA2 DINA3 DINA4 DINA5 DINA6 DINA7 DINB_PAR DINB0 DINB1 DINB2 DINB3 DINB3 Signal Name DINB4 DINB5 DINB6 DINB7 DIND4 DOUTA_C1J1 DOUTA_PAR DOUTA_SPE DOUTA0 DOUTA1 DOUTA2 DOUTA3 DOUTA4 DOUTA5 DOUTA6 DOUTA7 DOUTB_C1J1 DOUTB_PAR DOUTB_SPE DOUTB0 DOUTB1 DOUTB2 DOUTB3 DOUTB4 DOUTB5 DOUTB6 DOUTB7 ECSEL ETOGGLE EXDNUP HIZ_N INT_N Signal Name LINE_FP LOOPBKEN LVDS_EN LVDS_RESH LVDS_RESL MRESET Signal Name
Note: refers connect. connect pins designated.
Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
Information (continued)
Table Assignments 272-Pin PBGA Signal Name (continued) Signal Name Signal Name Signal Name STS_OUTB_P SYS_CLK SYS_FP TOH_CLK TOH_INA TOH_INB TOH_OUTA TOH_OUTB TRSTN TSTCLK TSTMD TSTMODE TSTMUX0S TSTMUX1S TSTMUX2S TSTMUX3S TSTMUX4S TSTMUX5S TSTMUX6S TSTMUX7S TSTMUX8S TSTPHASE TSTSHFTLD TX_TOH_CKEN Signal Name
PLL_VDDA PLL_VSSA PROT_SWITCH_A PROT_SWITCH_C RD_WRN REF10 REF14 RESETRN RESETTN RST_N RX_TOH_CKEN RX_TOH_FP SCANEN STS_INA_N STS_INA_P STS_INB_N STS_INB_P STS_OUTA_N STS_OUTA_P STS_OUTB_N
Note: refers connect. connect pins designated.
Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
Information (continued)
Table Descriptions N18, N19, N20, P17, P18, P19, P20, R18, T17, T18, T19, T20, U18, U19, A15, B15, C15, A16, B16, C16, D16, Symbol DINA[7:0] Type Pull-up Pull-up Pull-up Pull-up HI-Z/ Pull-up HI-Z/ Pull-up HI-Z/ Pull-up HI-Z/ Pull-up HI-Z/ Pull-up HI-Z/ Pull-up HI-Z/ Pull-up HI-Z/ Pull-up Pull-up Pull-up Pull-up Pull-up HI-Z/ Pull-up Description Input parallel transmitter
DINA_PAR DINB[7:0]
Parity input transmitter Input parallel transmitter
DINB_PAR DOUTA[7:0]
Parity input transmitter Output parallel receiver
DOUTA_PAR
Parity output parallel receiver
DOUTA_SPE
signal output parallel receiver
DOUTA_C1J1
C1J1 signal output parallel receiver
A19, A20, B18, B19, B20, C18, C19,
DOUTB[7:0]
Output parallel receiver
DOUTB_PAR
Parity output parallel receiver
DOUTB_SPE
signal output parallel receiver
DOUTB_C1J1
C1J1 signal output parallel receiver
TOH_CLK TOH_INA TOH_INB TX_TOH_CKEN TOH_OUTA
serial links clock MHz- 77.76 MHz). serial link input transmitter serial link input transmitter serial link clock enable. serial link output receiver
Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
Information (continued)
Table Descriptions (continued) Symbol TOH_OUTB Type HI-Z/ Pull-up HI-Z/ Pull-up HI-Z/ Pull-up Pull-up Pull-up I/Pull-Up Pull-up SCHMITT Pull-up Pull-up Pull-up Pull-up Pull-up Open Drain Pull-down/ SCHMITT Description serial link output receiver
RX_TOH_CKEN
serial link clock enable.
RX_TOH_FP
serial link frame pulse.
U11, V11, W11, Y11, U12, V12, W12,
STS_INA_P STS_INA_N STS_INB_P STS_INB_N STS_OUTA_P STS_OUTA_N STS_OUTB_P STS_OUTB_N CTAP_REFA CTAP_REFB CPU_DATA[7:0]
LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS
LVDS input receiver LVDS input receiver LVDS input receiver LVDS input receiver LVDS output transmitter LVDS output transmitter LVDS output transmitter LVDS output transmitter LVDS input center (use 0.01 GND). LVDS input center (use 0.01 GND). Central processing unit (CPU) interface data bus.
CPU_ADDR[6:0] RD_WRN CS_N
interface address bus. interface read/write. Chip select.
SYS_FP LINE_FP SYS_CLK PROT_SW_A PROT_SW_C INT_N
System frame pulse transmitter section. Line frame pulse receiver section. System clock (77.76 MHz). Protection switching control signal. Protection switching control signal. Interrupt output.
RST_N
Global reset.
Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
Information (continued)
Table Descriptions (continued) Symbol HIZ_N Type Description
PLL_REF REF10 REF14 LVDS_RESH LVDS_RESL PLL_VDDA PLL_VSSA TCLK TRSTN TSTMD SCANEN LVDS_EN TSTMODE BYPASS TSTCLK MRESET RESETRN RESETTN TSTSHFTLD
Global 3-state control. Pull-up/ SCHMITT Reference GND). reference LVDS reference block. Figure page reference LVDS reference block. Figure page Resistance high input (use LVDS_RESL input). Resistance input (use LVDS_RESH input). Temperature-sensing diode (anode Temperature-sensing diode (cathode analog (3.3 analog (GND). JTAG clock input. Pull-up JTAG data input. Pull-up JTAG mode select input. Pull-up JTAG data output. JTAG reset input. Pull-up Scan test mode input. Pull-up Scan mode enable input. Pull-Up LVDS enable used during boundary scan (B-S). Pull-up Enables test mode. Pull-down Enables bypassing clock synthesis Pull-down with TSTCLK. Test clock emulation clock during Pull-down bypass. Test mode reset. Pull-down Resets receiver clock division counter. Pull-up Resets transmitter clock division counter. Pull-up Enables test mode control register shifting-in Pull-down selected tests serial port. Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
Information (continued)
Table Descriptions (continued) Symbol ECSEL EXDNUP ETOGGLE LOOPBKEN TSTPHASE Type Pull-down Pull-down Pull-down Pull-Down Pull-down Description Enables external test control clock phase selection. Direction phase change. Moves 622.08 clock selection phase positive pulse. Enables Mbits/s loopback mode. Controls bypass PLL-generated phases with low-speed phases. Test mode output port.
TSTMUX[8:0]S D13, D17, H17, N17, U13, U17, J10, J11, J12, K10, K11, K12, L10, L11, L12, M10, M11, D11, D15, F17, L17, R17, U10,
Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
Information (continued)
2.32 REF10 REF14
1.91
1.43
Figure Suggested Schematic Reference Voltages
Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
Synchronization
incoming data from high-speed interface (HSI) separated into STS-12 channels slice Example TTSV02622 alignment.
STREAM STREAM STREAM STREAM
Figure Alignment STS-12 Streams There also provision allow certain streams disabled (i.e., producing interrupts affecting synchronization). These streams enabled later time without disrupting other streams.
Block Interface
block should provide independent 77.76 interfaces. Each interface will consist byte-wide data stream recovered clock. There requirement alignment since SONET type framing will take place inside TTSV02622 device.
Line Interface
line side will receive/transmit frame-aligned streams STS-12 data. frames transmitted line will aligned line frame pulse, which will provided TTSV02622. frames received from line will aligned system frame pulse, which will supplied TTSV02622.
Architecture
TTSV02622 composed transmit (Tx) receive (Rx) sections. device (see Figure page receives byte-wide data streams 77.76 (STS-12 rate) associated clock. incoming streams framed, descrambled before they then written into FIFO that absorbs phase delay variations allows shift system clock. then extracted sent serial ports. pointer interpreter will then synchronous transport signal (STS) synchronous payload envelopes (SPEs) into small elastic store from which pointer generator will produce byte-wide STS-12 streams data that aligned line timing pulse.
Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
Architecture (continued)
INPUT LINE LBPK (SOFT CTL) PROC. DUAL CHANNEL TRANSMITTER PROCESSOR FRAME PROC. CH#1 (MACRO) LVDS
INPUT DATA(8) PARITY(1) INPUT PROCESSOR
INPUT DATA(8) PARITY(1)
FRAME PROC.
CH#2 (MACRO)
LVDS
SYSTEM FRAME SYSTEM CLOCK (77.76 MHz) LINE FRAME PROT SWITCH
CH#1 SOFT SOFT FRAME CLOCK 77.76 FDBK
77.76
CLKs
DATA(8)/PARITY(1) SPE(1) C1J1(1) OUTPUT
CH#1 77.76 (MACROCELL) CH#2 SOFT
LVDS
DATA(8)/PARITY(1) SPE(1) C1J1(1) OUTPUT
POINTER MOVER STS-24 FIFO
77.76
CH#2 (MACROCELL)
LVDS
LVDS LPBK (SOFT CTL)
SOFT SOFT
OUTPUT OUTPUT
SOFT
CH#1 CH#2
PROCESSOR
DUAL CHANNEL RECEIVER
SOFT FRAME INTERFACE (ASYNC) LINE SIDE HIZ_N RST_N (HARD RST) CS_N RD/WR_N ADDR DATA INT_N LVDS SIDE
Figure Interior View TTSV02622 Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
Architecture (continued)
alignment FIFO allows transfer data system clock. FIFO sync block allows system configured allow frame alignment multiple slightly varying data streams (see FIFO Sync Subblock (Backplane Line) section page 28).
STS-12 STREAM STS-12 STREAM FIFO SYNC
Figure Interconnect Streams FIFO Alignment pointer mover (see Pointer Mover Subblock (Backplane Line) section page responsible mapping incoming frames line frames. pointer mover pseudo SONET implementation which streamlined wherever possible minimize gate count complexity. result, only capable correcting single bit, nonrepeating pointer errors. This pointer mover (i.e., interpreter, elastic store, generator) will capable handling intra STS-12 concatenation well inter STS-12 concatenation long STS-12 streams frame aligned.
Powerdown Mode
Powerdown mode should entered when corresponding channel disabled. Channels independently enabled disabled under software control. Note: PROT FUNC STS-12 mode. When channel disabled, disabled channel clock data recovery module powered down, well LVDS buffers buffers that channel. When channels powered down, module also powered down. addition, been added enable LVDS pins during boundary scan. This should pulled high board functional operation.
Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
Supervisory
Parallel integrity: Parity error checking implemented each four parallel input buses. Even parity supported controlled from interface (per device control). Upon detection error, interrupt raised. This feature per-channel basis. serial port integrity: There even parity generation each four serial output ports. There even parity error checking each four serial input ports. There parity imbedded frame. occupies most significant location byte STS-1. Upon detection error, interrupt raised. This feature per-channel basis. LVDS link integrity: There parity generation each four LVDS output channels. There also performance monitoring each four LVDS input channels, implemented parity error checking. Upon detection error, counter incremented (one count errored bit) interrupt raised. counter bits wide plus overflow indicator bit. This feature per-channel basis. Framer monitor: framer receive direction will report loss frame (LOF) interrupt, well count errored frame count. interrupt must clearable long channel state. addition, errored frame count must represent errored frames, should increment more than once frame even there multiple errors. Receiver internal path integrity: There even parity generation receiver section (after descrambler). There also even parity error checking receiver section (before output). Upon detection error, interrupt raised. This feature per-channel basis. Pointer mover performance monitoring: There pointer mover performance monitoring receiver section. Alarm indication signal path (AIS-P) concatenation reported, well elastic store overflows. AIS-P implemented STS-1 interrupt. case concatenated payload, only interrupt associated with head group will active. Concatenation reported STS-1 status, high when STS-1 concatenated; when concatenated. Elastic store overflow will generate interrupt STS-1 basis. FIFO aligner monitoring: There monitoring FIFO aligner operating point, upon deviating from nominal operating point FIFO more than user-programmable threshold values (min threshold values), interrupt raised. Threshold values defined device, flags channel. Frame offset monitoring: There monitoring frame offset between enabled channels (disabled channels must interfere with monitoring). Monitoring performed continuously. Upon exceeding maximum allowed frame offset bytes) between enabled channels, interrupt raised. interface monitoring: There monitoring potential write cycles that occur when operating write protect mode. Upon detecting write access application specific integrated circuit (ASIC) when device write protect mode, interrupt raised (W-LOCK flag).
Note: parallel output ports, parity calculated over 8-bit data C1J1 lines.
Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
Test
Line loopback: There line loopback feature allowing user perform loopback line side (per device control). line frame signal used pointer mover automatically replaced system frame signal when operating line loopback mode. LVDS loopback: There LVDS loopback feature allowing user perform loopback LVDS side (per device control). A1/A2 error insert: There frame error inject feature, transmitter section, allowing user replace framing bytes A1/A2 (only last byte first byte) with selectable A1/A2 byte value selectable number consecutive frames. number consecutive frames alter specified 4-bit field, while A1/A2 value specified 8-bit fields. error insert feature per-channel basis, A1/A2 values 4-bit frame count value per-device basis. error insert: There error insert feature, transmitter section, allowing user insert errors user selectable bits byte. Errors created simply inverting values. Bits invert will specified through 8-bit register (each associated with eight bits). insert error, software will first bits transmitter error insert mask. Then, per-channel basis, software will write error insert command. insertion circuitry performs rising edge detect bit, will issue corruption signal next frame, frame only. This feature per-channel basis. serial output port parity error insert: There parity error inject feature, receive section, allowing user invert parity each serial output port. This feature inserts single error. This feature per-channel basis. Parallel output parity error insert: There parity error inject feature, receive section, allowing user invert parity lines associated with each output parallel buses. This feature inserts single error. This feature per-channel basis. This feature supports both even parities. Scrambler/descrambler disable: There scrambler/descrambler disable feature, allowing user disable scrambler transmitter descrambler receiver. calculated transmitter receiver) nonscrambled data stream. This feature device.
Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
Transmit Direction (Line Backplane)
Each insert block receives byte-wide 77.76 data from line, which nominally represents STS-12 streams Transport overhead bytes then optionally inserted into these streams streams forwarded HSI. byte timing pulses required isolate individual overhead bytes (e.g., D1-D12, etc.) generated internally based Frame_Sync received from system (SYS_FP).
insertion optional corruption. pass through transparently. calculation (after scrambling), insertion optional corruption (before scrambling). Optional insert. Optional S1/M0 insert. Optional E1/F1/E2 insert. Optional section line data communication channel (DCC, D1-D12) insertion (for intercard communications channel). Scrambling outgoing data stream with optional scrambler disabling. Optional stream disabling.
streams operate byte wide 77.76 (622 Mbits/s) modes.
EVEN/ODD PARITY (SOFT CTL) FLAG (SOFT REG)
CLOCK SERIAL (COMMON DATA
CLOCK (COMMON FLAG (SOFT REG)
ERROR ERROR MASK INSERT (SOFT REG) (SOFT CTL)
CONVERTER BUFFER
CHECK LINE LPBK (SOFT CTL) INPUT DATA(8) PARITY(1)
BYTE PARITY GENERATOR
LPBK
A1/A2
A1/A2
SONET SCRAMBLER
PARALLEL SERIAL (MEGACELL FROM ASIC VENDOR)
LVDS OUT#1
SYSTEM FRAME SYSTEM CLOCK
77.76 BLOCKS) SYNC (COMMON CHANNELS)
A1/A2
LINE LPBK (FROM
MODE BYTES (INS/PASS) INS/PASS (SOFT CTL) (SOFT CTL)
A1/A2 ERROR A1/A2 ERROR INSERT INSERTVALUE COUNT (SOFT REG) (SOFT REG)
A1/A2 ERROR INSERTCMD (SOFT CTL)
SCRAMBLER 77.76 LVDS LPBK DISABLE (FROM PLL) (FROM PLL) (SOFT CTL)
Figure Transmitter Block
Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
Transmit Direction (Line Backplane) (continued)
Transport Overhead Serial Link
serial links used insert bytes into transmit data. TOH_IN TOH_CLK_EN retimed TOH_CLK order meet setup hold specifications device. Insertion passthrough under software control. parity calculated using initial retimed data (TOH_IN_D).
A1/A2 Frame Insert Corruption
When corrupted, each stream, twelve bytes STS-12 0xF6 twelve bytes STS-12 Corruption controlled stream A1/A2 error insert register. When A1/A2 corruption particular stream, A1/A2 value corrupted A1/A2 value registers sent number frames defined corrupted A1/A2 frame count register (see Table page Table page register details). Note: When corrupted A1/A2 frame count register zero, A1A2 corruption will continue until A1/A2 error insert register cleared, i.e., indefinitely. per-device basis, byte values set, well number frames corruption. Then, insert specified A1/A2 values, each channel enable register. When enable register set, A1/A2 values corrupted number specified number frames corrupt. insert errors again, perchannel fault insert register must cleared, again. Only last first corrupted.
Calculation Insertion
calculation block computes BIP-8 code, using even parity over bits previous STS-n frame after scrambling inserted byte current STS-n frame before scrambling. Per-bit corruption controlled force BIP-8 corruption register (per device register). this register, corresponding calculated BIP-8 inverted before insertion into byte position. Each stream independent fault insert register that enables inversion bytes. bytes other STS-1s stream passed through transparently.
Stream Disable
When disabled appropriate stream enable register, prescrambled data stream ones, feeding HSI. macro powered down per-stream basis, LVDS outputs.
Scrambler
data stream scrambled using frame synchronous scrambler sequence length 127, operating line rate. scrambling function disabled software. generating polynomial scrambler scrambler reset 111_1111 first byte (byte following byte twelfth STS-1). That byte subsequent bytes scrambled exclusive ORed, with output from byte-wise scrambler. scrambler runs continuously from that byte throughout remainder frame. bytes scrambled. Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
Receiver Block
EVEN/ODD PARITY (SOFT CTL) PROT SWITCH CH#1-2 PERF INSERT MONITORS (SOFT CTL) (SOFT CTL) (SOFT CTL) (SOFT REG) PROT SWITCH LINE FUNCTION HI-Z LPBK FLAG INSERT (SOFT CTL) (SOFT CTL) (SOFT REG) (SOFT CTL) FLAG, CLOCK FRAME COUNT, (COMMON (COMMON A1/A2 COUNT LVDS LPBK (SOF REG) (SOFT CTL) SERIAL CLOCK DATA ENABLE COUNT, 16-622 (COMMON FLAG CLOCKS LVDS LPBK (SOFT REG) (FROM PLL) (FROM HI-Z (SOFT CTL) CH#1-2 HI-Z (SOFT CTL) (SOFT CTL) CH#2 DATA PORT CONTROL CONVERTER (COMMON CTLS BUFFER CH#1 DATA(8) PARITY(1) SPE(1) C1J1(1) PARTIY /CHECK DATA PARTIY C1J1 SONET DESCRAMBLER SONET FRAME RECOVERY SERIAL PARALLEL (MEGACELL FROM ASIC VENDOR) 77.76 PARITY ERROR COUNT
PROT SWITCH
PROT SWITCH
LPBK
CH#2 DATA
STS-12 POINTER MOVER
FIFO ALIGNER
LINE FRAME
CTLS
SYSTEM FRAME (FROM
FIFO READ/WRITE CONTROL
LVDS
FRAME PULSE
SYSTEM CLOCK (77.76 MHz)
FIFO SYNC (COMMON CHANNELS)
CTLS (TO/FROM OTHER LINE LPBK (SOFT CTL) K1/K2 PASS /REGEN (SOFT CTL)
FORCE AIS-L (SOFT CTL)
FIFO RE-ALIGN (SOFT CTL)
CTLS OTHER
AIS-L CTLS OTHER (SOFT CTL)
FRAME OFFSET ALARM FLAG (SOFT REG)
FIFO MIN/MAX THRESHOLDS (SOFT REG)
FIFO THRESHOLD ALARM FLAG (SOFT REG)
DESCRAMBLER DISABLE (SOFT CTL)
Figure Receiver Block
Framer Subblock (Backplane Line)
framer block takes byte-wide data from HSI, outputs byte-aligned byte-wide stream sync pulse (asserted clock before first byte). framer algorithm determines out-of-frame/in-frame status incoming data will cause interrupts both errored frame state.
A1-A2 framing pattern detection. Framing similar SONET specification. Generates timing frame pulse. Detects generates interrupt. Detects errored frame increments counter.
Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
Receiver Block (continued)
Framer Subblock (Backplane Line) (continued)
Framer State Machine Figure shows state machine that controls framer. Since TTSV02622 intended between ASICs backplane, there only errored frame state; thus, after transitions missed, state machine goes into state there indication. State. this state, pattern searched every clock cycle. second stage comparison implemented locate A1/A2 transition. When A1/A2 transition found, following occurs:
state machine moves from state frame confirm state. A1offset byte start location locked. row, column, counters set.
Frame Confirm. this state, A1/A2 transition only compared appropriate location, i.e., beginning twelfth location. This location determined from row, column, counters which were transition from frame confirm. this time comparison fails, state machine reverts state. comparison passes, next state will frame. Frame. This state similar frame confirm state except that comparison A1/A2 time incorrect, next state will errored frame state. comparison correct, next state will frame. Errored Frame. Once errored frame state been reached, next comparison incorrect, next state will OOF. Otherwise, correct, next state will frame. This state will generate error interrupt micro.
Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
Receiver Block (continued)
Framer Subblock (Backplane Line) (continued)
EXPECT A1/A2 FIND A1/A2 EXPECT A1/A2 FIND A1/A2 EXPECT A1/A2 !FIND A1/A2
FRAME
EXPECT A1/A2 FIND A1/A2 FRAME CONFIRM ERRORED FRAME
EXPECT A1/A2 !FIND A1/A2
FIND A1/A2 TRANSITION LOCK BARREL SHIFTER ROW/COL/STS COUNTERS
EXPECT A1/A2 !FIND A1/A2
RESET Notes: Row, column, counters only set/reset state transition from frame confirm. Expect A1/A2 means that row/col/STS counter values indicate time last (twelfth) byte.
Figure Framer State Machine
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TTSV02622 STS-24 Backplane Transceiver
Receiver Block (continued)
Calculate Descramble (Backplane Line)
Each block receives byte-wide scrambled 77.76 data frame sync from framer. Since each independently clocked, block operates individual streams. Timing signals required locate overhead bytes extracted generated internally based frame sync. frame sync occurs clock pulse before first byte stream. block produces byte-wide descrambled data output frame sync alignment FIFO block. output frame sync occurs clocks before first byte descrambled data stream allow metastable hardening write control subblock. received data, following functionality needed:
Descrambling received data stream with optional descrambling disable. verification.
Descrambling streams scrambled using frame synchronous scrambler sequence length 127, operating line rate. descrambling function disabled software. generating polynomial scramble scrambler reset 1111111 first byte (byte following byte twelfth STS-1). That byte subsequent bytes scrambled exclusive ORed, with output from byte-wise scrambler. scrambler runs continuously from that byte throughout remainder frame. bytes scrambled. Verification calculation block computes BIP-8 code, using even parity over bits previous STS-12 frame before descrambling, this value checked against byte current frame after descrambling. perstream error counter incremented each that error. Alarm Indication Signal Line (AIS-L) Insertion enabled AIS_L_INSERT[x] AIS_L force register, AIS-L inserted into received frame writing ones bytes descrambled stream. AIS-L Insertion Frame enabled appropriate AIS_L force frame register, AIS-L inserted into received frame writing ones bytes descrambled stream when framer indicates that frame condition exists.
Internal Parity Generation
even parity generated data bytes routed parallel with data checked before protection switch parallel output.
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TTSV02622 STS-24 Backplane Transceiver
Receiver Block (continued)
FIFO Subblock (Backplane Line)
FIFO subblock consists 10-bit FIFO STS-12. This FIFO will used align ±154.3 interlink skew transfer system clock. FIFO Sync Subblock (Backplane Line) This FIFO sync block takes metastable hardened frame pulses from write control blocks produces sync signals that indicate when read control blocks should begin reading from first FIFO location. sync signals, this block produces error indicator which indicates that signals aligned apart alignment (i.e., greater than clocks apart). Sync error signals sent read control block alignment. read control block synchronized only once start-up, further synchronizing software (S/W) controlled. action resynchronizing read control block will always cause data hit. software register allows read control block resynchronized. Recommended Procedure Synchronization Selected Streams
Force AIS-L streams synchronized. Wait four frames. Write FIFO alignment resynchronizing register, register 0x06. Wait four frames. Release AIS-L streams.
Pointer Mover Subblock (Backplane Line)
pointer mover simply maps incoming frames line framing. K1/K2 bytes H1-SS bits also passed through pointer generator that line receive them. mover will handle both concatenations inside STS-12, other STS-12s inside TTSV02622. Pointer Interpreter State Machine pointer interpreter minimized much possible keep gate count low. keeping with that goal, pointer interpreter only three states (NORM, AIS, CONC). interpreter's highest priority maintain accurate dataflow (i.e., valid only). This will ensure that errors pointer value will corrected standard pointer interpreter without data hits. This means that error checking increment, decrement, (i.e., maintained order ensure accurate dataflow. single valid pointer (i.e., 0-782) that differs from current pointer will ignored. consecutive incoming valid pointers that differ from current pointer will cause reset location latest pointer value (the generator will then produce NDF). This block designed handle single errors without affecting dataflow changing state, compliant with SONET standards.
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TTSV02622 STS-24 Backplane Transceiver
Receiver Block (continued)
Pointer Mover Subblock (Backplane Line) (continued)
Rules Concatenation. pointer mover block correctly process length concatenation (multiple three) long begins STS-3 boundary (i.e., STS-1 number etc.) contained within smaller STS-3, (see Table Table Valid Starting Positions STS-MC STS-1 Number
Notes: STS-Mc start that STS-1. STS-Mc cannot start that STS-1. depending particular value
STS-3c
STS-6c
STS-9c
STS-12c
STS-15c
STS-18c STS-24c SPEs
Rules Pointer Interpretation.
bits byte (1001 single error). NRMNBTS (i.e., set) bits byte (0110 single error). CONC pointer bits byte 1001 single error) offset 11_1111_1111. pointer offset bits bits ignored). NORM pointer (offset 0-782) (NDF NRMNBITS).
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TTSV02622 STS-24 Backplane Transceiver
Receiver Block (continued)
Pointer Mover Subblock (Backplane Line) (continued)
NORM State. This state will begin whenever consecutive NORM pointers received. consecutive NORM pointers received, such that both differ from current offset, then current offset will reset last received NORM pointer. When pointer interpreter changes offset, causes pointer generator receive value position. When pointer generator gets unexpected resets offset value location declares NDF. Note: interpreter only looking consecutive pointers that different from current value. These consecutive NORM pointers have have same value. example; current pointer receive NORM pointer with offset second NORM pointer with offset then interpreter will change current pointer CONC State. receipt consecutive CONC pointers causes this state entered. Once this state, offset values from head concatenation chain used determine location each chain. State. consecutive pointers cause this state occur. consecutive normal concatenation pointers will this state. This state will cause data leaving pointer generator overwritten with 0xFF.
NORM
CONC
CONC
Figure Pointer Mover State Machine Pointer Generator pointer generator simply maps corresponding bytes into their appropriate location outgoing byte stream. generator also creates offset pointers based location byte indicated pointer interpreter. generator will signal NDFs when interpreter signals that coming state. generator resets pointer value generates every time byte marked read from elastic store that doesn't match previous offset. Increments decrements signals from pointer interpreter latched once frame either byte times (depending collisions), this ensures constant values during through times. choice which byte time latching made when relative frame phases (i.e., received system) determined. This latch point will then stable, unless relative framing changes received byte times collide with system times, which case latch point would switched collision-free byte time.
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TTSV02622 STS-24 Backplane Transceiver
Receiver Block (continued)
Pointer Mover Subblock (Backplane Line) (continued)
There restriction many often increments decrements processed. received increment decrement immediately passed generator implementation regardless when last pointer adjustment made. responsibility meeting SONET criteria frequency pointer adjustments then left upstream pointer processor. When interpreter signals state, generator will immediately begin sending 0xFF place data This will continue until interpreter returns NORM CONC states byte received.
Miscellaneous Functions
K1/K2, A1/A2 Handling
K1/K2 bytes optionally passed through pointer mover under software control, zero with other bytes. A1/A2 bytes regenerated respectively.
C1J1 Outputs
attempt minimize complexity required from pointer processor that hooked-up TTSV02622 parallel output port, signals (per channel) must provided external world; these called C1J1. These signals will allow pointer processor extract payload without interpreting pointers. Table C1J1 Functionality C1J1 Description information excluding C1(J0) STS-1 Position C1(J0) STS-1 information excluding bytes. Position twelve bytes.
following rules must observed generating C1J1 signals:
occurrence AIS-P STS-1, there must corresponding pulse. case concatenated payloads STS-24c), only head STS-1 group must have associated pulse. C1J1 signal must track pointer movements. During negative justification event, must high during byte indicate that payload data available. During positive justification event, must during positive stuff opportunity byte indicate that payload data available.
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TTSV02622 STS-24 Backplane Transceiver
Registers
Definition Register Types
TTSV02622 design contains structural register elements: SREG, CREG, PREG, IAREG, ISREG, IEREG. There mixed registers TTSV02622. This means that bits particular register (particular address) structurally same follows:
Status register (SREG): status register read only, name implies used convey status information particular element function TTSV02622 chip. reset value SREG really reset value particular element function that being read. some cases, SREG really fixed value; example which fixed revision registers. Control register (CREG): control register read writable memory element inside CORE_CONTROL. value CREG will always value written Events inside TTSV02622 chip cannot affect CREG value. only exception soft reset, which case CREG will return reset value. control register have reset values defined reset value column Table page Pulse register (PREG): Each element, bit, pulse register control event signal that asserted then deasserted when value written This means that each always value until written upon which pulsed value then returned value pulse register will always have read value Interrupt alarm register (IAREG): Each interrupt alarm register event latch. When particular event produced TTSV02622 chip, occurrence latched associated IAREG bit. clear particular IAREG bit, value must written TTSV02622 chip, IAREG reset values Interrupt status register (ISREG): Each interrupt status register physically logical function. consolidation lower-level interrupt alarms and/or ISREG bits from other registers. direct result fact that each ISREG logical function means that will have read value consolidation signals value will value only consolidation signals value TTSV02622 chip, ISREG reset values Interrupt enable register (IEREG): Each status register alarm register associated enable bit. this value then event allowed propagate next higher level consolidation. this zero, then associated IAREG ISREG still asserted alarm will propagate next higher level. Obviously, interrupt enable interrupt mask when value
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TTSV02622 STS-24 Backplane Transceiver
Registers (continued)
Register
Table Register
ADDR* Reg. [6:0] Type
SREG SREG SREG CREG CREG CREG PREG
Reset Comments Value (hex)
Generic register block.
FIXED FIXED FIXED SCRATCH LOCKREG LOCKREG
FIFO ALIGNMENT COMMAND STS-12 SELECT
GLOBAL RESET COMMAND LVDS LPBK CONTROL
Device Register Block CREG
FRAME CLOCK ENABLE HI-Z CONTROL
PROT
PROT FUNC
Device register block (Rx).
CREG
PARALLEL PORT OUTPUT SELECT
SERIAL PORT OUTPUT SELECT
CREG CREG CREG
SCRAMBLER/ DESCREAMBLER CONTROL
PARALLEL PARITY CONTROL LINE LPBK CONTROL
FIFO ALIGNER THRESHOLD VALUE (min) FIFO ALIGNER THRESHOLD VALUE (max) NUMBER CONSECUTIVE A1/A2 ERRORS GENERATE [3:0]
Device register block (Tx).
CREG CREG CREG ISREG IEREG IAREG
ERROR INSERT VALUE ERROR INSERT VALUE TRANSMITTER ERROR INSERT MASK
FRAME OFFSET ERROR FLAG Top-level interrupts.
DEVICE
ENABLE/MASK REGISTER [4:0]
WRITE LOCKED REGISTER ERROR FLAG
IEREG
ENABLE/MASK REGISTER
ADDR values delimited comma indicate address each channels, from channel example, register control signals addresses This indicates that channel control signals address channel control signals address Reserved.
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TTSV02622 STS-24 Backplane Transceiver
Registers (continued)
Register (continued)
Table Register (continued)
ADDR* Reg. [6:0] Type Reset Comments Value (Hex)
control signals.
Channel Register Block CREG HI-Z CONTROL DATA OUTPUT HI-Z CONTROL PARALLEL OUTPUT E1/F1/E2 SOURCE SELECT SOURCE SELECT CHANNEL ENABLE DISABLE CONTROL PARALLEL OUTPUT PARITY K1/K2 SOURCE SELECT SOURCE SELECT K1/K2 SOURCE SELECT SERIAL OUTPUT PORT SOURCE SELECT SOURCE SELECT FORCE AIS-L CONTROL BEHAVIOR
CREG
MODE OPERATION SOURCE SELECT
S1/M0 SOURCE SELECT SOURCE SELECT
SOURCE SELECT SOURCE SELECT
SOURCE SELECT SOURCE SELECT ERROR INSERT COMMAND
SOURCE SELECT SOURCE SELECT A1/A2 ERROR INSERT COMMAND CONCAT INDICATION CONCAT INDICATION STS-12 ALARM FLAG
control signals.
CREG
CREG
CONCAT INDICATION
SREG
CONCAT CONCAT CONCAT INDICATION INDICATION INDICATION
STS-1 change state flag.
SREG
CONCAT CONCAT CONCAT CONCAT CONCAT CONCAT INDICATION INDICATION INDICATION INDICATION INDICATION INDICATION
ISREG
ELASTIC STORE
OVERFLOW
AIS-P FLAG
FLAG IEREG IAREG
Per-channel interrupt consolidation.
SERIAL INPUT PORT PARITY ERROR FLAG
INPUT PARALLEL PARITY ERROR FLAG
LVDS LINK PARITY ERROR FLAG
ENABLE/MASK REGISTER [2:0] FLAG RECEIVER INTERNAL PATH PARITY ERROR FLAG FIFO ALIGNER THRESHOLD ERROR FLAG
STS-12 interrupt flags.
IEREG
ENABLE/MASK REGISTER [5:0]
ADDR values delimited comma indicate address each channels, from channel example, register control signals addresses This indicates that channel control signals address channel control signals address Reserved.
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TTSV02622 STS-24 Backplane Transceiver
Registers (continued)
Register (continued)
Table Register (continued)
ADDR* [6:0] Reg. Type Reset Comments Value (hex)
STS-1 interrupt flags.
Channel Register Block (continued)
IAREG
INTERRUPT INTERRUPT INTERRUPT INTERRUPT FLAGS FLAG FLAGS FLAGS
IAREG
INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT FLAG FLAG FLAG FLAG FLAG FLAG FLAG FLAG
IEREG
ENABLE/ ENABLE/ ENABLE/ ENABLE/ MASK MASK MASK MASK INTERRUPT INTERRUPT INTERRUPT INTERRUPT FLAGS FLAG FLAGS FLAGS
IEREG
ENABLE/ ENABLE/ ENABLE/ ENABLE/ ENABLE/ ENABLE/ ENABLE/ ENABLE/ MASK MASK MASK MASK MASK MASK MASK MASK INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT FLAG FLAG FLAG FLAG FLAG FLAG FLAG FLAG
IAREG
OVERFLOW OVERFLOW OVERFLOW OVERFLOW FLAGS FLAG FLAGS FLAGS
IAREG
OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW FLAG FLAG FLAG FLAG FLAG FLAG FLAG FLAG
IEREG
ENABLE/ ENABLE/ ENABLE/ ENABLE/ MASK MASK MASK MASK OVERFLOW OVERFLOW OVERFLOW OVERFLOW FLAGS FLAG FLAGS FLAGS
IEREG
ENABLE/ ENABLE/ ENABLE/ ENABLE/ ENABLE/ ENABLE/ ENABLE/ ENABLE/ MASK MASK MASK MASK MASK MASK MASK MASK OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW FLAG FLAG FLAG FLAG FLAG FLAG FLAG FLAG LVDS LINK PARITY ERROR COUNTER COUNTER A1/A2 FRAME ERROR COUNTER
COUNTER OVERFLOW COUNTER OVERFLOW COUNTER OVERFLOW
Binning.
ADDR values delimited comma indicate address each channels, from channel example, register control signals addresses This indicates that channel control signals address channel control signals address Reserved.
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TTSV02622 STS-24 Backplane Transceiver
Register Descriptions
Table Register Description Address (hex) [7:0] [7:0] [7:0] [7:0] Name Type Description Reset Value (hex)
FIXED FIXED FIXED SCRATCH
SREG SREG SREG CREG
[7:0]
LOCKREG
CREG
[7:0]
LOCKREG GLOBAL RESET COMMAND
CREG PREG
[7:2]
FIFO ALIGNMENT COMMAND
PREG
scratch function used anywhere TTSV02622 chip. However, this register written read from. order write registers memory locations 06-7F, LOCKREG LOCKREG must respectively values LOCKREG LOCKREG values respectively, then values written registers memory locations 06-7F will ignored. After reset (both hard soft), TTSV02622 chip write locked mode. TTSV02622 chip needs unlocked before written Also note that scratch register (03) always written since unaffected write lock mode. address 0x04 bits [7:0] description. FIFO ALIGNMENT GLOBAL RESET COMMANDS both accessed pulse register memory address FIFO ALIGNMENT command used frame align outputs four receive Sstream FIFOs. GLOBAL RESET COMMAND soft (software initiated) reset. Nevertheless, GLOBAL RESET COMMAND will have exact reset effect hard (RST_N pin) reset. address 0x06 description. Reserved.
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Register Descriptions (continued)
Table Register Description (continued) Address (hex) Name Type Description Reset Value (hex)
Device Register Blocks CREG loopback. LVDS loopback, transmit receive CREG This control signal untracked TTSV02622 chip. scratch bit, value effect TTSV02622 chip. Switching Control Master [3:2] PROT CREG PORT PROT (bit FUNC PROT FUNC controlled software (bit control MUX). Output buffers controlled software control channel). parallel output controlled PROT_SWITCH_A/B pin. Output buffers controlled software control channel). controlled software control MUX). Output buffers parallel output controlled PROT_SWITCH_A/B pin. Buffers active. HI-Z. CREG High impedance. FRAME Enable receive outputs. CLOCK ENABLE HI-Z CONTROL [7:5] Reserved. LVDS LPBK CONTROL STS-12 SELECT
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TTSV02622 STS-24 Backplane Transceiver
Register Descriptions (continued)
Table Register Description (continued) Address (hex) Name Type Description Reset Value (hex)
SERIAL PORT OUTPUT SELECT PARALLEL PORT OUTPUT SELECT
Device Register Blocks (continued) CREG output multiplexed output multiplexed Reserved. CREG Parallel output data multiplexed Parallel output data multiplexed
[7:4] [4:0]
Reserved. Reserved. FIFO ALIGNER CREG This minimum threshold value per-channel THRESHOLD VALUE receive direction alignment FIFOS. when mini(min) threshold value violated particular channel, then interrupt event FIFO ALIGNER THRESHOLD ERROR will generated that channel latched FIFO ALIGNER THRESHOLD ERROR FLAG respective STS-12 interrupt alarm register. allowable range minimum threshold values
Note: minimum FIFO aligner threshold values apply both channels. [7:5] Reserved. [4:0] FIFO ALIGNER CREG This maximum threshold value per-channel receive direction alignment FIFOS. when maxiTHRESHOLD VALUE threshold value violated particular channel, (max) then interrupt event FIFO ALIGNER THRESHOLD ERROR will generated that channel latched FIFO ALIGNER THRESHOLD ERROR FLAG respective STS-12 interrupt alarm register. allowable range maximum threshold values Note: minimum FIFO aligner threshold values apply both channels. Reserved.
[7:5]
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TTSV02622 STS-24 Backplane Transceiver
Register Descriptions (continued)
Table Register Description (continued) Address (hex) Name Type Description Reset Value (hex)
[3:0]
NUMBER CONSECUTIVE A1/A2 ERRORS GENERATE [3:0]
Device Register Blocks (continued) CREG These three (0C, per-device control signals used conjunction with channel A1/A2 ERROR INSERT COMMAND control bits force A1/A2 errors transmit direction. particular channel's A1/A2 ERROR INSERT COMMAND control value then error insert values will inserted into that channels respective bytes. number consecutive frames corrupted determined NUMBER CONSECUTIVE ERRORS GENERATE [3:0] control bits. error insertion based rising edge detector. such, control must value before trying initiate second corruption. CREG loopback. loopback line side. CREG parity. Even parity. CREG direction descramble/Tx direction scramble. direction, descramble channel after SONET frame recovery. direction, scramble data just before parallel-to-serial conversion. Reserved. CREG address 0x0C bits [3:0] description. CREG address 0x0C bits [3:0] description. CREG error insertion. Invert corresponding byte.
LINE LPBK CONTROL INPUT/OUTPUT PARALLEL PARITY CONTROL SCRAMBLER/ DESCREAMBLER CONTROL
[7:0] [7:0] [7:0]
ERROR INSERT VALUE ERROR INSERT VALUE TRANSMIT ERROR INSERT MASK
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TTSV02622 STS-24 Backplane Transceiver
Register Descriptions (continued)
Table Register Description (continued) Address (hex) Name Type Description Reset Value (hex)
[3:2]
[7:5] [4:0] [7:5]
Device Register Blocks (continued) ISREG Consolidation interrupts. interrupt. Interrupt. ISREG Consolidation interrupts. interrupt. Interrupt. Reserved. DEVICE ISREG Consolidation interrupts. interrupt. Interrupt. Reserved. ENABLE/MASK IEREG REGISTER Reserved. FRAME OFFSET IAREG receive direction phase offset between ERRROR FLAG channels exceeds bytes, then frame offset error event will issued. This condition continuously monitored.
TTSV02622 memory been unlocked writing lock registers), address other than LOCKREG registers SCRATCH register written then WRITE LOCKED REGISTER event will generated. WRITE LOCKED IAREG address 0x12 description. REGISTER ERROR FLAG [7:2] Reserved. [1:0] ENABLE/MASK IEREG address 0x12 description. REGISTER [7:2] Reserved.
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TTSV02622 STS-24 Backplane Transceiver
Register Descriptions (continued)
Table Register Description (continued) Address (hex) Name Type Description Reset Value (hex)
BEHAVIOR FORCE AIS-L CONTROL SERIAL OUTPUT PORT K1/K2 SOURCE SELECT PARALLEL OUTPUT PARITY CHANNEL ENABLE/ DISABLE CONTROL HI-Z CONTROL PARALLEL OUTPUT HI-Z CONTROL DATA OUTPUT SOURCE SELECT SOURCE SELECT SOURCE SELECT SOURCE SELECT K1/K2 SOURCE SELECT S1/M0 SOURCE SELECT E1/F2/E2 SOURCE SELECT MODE OPERATION
Channel Register Blocks CREG When direction occurs, insert AIS-L. When direction occurs, insert AIS-L. CREG force AIS-L. Force AIS-L. CREG insert parity error. Insert parity error parity receive serial output long this set. CREG receive direction K2/K2 bytes Pass receive direction K1/K2 though pointer mover. CREG insert parity error. Insert parity error parity receive direction parallel output long this set. CREG Powerdown channel 3-state output buses. Functional mode. CREG 3-state output bus. Functional mode. CREG 3-state output lines. Functional mode. CREG Insert from serial ports. Pass through that particular byte. CREG Insert from serial ports. Pass through that particular byte. CREG Insert from serial ports. Pass through that particular byte. CREG Insert from serial ports. Pass through that particular byte. CREG Insert from serial ports. Pass through that particular byte. CREG Insert from serial ports. Pass through that particular byte. CREG Insert from serial ports. Pass through that particular byte. CREG Insert from serial ports. Pass through TOH.
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TTSV02622 STS-24 Backplane Transceiver
Register Descriptions (continued)
Table Register Description (continued) Address (hex) Name Type Description Reset Value (hex)
Channel Register Blocks (continued) SOURCE CREG Insert from serial ports. SELECT Pass through that particular byte. SOURCE CREG Insert from serial ports. SELECT Pass through that particular byte. SOURCE CREG Insert from serial ports. SELECT Pass through that particular byte. SOURCE CREG Insert from serial ports. SELECT Pass through that particular byte. SOURCE CREG Insert from serial ports. SELECT Pass through that particular byte. SOURCE CREG Insert from serial ports. SELECT Pass through that particular byte. SOURCE CREG Insert from serial ports. SELECT Pass through that particular byte. SOURCE CREG Insert from serial ports. SELECT Pass through that particular byte. A1/A2 ERROR CREG insert error. INSERT COMMAND Insert error number frames register 0x0C. error insertion based rising edge detector. such, control must value before trying initiate second corruption. CREG insert error. Insert error frame bits defined register 0x0F. error insertion based rising edge detector. such, control must value before trying initiate second corruption. Reserved. value location indicates that STS# CONCAT mode. indicates that CONCAT mode, head concatenation group. value location indicates that STS# CONCAT mode. indicates that CONCAT mode, head concatenation group. value location indicates that STS# CONCAT mode. indicates that CONCAT mode, head concatenation group. value location indicates that STS# CONCAT mode. indicates that CONCAT mode, head concatenation group. Reserved.
ERROR INSERT COMMAND
[7:2]
CONCAT INDICATION CONCAT INDICATION CONCAT INDICATION CONCAT INDICATION
SREG
SREG
SREG
SREG
[7:4]
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TTSV02622 STS-24 Backplane Transceiver
Register Descriptions (continued)
Table Register Description (continued) Address (hex) Name Type Description Reset Value (hex)
[7:3] [2:0] [7:3]
Channel Register Blocks (continued) SREG value location indicates that STS# CONCAT mode. indicates that CONCAT mode, head concatenation group. CONCAT SREG value location indicates that STS# INDICATION CONCAT mode. indicates that CONCAT mode, head concatenation group. CONCAT SREG value location indicates that STS# INDICATION CONCAT mode. indicates that CONCAT mode, head concatenation group. CONCAT SREG value location indicates that STS# INDICATION CONCAT mode. indicates that CONCAT mode, head concatenation group. CONCAT SREG value location indicates that STS# INDICATION CONCAT mode. indicates that CONCAT mode, head concatenation group. CONCAT SREG value location indicates that STS# INDICATION CONCAT mode. indicates that CONCAT mode, head concatenation group. CONCAT SREG value location indicates that STS# INDICATION CONCAT mode. indicates that CONCAT mode, head concatenation group. CONCAT SREG value location indicates that STS# INDICATION CONCAT mode. indicates that CONCAT mode, head concatenation group. STS-12 ALARM ISREG These flag register bits STS-12 ALARM FLAG, FLAG AIS-P FLAG, ELASTIC STORE OVERFLOW FLAG AIS-P FLAG ISREG per-channel interrupt status (consolidation) ELASTIC STORE ISREG register. CONCAT INDICATION OVERFLOW FLAG Reserved. IEREG These enable/mask register bits per-channel interrupt status (consolidation) register. Reserved.
ENABLE/MASK REGISTER
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TTSV02622 STS-24 Backplane Transceiver
Register Descriptions (continued)
Table Register Description (continued) Address (hex) Name Type Description Reset Value (hex)
[7:6] [5:0] [7:6] [7:4]
Channel Register Blocks (continued) FIFO ALIGNER IAREG These STS-12 ALARM FLAGs. THRESHOLD ERROR FLAG RECEIVER INTER- IAREG These STS-12 ALARM FLAGs. PATH PARITY ERROR FLAG FLAG IAREG These STS-12 ALARM FLAGs. LVDS LINK PAR- IAREG These STS-12 ALARM FLAGs. ERROR FLAG INPUT PARALLEL IAREG These STS-12 ALARM FLAGs. PARITY ERROR FLAG SERIAL INPUT IAREG These STS-12 ALARM FLAGs. PORT PARITY ERROR FLAG Reserved. ENABLE/MASK IEREG These STS-12 ALARM FLAGs. REGISTER Reserved. INTERRUPT IAREG These AIS-P ALARM FLAGs. FLAGS INTERRUPT IAREG These AIS-P ALARM FLAGs. FLAGS INTERRUPT IAREG These AIS-P ALARM FLAGs. FLAGS INTERRUPT IAREG These AIS-P ALARM FLAGs. FLAGS Reserved.
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TTSV02622 STS-24 Backplane Transceiver
Register Descriptions (continued)
Table Register Description (continued) Address (hex) Name Type Description Reset Value (hex)
Channel Register Blocks (continued) INTERRUPT IAREG These AIS-P ALARM FLAGs. FLAGS INTERRUPT IAREG These AIS-P ALARM FLAGs. FLAGS INTERRUPT IAREG These AIS-P ALARM FLAGs. FLAGS INTERRUPT IAREG These AIS-P ALARM FLAGs. FLAGS INTERRUPT IAREG These AIS-P ALARM FLAGs. FLAGS INTERRUPT IAREG These AIS-P ALARM FLAGs. FLAGS INTERRUPT IAREG These AIS-P ALARM FLAGs. FLAGS INTERRUPT IAREG These AIS-P ALARM FLAGs. FLAGS ENABLE/MASK IEREG These AIS-P ALARM FLAGs. INTERRUPT FLAG ENABLE/MASK IEREG These AIS-P ALARM FLAGs. INTERRUPT FLAG ENABLE/MASK IEREG These AIS-P ALARM FLAGs. INTERRUPT FLAG ENABLE/MASK IEREG These AIS-P ALARM FLAGs. INTERRUPT FLAG [7:4] Reserved. ENABLE/MASK IEREG These AIS-P ALARM FLAGs. INTERRUPT FLAG ENABLE/MASK IEREG These AIS-P ALARM FLAGs. INTERRUPT FLAG ENABLE/MASK IEREG These AIS-P ALARM FLAGs. INTERRUPT FLAG ENABLE/MASK IEREG These AIS-P ALARM FLAGs. INTERRUPT FLAG ENABLE/MASK IEREG These AIS-P ALARM FLAGs. INTERRUPT FLAG ENABLE/MASK IEREG These AIS-P ALARM FLAGs. INTERRUPT FLAG ENABLE/MASK IEREG These AIS-P ALARM FLAGs. INTERRUPT FLAG ENABLE/MASK IEREG These AIS-P ALARM FLAGs. INTERRUPT FLAG
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TTSV02622 STS-24 Backplane Transceiver
Register Descriptions (continued)
Table Register Description (continued) Address (hex) Name Type Description Reset Value (hex)
Channel Register Blocks (continued) IAREG These ELASTIC STORE OVERFLOW alarm flags. IAREG These ELASTIC STORE OVERFLOW alarm flags. IAREG These ELASTIC STORE OVERFLOW alarm flags. IAREG These ELASTIC STORE OVERFLOW alarm flags. [7:4] Reserved. OVERFLOW IAREG These ELASTIC STORE OVERFLOW alarm FLAGS flags. OVERFLOW IAREG These ELASTIC STORE OVERFLOW alarm FLAGS flags. OVERFLOW IAREG These ELASTIC STORE OVERFLOW alarm FLAGS flags. OVERFLOW IAREG These ELASTIC STORE OVERFLOW alarm FLAGS flags. OVERFLOW IAREG These ELASTIC STORE OVERFLOW alarm FLAGS flags. OVERFLOW IAREG These ELASTIC STORE OVERFLOW alarm FLAGS flags. OVERFLOW IAREG These ELASTIC STORE OVERFLOW alarm FLAGS flags. OVERFLOW IAREG These ELASTIC STORE OVERFLOW alarm FLAGS flags. ENABLE/MASK IEREG These AIS-P ALARM FLAGs. OVERFLOW FLAG ENABLE/MASK IEREG These AIS-P ALARM FLAGs. OVERFLOW FLAG ENABLE/MASK IEREG These AIS-P ALARM FLAGs. OVERFLOW FLAG ENABLE/MASK IEREG These AIS-P ALARM FLAGs. OVERFLOW FLAG [7:4] Reserved. OVERFLOW FLAGS OVERFLOW FLAGS OVERFLOW FLAGS OVERFLOW FLAGS
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TTSV02622 STS-24 Backplane Transceiver
Register Descriptions (continued)
Table Register Description (continued) Address (hex) Name Type Description Reset Value (hex)
Channel Register Blocks (continued) ENABLE/MASK IEREG These AIS-P ALARM FLAGs. OVERFLOW FLAG ENABLE/MASK IEREG These AIS-P ALARM FLAGs. OVERFLOW FLAG ENABLE/MASK IEREG These AIS-P ALARM FLAGs. OVERFLOW FLAG ENABLE/MASK IEREG These AIS-P ALARM FLAGs. OVERFLOW FLAG ENABLE/MASK IEREG These AIS-P ALARM FLAGs. OVERFLOW FLAG ENABLE/MASK IEREG These AIS-P ALARM FLAGs. OVERFLOW FLAG ENABLE/MASK IEREG These AIS-P ALARM FLAGs. OVERFLOW FLAG ENABLE/MASK IEREG These AIS-P ALARM FLAGs. OVERFLOW FLAG COUN 7-bit count overflow reset read. [6:0] LVDS LINK PARITY ERROR COUNTER OVERFLOW COUN [6:0] COUNTER COUN 7-bit count overflow reset read. OVERFLOW COUN [6:0] A1/A2 FRAME COUN 7-bit count overflow reset read. ERROR COUNTER OVERFLOW COUN
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TTSV02622 STS-24 Backplane Transceiver
Absolute Maximum Ratings
Stresses excess absolute maximum ratings cause permanent damage device. These absolute stress ratings only. Functional operation device implied these other conditions excess those given operational sections data sheet. Exposure absolute maximum ratings extended periods adversely affect device reliability. Table Absolute Maximum Ratings Parameter Power Supply Voltage with Respect Ground Input Voltages Power Dissipation Storage Temperature Range Symbol Tstg Unit
Handling Precautions
Although electrostatic discharge (ESD) protection circuitry been designed into this device, proper precautions must taken avoid exposure electrical overstress (EOS) during handling, assembly, test operations. Agere employs both human-body model (HBM) charged-device model (CDM) qualification requirement order determine ESD-susceptibility limits protection design evaluation. voltage thresholds dependent circuit parameters used each models, defined JEDEC's JESD22-A114 (HBM) JESD22-C101 (CDM) standards. Table Handling Precautions Model Minimum Threshold Minimum corner pins only Minimum other pins Voltage 2000 1000
Recommended Operating Conditions
following tables list voltages required proper operation TTSV02622 device, along with their tolerances. Table Recommended Operating Conditions Parameter Power Supply Voltage with Respect Ground Input High Voltage (TTL input) Input Voltage (TTL input) Input Voltages Junction Temperature Symbol 3.14 3.47 Unit
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TTSV02622 STS-24 Backplane Transceiver
Thermal Characteristics
TTSV02622 5.86 6.49 272-pin PBGA (2-layer BGA). thermal characteristics, following values should used:
15.38 °C/W 25.09 °C/W 31.92 °C/W
1.00 °C/W
Table Thermal Resistance-Junction Ambient Speed Linear Feet Minute (LFPM) JEDEC Standard Natural Convection
(°C/W)
29.48 28.65 27.42
Power Consumption (Advance)
Table Power Consumption (Advance) Parameter Channel Condition 3.465 Unit
Electrical Characteristics
Table LVTTL Electrical Characteristics Parameter Output Voltage: High Symbol Test Conditions Unit
Propagation Delay Specifications
Delay 77.78 system clocks from line input LVDS backplane output seven clocks (see Figure Transmitter Transport Delay page 56). Propagation delay from change PROT protection switch activity:
NORM HI-Z: Five rising edges SYS_CLK from assertion PROT_SW_A/C pins data changing HI-Z. NORM switch: Eight rising edges SYS_CLK from assertion PROT_SW_A/C pins data changing from stream (See Figure page 58.)
Propagation delay from STS-1 arriving LVDS input RX_TOH_FP SYS_CLKs, TOH_CLKs. This will vary SYS_CLKs, each FIFO alignment, SYS_CLKs variability clock recovery macro. Delay from CS_N going active (CPU write access reset chip) reset being deactivated interface being ready handle another access nine SYS_CLKs. Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
LVDS
LVDS buffers compatible with IEEE 1596.3 ®/TIA-644. However, specs listed IEEE document pertained just buffer itself; rather they system-level specifications. LVDS buffers TTSV02622 compliant parts IEEE 1596.3 spec that pertain silicon implementation. Unused inputs will oscillate when they open short-circuited. Both terminals input should held voltages lower than resistor included internally, board termination necessary. Unused outputs need termination, since they terminated internally. This valid both powerdown mode functional mode. LVDS_EN enable that overrides processor control over powerdown LVDS input output pads. This boundary scan only, should pulled high during functional mode. boundary scan, LVDS_EN HIZ_N board layout, LVDS traces should controlled impedance layers, should specified lineto-ground. LVDS buffers support point-to-point connections. They intended bussed implementations.
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TTSV02622 STS-24 Backplane Transceiver
LVDS (continued)
LVDS DRIVER LVDS RECEIVER
CENTER
EXTERNAL DEVICE PINS
Figure LVDS Driver Receiver Associated Internal Components
DRIVER
INTERCONNECT
RECEIVER
VGPD
Figure LVDS Driver Receiver
RLOAD (VOA VOB)
Figure LVDS Driver
Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
LVDS (continued)
LVDS Receiver Buffer Capabilities
disabled unpowered LVDS receiver withstand driving LVDS transmitter over full range driver operating range, unlimited period time, without being damaged. Table illustrates LVDS driver data, Table data, Table page Table page LVDS receiver data. Table LVDS Receiver Data* Parameter Input Voltage Range, (Common-Mode Voltage) Input Differential Threshold (Differential-Mode Voltage) Input Differential Hysteresis Receiver Differential Input Impedance Symbol VIDTH VHYST Conditions |VGPD| |VGPD| (+VIDTHH) (-VIDTHL) With Build-In Termination, Center-Tapped -100 Unit
V-3.5 °C-125 slow-fast process. Buffer will produce output transition when input open-circuited.
Table LVDS Receiver Data* Parameter Rise Time (20%-80%) Fall Time (80%-20%)
V-3.5 °C-125 slow-fast process.
Symbol
Conditions
Unit
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TTSV02622 STS-24 Backplane Transceiver
LVDS (continued)
Table LVDS Driver Data* Parameter Output Voltage High, Output Voltage Low, Output Differential Voltage Output Offset Voltage Output Impedance, Signal Ended Mismatch Between Change Differential Voltage Between Complementary States Change Output Offset Voltage Between Complementary States Output Current Output Current Power-Off Output Leakage Symbol |VOD| |VOD| ISA, ISAB |Ixa|, |Ixb| Conditions RLOAD RLOAD RLOAD RLOAD RLOAD RLOAD Driver Shorted Drivers Shorted Together VPAD, VPADN 0.925 0.25 1.125
1.475 0.45
Unit
1.275
V-3.5 °C-125 slow-fast process. External references selected (CNT REF10 REF14
Table LVDS Driver Data* Parameter Fall Time, 80%-20% Rise Time, 20%-80% Differential Skew |tPHLA tPHLB| |TPHLB TPLHA| Symbol tSKEW1 Conditions CPAD CPADN CPAD CPADN Differential Pair Package Point Transition Unit
V-3.5 °C-125 slow-fast process.
Table LVDS Driver Reference Data Parameter REF10 Voltage Range REF14 Voltage Range Nominal Input Current- REF10 REF14 Reference Inputs Conditions 0.95 1.35 1.05 1.45 Unit
Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
Clock Data Recovery (CDR)
following specifications reference clock data recovery macro that used backplane interface TTSV02622 chip.
Input Data
Mbits/s scrambled data stream conforms SONET STS-12 STM-4 data format using either sequence. characteristic characteristic Longest stream nontransitional Mbits/s input data bits. This sequence should occur more often than once minute. Input signal phase change more than over time interval, which translates frequency change ppm. opening greater than UIp-p. Unit interval Mbits/s 1.6075
Jitter Tolerance
Table Jitter Tolerance Frequency UIp-p
Generated Output Jitter
UIp-p from measured spectrum analyzer.
Loop bandwidth less than MHz. Jitter peaking less than Minimum powerup reset duration Maximum lock acquisition less than External resistor ground required.
Input Reference Clock
Frequency deviation more than ppm. Phase change more than Time interval that translates frequency change ppm. Input reference clock 77.76 MHz.
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TTSV02622 STS-24 Backplane Transceiver
Timing Characteristics
timing numbers measured relative outputs driving maximum, minimum, except pins which drive
SYS_CLK SYS_FP
FIRST STS-1 INPUT
Figure Input Parallel Port Timing Table Input Parallel Port Timing Requirements Symbol Clock Period Clock Time Clock High Time Data Setup Time Data Hold Time Parameter 12.86 Unit
Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
Timing Characteristics (continued)
TPROP SYS_CLK
SYS_FP
PARALLEL DATA INPUT
STS-1
LVDS DATA FIRST STS-1
Figure Transmitter Transport Delay Table Transmitter Transport Delay Timing Requirements Symbol TPROP Parameter Number Clocks Delay from Parallel Input LVDS Output Unit SYS_CLK
Notes: LVDS data transmitted first. Min/max variation clock phase selected clock recovery block.
Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
Timing Characteristics (continued)
SYS_CLK LINE_FP OUTPUT FIRST STS-1 PARITY, SPE, C1J1 PINS
Figure Output Parallel Port Timing Table Output Parallel Port Timing Requirements Symbol Parameter Clock Period Clock Time Clock High Time Data Setup Time Data Hold Time Clock Output Time Data, Parity, SPE, C1J1 Pins 12.86 6.43 6.43 Unit
Note: number calculated based load. calculated based load.
Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
Timing Characteristics (continued)
SYS_CLK
PROT_SW_A
OUTPUT BUS*
THIZ
SYS_CLK
OUTPUT
Figure Protection Switch Timing Table Protection Switch Timing Requirements Symbol THIZ Parameter Transport Delay from Latching PROT_SW_A Actual Data Switch Transport Delay from Latching PROT_SW_A Actual Data HI-Z Propagation Delay from SYS_CLK HI_Z Output Setup Time Required from Change PROT_SW_A Rising SYS_CLK Hold Time Required from Rising SYS_CLK Change PROT_SW_A Unit Leading edge SYS_CLKs Leading edge SYS_CLKs
Notes: Output refers bits data, parity, SPE, C1J1. Channel refers whether PROT_SW_A pins that activated. example, PROT_SW_A activated, timing diagram output refers output Min/max variation THIZ clock phase selected clock recovery block.
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TTSV02622 STS-24 Backplane Transceiver
Timing Characteristics (continued)
SYS_CLK
SYS_FP
INPUT PARALLEL
bytes GUARD BAND CLK)
1044 bytes GUARD BAND CLK)
1044 bytes
bytes
TOH_CLK
TOH_ CLK_ENA
SERIAL INPUT
MSBIT(7) BYTE STS-1
BYTE STS-1
Figure Input Serial Port Timing Table Input Serial Port Timing Requirements Symbol Clock Period Clock High Time Clock Time Data Setup Time Data Hold Time Parameter 12.86 Unit
Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
Timing Characteristics (continued)
INPUT LVDS SERIAL Mbits/s DATA
bytes
1044 bytes TTRANS_SYS
1044 bytes
bytes
TTRANS_TOH
TOH_CLK
SERIAL OUTPUT
MSBIT(7) BYTE STS-1
BYTE STS-1
BYTE STS-1
Figure Output Serial Port Timing Table Output Serial Port Timing Requirements Symbol TTRANS_SYS TTRANS_TOH Parameter Data Clock Delay from First LVDS Serial Input Transfer TOH_CLK Delay from Transfer TOH_CLK RX_TOH_FP Unit SYS_CLKs TOH_CLKs
Note: total delay from STS-1 arriving LVDS input RX_TOH_FP SYS_CLKs, TOH_CLKs. This will vary SYS_CLKs, each FIFO alignment, SYS_CLKs variability clock recovery macro.
Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
Timing Characteristics (continued)
Interface Timing
TACCESS_MIN TPULSE CS_N TRD_WR_N, ADDR_MAX, DB_HOLD RD_WR_N
ADDR[6:0]
DB[7:0] INTERNAL REGISTER (SYS_CLK DOMAIN) TADDR_MAX TDAT_MAX, TRD_WR_MAX TWRITE_MAX INT_N
DATA VALID
VALUE
VALUE
TINT_MAX
Figure Write Transaction Table Write Transaction Timing Requirements Symbol TPULSE TADDR_MAX TDAT_MAX TRD_WR_MAX TWRITE_MAX TACCESS_MIN Parameter Minimum Pulse Width CS_N Maximum Time from Negative Edge CS_N ADDR Valid Maximum Time from Negative Edge CS_N Data Valid Maximum Time from Negative Edge CS_N Negative Edge RD_WR_N Maximum Time from Negative Edge CS_N Contents Internal Register Latching DB[7:0] Minimum Time Between Write Cycle (falling edge CS_N) other Transaction (read write, falling edge CS_N) Maximum Time from Register Minimum Hold Time that RD_WR_N, ADDR, Must Held Valid from Negative Edge CS_N Unit
TINT_MAX TRD_WR_N, ADDR_MAX,
DB_HOLD
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TTSV02622 STS-24 Backplane Transceiver
Timing Characteristics (continued)
Interface Timing (continued)
TACCESS_MIN TPULSE CS_N RD_WR_N
ADDR[6:0] THIZ_MAX DB[7:0] DATA VALID
TADDR_MAX TRD_WR_MAX TDATA_MAX
Figure Read Transaction Table Read Transaction Timing Requirements Symbol TPULSE TADDR_MAX TRD_WR_MAX TDATA_MAX THIZ_MAX TACCESS_MIN Parameter Minimum Pulse Width CS_N Maximum Time from Negative Edge CS_N Addr Valid Maximum Time from Negative Edge CS_N RD_WR_N Rising Maximum Time from Negative Edge CS_N Data Valid Port Maximum Time from Rising Edge CS_N Port Going HI-Z Data Hold Time After CS_N Deasserted Minimum Time Between Read Cycle (falling edge CS_N) Other Transaction (read write, falling edge CS_N) Unit
Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
Outline Diagram
272-Pin PBGA
Dimensions millimeters.
27.00 0.20 BALL IDENTIFIER ZONE +0.70 24.00 -0.00
24.00
+0.70 -0.00 27.00 0.20
MOLD COMPOUND 0.36 0.04 1.17 0.05 2.13 0.19 SEATING PLANE 0.20 0.60 0.10 SOLDER BALL SPACES 1.27 24.13
0.75 0.15
SPACES 1.27 24.13
CENTER ARRAY THERMAL ENHANCEMENT (OPTIONAL)
BALL CORNER
Agere Systems Inc.
TTSV02622 STS-24 Backplane Transceiver
Ordering Information
Device Code TTSV02622V2-DB Package 272-pin PBGA Temperature +125 Comcode (Ordering Number) 700034617
additional information, contact your Agere Systems Account Manager following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway Allentown, 18109-9138 1-800-372-2447, 610-712-4106 CANADA: 1-800-553-2448, 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 3210-12, 32/F, Tower Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 755-25881122 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 1344
Agere Systems Inc. reserves right make changes product(s) information contained herein without notice. liability assumed result their application. Agere, Agere Systems, Agere Logo trademarks Agere Systems Inc.
Copyright 2003 Agere Systems Inc. Rights Reserved
June 2003 DS02-340SONT

Low-power supply. +125 industrial temperature range. 272-pin ball grid

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