Features Specific CBGA 255, HiTCE CBGA CI-CGA SPECint95, SPECfp95

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Features Specific CBGA 255, HiTCE CBGA CI-CGA SPECint95, SPECfp95

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Superscalar Instructions Clock Peak) Dual Caches Selectable Clock 32-bit Compatibility PowerPC Implementation On-chip Debug Support Nap, Doze Sleep Power Saving Modes Device Offered Cerquad, CBGA 255, HiTCE CBGA CI-CGA
Features Specific CBGA 255, HiTCE CBGA CI-CGA
SPECint95, SPECfp95 (Estimated) Typically 3.5W (266 MHz), Full Operating Conditions Branch Folding 64-bit Data (32-bit Data Option) 4-Gbytes Direct Addressing Range Pipelined Single/Double Precision Float Unit IEEE Compatible IEEE 1149-1 Test Mode (JTAG/C0P) fINT fBUS Compatible CMOS Input/TTL Output
PowerPC® 603e RISC Microprocessor Family PID7t-603e TSPC603R
Features Specific Cerquad
SPECint95, SPECfp95 (Estimated) Typically 2.5W (200 MHz), Full Operating Conditions
Description
PID7t-603e implementation PowerPC 603e (renamed after 603R) low-power implementation Reduced Instruction Computer (RISC) microprocessor PowerPC family. 603R pin-to-pin compatible with PowerPC 603e 603P Cerquad package. 603R implements 32-bit effective addresses, integer data types bits, floating-point data types bits. 603R low-power 2.5/3.3V design provides four software controllable power-saving modes. This device superscalar processor capable issuing retiring many three instructions clock. Instructions executed order increased performance, but, 603R makes completion appear sequential. integrates five execution units able execute five instructions parallel. 603R provides independent on-chip, 16-Kbyte, four-way set-associative, physically addressed caches instructions data, well on-chip instructions, data Memory Management Units (MMUs). MMUs contain 64-entry, two-way set-associative, data instruction translation look aside buffers that provide support demand-paged virtual memory address translation variable-sized block translation. 603R selectable 64-bit data 32-bit address bus. interface protocol allows multiple masters compete system resources through central external arbiter. device supports single-beat burst data transfers memory accesses, supports memory-mapped I/Os.
Rev. 5410B-HIREL-09/05
603R uses advanced, 2.5/3.3V CMOS process technology maintains full interface compatibility with devices. also integrates in-system testability debugging features through JTAG boundary-scan capabilities.
Screening/Quality/Packaging
This product manufactured full compliance with: HiTCE CBGA according Atmel Standards CI-CGA Cerquad: MIL-PRF-38535 class according Atmel standards CBGA 255: Upscreenings based upon Atmel standards CBGA, CI-CGA, HiTCE packages: Full military temperature range -55°C, +125°C) Industrial temperature range Cerquad: Full military temperature range -55°C, +125°C) Industrial temperature range -40°C, +110°C) Commercial temperature ranges 0°C, +70°C) Internal Power Supply 3.3V
suffix CBGA Ceramic Ball Grid Array
-40°C, +110°C)
suffix CERQUAD Ceramic Leaded Chip Carrier Cavity
suffix CI-CGA Ceramic Ball Grid Array with Solder Column Interposer (SCI)
CERQUAD
suffix HiTCE Ceramic Ball Grid Array
TSPC603R
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TSPC603R
Block Diagram
Figure 3-1. Block Diagram
Fetch Unit Completion Unit Dispatch Unit Branch Unit
Integer Unit
Unit
Rename
Load/ Store Unit
Rename
File
Float Unit
Data Cache
Inst. Cache
Interface Unit
Address System
Data
Overview
603R low-power implementation PowerPC microprocessor family Reduced Instruction Computing (RISC) microprocessors. 603R implements 32-bit portion PowerPC architecture, which provides 32-bit effective addresses, integer data types bits, floating-point data types bits. 64-bit PowerPC microprocessors, PowerPC architecture provides 64-bit integer data types, 64-bit addressing, other features required complete 64-bit architecture. 603R provides four software controllable power-saving modes. Three modes (nap, doze, sleep) static nature, progressively reduce amount power dissipated processor. fourth dynamic power management mode that causes functional units 603R automatically enter low-power mode when functional units idle without affecting operational performance, software execution, external hardware. 603R superscalar processor capable issuing retiring many three instructions clock. Instructions executed order increased performance, but, 603R makes completion appear sequential. 603e integrates five execution units: Integer Unit (IU) Floating-point Unit (FPU) Branch Processing Unit (BPU)
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Load/Store Unit (LSU) System Register Unit (SRU) ability execute five instructions parallel simple instructions with rapid execution times yield high efficiency throughput 603R-based systems. Most integer instructions execute clock cycle. pipelined single-precision multiply-add instruction issued every clock cycle. 603R provides independent on-chip, Kbyte, four-way set-associative, physically addressed caches instructions data, well on-chip instruction data Memory Management Units (MMUs). MMUs contain 64-entry, two-way set-associative, Data Instruction Translation Lookaside Buffers (DTLB ITLB) that provide support demand-paged virtual memory address translation variable-sized block translation. TLBs caches Least Recently Used (LRU) replacement algorithm. 603R also supports block address translation through independent Instruction Data Block Address Translation (IBAT DBAT) arrays four entries each. Effective addresses compared simultaneously with four entries array during block translation. accordance with PowerPC architecture, effective address hits both array, translation priority. 603R selectable 64-bit data 32-bit address bus. 603R interface protocol allows multiple masters compete system resources through central external arbiter. 603R provides three-state coherency protocol that supports exclusive, modified, invalid cache states. This protocol compatible subset MESI four-state protocol operates coherently systems that contain four-state caches. 603R supports single-beat burst data transfers memory accesses, supports memory-mapped I/Os. 603R uses advanced, 0.29 5-metal-layer CMOS process technology maintains full interface compatibility with devices.
Signal Description
Figure page Table 10-5 Table 10-6 page describe signals TSPC603R indicate signal functions. test signals, TRST, TMS, TCK, TDO, comply with subset P-1149.1 IEEE testability standard. three signals LSSD_MODE, LI_TSTCLK L2_TSTCLK test signals factory only must pulled normal machine operations.
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Figure 5-1. Functional Signal Groups
ADDRESS ARBITRATION DBWO DATA ATTRIBUTION
ADDRESS START
DH[0-31], DL[0-31] DP[0-7] DBDIS INT, CKSTP_IN, CKSTP_OUT HRESET, SRESET RSRV QREQ, QACK TBEN TLBISYNC PROCESSOR STATUS INTERRUPTS CHECKSTOPS RESET DATA TERMINATION DATA TRANSFER
A[0-31] ADDRESS AP[0-3] TT[0-4] TBST TSIZ[0-2] TRANSFER ATTRIBUTE CSE[0-1] TC[0-1]
603r
ADDRESS TERMINATION
AACK ARTRY
TRST, TCK, TMS, TDI, LSSD_MODE L1_TSTCLK, L2_TSTCLK OVDD AVDD
JTAG/COP INTERFACE LSSD TEST CONTROL
SYSCLK CLOCKS CLK_OUT PLL_CFG[0-3] POWER SUPPLY INDICATOR VOLTDETGND
POWER SUPPLY
Detailed Specifications
This specification describes specific requirements microprocessor TSPC603R, compliance with MIL-STD-883 class Atmel standard screening.
Applicable Documents
MIL-STD-883: Test methods procedures electronics MIL-PRF-38535: General specifications microcircuits microcircuits accordance with applicable documents specified herein.
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7.1.1
Design Construction
Terminal Connections Depending package, terminal connections shown Table 10-2 page Table 10-4 page "Recommended Operating Conditions" page Figure 15-2 page Figure 15-4 page Figure page Lead Material Finish Lead material finish shall specified MIL-STD-1835. (See "Package Mechanical Data" page 47.)
7.1.2
Absolute Maximum Ratings
Absolute maximum ratings stress ratings only functional operation maximum guaranteed. Stresses beyond those listed affect device reliability cause permanent damage device. 7.2.1 Absolute Maximum Ratings 603R(1)(2)(3)
Symbol AVDD OVDD TSTG -0.3 -0.3 -0.3 -0.3 2.75 2.75 +150 Unit
Parameter Core supply voltage supply voltage supply voltage Input voltage Storage temperature range Notes:
Caution: input voltage must greater than OVDD more than 2.5V time, including during power-on reset. Caution: OVDD voltage must greater than VDD/AVDD more than 1.2V time, including during power-on reset. Caution: VDD/AVDD voltage must greater than OVDD more than 0.4V time, including during power-on reset.
Functional operating conditions given electrical specifications. Stresses beyond absolute maximums listed affect device reliability cause permanent damage device. 7.2.2 Recommended Operating Conditions following recommended tested operating conditions. Proper device operation outside these ranges guaranteed. 7.2.3 Recommended Operating Conditions
Symbol AVDD OVDD 2.375 2.375 3.135 2.625 2.625 3.465 +125 +135 Unit
Parameter Core supply voltage supply voltage supply voltage Input voltage Operating temperature Junction operating temperature specific Cerquad
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Thermal Characteristics
CBGA CI-CGA Packages
data found this section concerns 603R devices packaged 255-lead multi-layer ceramic (MLC) ceramic package. Data included with Thermalloy #2328B heat sink. internal thermal resistance this package negligible exposed design. thermal interface material recommended package heat sink interface minimize thermal contact resistance. Additionally, CBGA package offers excellent thermal connection card power planes. Heat generated chip dissipated through package, heat sink (when used) card. parallel heat flow paths result lowest overall thermal resistance well offer significantly better power dissipation capability heat sink used. thermal characteristics flip-chip CBGA CI-CGA packages follows: Thermal resistance (junction-to-case) 0.095°C/Watt packages. Thermal resistance (junction-to-ball) 3.5°C/Watt CBGA package. Thermal resistance (junction-to-bottom SCI) 3.7°C/Watt CI-CGA package. junction temperature calculated from junction ambient thermal resistance, follow: Junction temperature: (Rjc Rsa)
where:
ambient temperature vicinity device junction case thermal resistance device case heat sink thermal resistance interface material heat sink ambient thermal resistance power dissipated device
During operation, die-junction temperatures (Tj) should maintained lower value than value specified "Recommended Operating Conditions" page thermal resistance thermal interface material (Rcs) typically about 1°C/Watt. Assuming 85°C consumption Watts, junction temperature device would follow: 85°C (0.095°C/Watt 1°C/Watt Rsa) Watts. Thermalloy heat sink #2328B, heat sink-to-ambient thermal resistance (Rsa) versus airflow velocity shown Figure 8-1.
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Figure 8-1.
Heat Sink Thermal Resistance
CBGA Thermal Management Example
Approach Velocity (m/sec)
(°C/W)
Assuming velocity m/sec, associated overall thermal resistance junction temperature, found Table will result. Table 8-1. Thermal Resistance Junction Temperature
(°C/W) (°C)
Configuration With 2328B heat sink
Vendors such Aavid, Thermalloy®, Wakefield Engineering supply heat sinks with wide range thermal performance.
HiTCE CBGA Package
Table 8-2. HiTCE CBGA Package
Symbol
Characteristic Junction-to-bottom balls
Value 22.4(2) 11.7(3)
Unit °C/W °C/W °C/W
RJMA
Junction-to-ambient thermal resistance natural convection, four-layer (2s2p) board Junction board thermal resistance Notes: Simulation, convection flow. JEDEC JESD51-2 with board horizontal. JEDEC JESD51-8 with board horizontal.
CERQUAD Package
This section provides thermal management data 603R. This information based typical desktop configuration using lead, wire-bond CERQUAD package with cavity (the silicon attached bottom package). This configuration enables dissipation through PCB. thermal characteristics wire-bond CERQUAD package follows: Thermal resistance (junction bottom case) (typical) 2.5°C/Watt Thermal resistance (junction case) typically 16°C/W
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8.3.1 Thermal Management Example junction temperature calculated from junction ambient thermal resistance, follows: Junction temperature: (Rcs Rsa) (Rjc Rsa) Where: ambient temperature vicinity device junction ambient resistance junction case thermal resistance device case heat sink thermal resistance interface material heat sink ambient thermal resistance power dissipated device Because dissipation made through PCB, user values, vary considerably depending customer's application. typical customer application, 0.5°C/W, 3°C/W 110°C, estimated. 110°C (2.5 125°C Note that verification external thermal resistance case temperature should performed each application. Thermal resistance depends many factors including amount turbulence therefore vary considerably.
Power Consideration
PowerPC 603R microprocessor specifically designed low-power operation. Like 603e microprocessor version, 603R provides both automatic program-controllable power reduction modes progressive reduction power consumption. This section describes hardware support provided 603R power management.
Dynamic Power Management
Dynamic power management automatically powers down individual execution units 603R, based upon contents instruction stream. example, floating-point instructions being executed, floating-point unit automatically powered down. Power actually removed from execution unit; instead, each execution unit independent clock input, which automatically controlled clock-by-clock basis. Since CMOS circuits consume negligible power when they switching, stopping clock execution unit effectively eliminates power consumption. operation completely transparent software external hardware. Dynamic power management enabled setting HID0 power-up, following HRESET.
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Programmable Power Modes
603R provides four programmable power states, full power, doze, sleep. software selects these modes setting (and only one) three power saving mode bits. hardware enable power management state through external asynchronous interrupts. hardware interrupt causes transfer program flow interrupt handler code. appropriate mode then software. 603R provides separate interrupt interrupt vector power management, System Management Interrupt (SMI). 603R also contains decrement timer which allows enter doze mode predetermined amount time then return full power operation through Decrementer Interrupt (DI). Note that 603R cannot switch from power-on management mode another without first returning full mode. sleep modes disable snooping; therefore, hardware handshake provided ensure coherency before 603R enters these power management modes. Table summarizes four power states.
Table 9-1.
Mode Full Power
Power 603R Microprocessor Programmable Power Modes
Functioning Units units active Requested logic demand snooping Data cache needed Decrementer timer Decrementer timer Activation Method instruction dispatch Controlled Full-power Wake-up Method External asynchronous exceptions(1) Decrementer interrupt Reset External asynchronous exceptions Decrementer interrupt Reset External asynchronous exceptions Reset
Full Power (with DPM) Doze
Controlled hardware software Controlled hardware software
Sleep Note:
None
Exceptions referred interrupts architecture specification.
Power Management Modes
following describes characteristics 603R's power management modes, requirements entering exiting various modes, system capabilities provided 603R while power management modes active. Full Power Mode with Disabled Full power mode with disabled; power mode selected when enable (bit HID0 cleared Default state following power-up HRESET functional units operating full processor speed times Full Power Mode with Enabled Full power mode with enabled (HID0[11] provides on-chip power management without affecting functionality performance 603R Required functional units operating full processor speed
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Functional units clocked only when needed software hardware intervention required after mode Software/hardware performance transparent Doze Mode doze mode disables most functional units maintains cache coherency enabling interface unit snooping. snoop will cause 603R enable data cache, copy data back memory, disable cache, fully return doze state. this mode: Most functional units disabled snooping time base/decrementer still enabled Dose mode sequence: doze (HID0[8) 603R enters doze mode after several processor clocks There several methods returning full-power mode Assert INT, SMI, decrementer interrupts Assert hard reset soft reset Transition full-power state takes more than processor cycles Phase Locked Loop (PLL) running locked SYSCLK Mode mode disables 603R still maintains phase locked loop (PLL) time base/decrementer. time base used restore 603R full-on state after programmed amount time. Because snooping disabled sleep modes, hardware handshake using quiesce request (QREQ) quiesce acknowledge (QACK) signals required maintain data coherency. 603R will assert QREQ signal indicate that ready disable snooping. When system ensured that snooping longer necessary, will assert QACK 603R will enter sleep mode. this mode: time base/decrementer still enabled Most functional units disabled (including snooping) non-essential input receivers disabled mode sequence: (HID0[9] 603R asserts quiesce request (QREQ) signal System asserts quiesce acknowledge (QACK) signal 603R enters sleep mode after several processor clocks There several methods returning full-power mode: Assert INT, SPI, decrementer interrupts Assert hard reset soft reset Transition full-power takes more than processor cycles running locked SYSCLK
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Sleep Mode Sleep mode consumes least amount power four modes since functional units disabled. conserve maximum amount power, disabled SYSCLK removed. fully static design 603R, internal processor state preserved when internal clock present. Because time base decrementer disabled while 603R sleep mode, 603R's time base contents will have updated from external time base following sleep mode accurate time-of-day maintenance required. Before 603R enters sleep mode, 603R will assert QREQ signal indicate that ready disable snooping. When system ensured that snooping longer necessary, will assert QACK 603R will enter sleep mode. this mode: functional units disabled (including snooping time base) non-essential input receivers disabled Internal clock regenerators disabled still running (see below) Sleep mode sequence sleep (HID0[10] 603R asserts quiesce request (QREQ) System asserts quiesce acknowledge (QACK) 603R enters sleep mode after several processor clocks There several methods returning full-power mode Assert INT, SMI, interrupts Assert hard reset soft reset disabled SYSCLK removed while sleep mode Return full-power mode after SYSCLK disabled sleep mode Enable SYSCLK Reconfigure into desired processor clock mode System logic waits startup relock time (100 System logic asserts sleep recovery signals (for example, SMI)
Power Management Software Considerations
Since 603R dual issue processor with out-of-order execution capabilities, care must taken with power management mode entered. Furthermore, sleep modes require outstanding operations completed before power management mode entered. Normally, during system configuration time, power management modes would selected setting appropriate HID0 mode bit. Later power management mode invoked setting MSR[POW] bit. provide clean transition into power management mode, stmsr[POW] should preceded sync instruction followed isync instruction.
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Power Dissipation
Power Dissipation(1)(2)(3)(4) with VDD/AVDD ±5%V, OVDD ±5%V, 125°C
Cerquad Package Clock Frequency Full-on Mode (DPM Enabled) Typical Doze Mode Typical Mode Typical Sleep Mode Typical Sleep Mode-PLL Disabled Typical CBGA 255, HiTCE CBGA CI-CGA Units
Table 9-2.
Sleep Mode-PLL SYSCLK Disabled Typical Maximum Notes:
These values apply valid PLL_CFG[0-3] settings include output driver power (OVDD) analog supply power (AVDD). OVDD power system dependent typically VDD. Worst case AVDD Typical power average value measured AVDD 2.5V, OVDD 3.3V, system executing typical applications benchmark sequences. Maximum power measured 2.625V using worst-case instruction mix. calculate power consumption temperature (-55°C), factor 1.25.
Marking
Each microcircuit legible permanently marked with least following information: Atmel logo Manufacturer's part number Class identification applicable Date code inspection identifier available Country manufacture
Assignments
10.1 CBGA CI-CGA Packages
Figure 10-1 (pin matrix) shows pinout viewed from CBGA CI-CGA packages. direction surface view shown side profile packages.
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Figure 10-1. CBGA 255, HiTCE CBGA CI-CGA View
matrix view
View Substrate Assembly
CBGA 255, CBGA HiTCE
Encapsulant
CI-CGA
scale
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10.1.1 Pinout Listing
Table 10-1.
Power Ground Pins
CBGA, HiTCE CBGA CI-CGA Number
(AVDD) Internal Logic(1) (VDD) Drivers(1) (OVDD) Notes:
F06, F08, F09, F11, G07, G10, H06, H08, H09, H11, J06, J08, J09, J11, K07, K10, L06, L08, L09, C07, E05, E07, E10, E12, G03, G05, G12, G14, K03, K05, K12, K14, M05, M07, M10, M12, P07, C05, C12, E03, E06, E08, E09, E11, E14, F05, F07, F10, F12, G06, G08, G09, G11, H05, H07, H10, H12, J05, J07, J10, J12, K06, K08, K09, K11, L05, L07, L10, L12, M03, M06, M08, M09, M11, M14, P05,
OVDD inputs apply power drivers inputs supply power processor core.
Table 10-2.
Signal Name A[0-31] AACK AP[0-3] ARTRY CKSTP_IN CKSTP_OUT CLK_OUT CSE[0-1] DBDIS DBWO DH[0-31] DL[0-31] DP[0-7] DRTRY
Signal Pinout Listing
CBGA, HiTCE CBGA CI-CGA Number C16, E04, D13, F02, D14, G01, D15, E02, D16, D04, E13, G02, E15, H01, E16, H02, F13, J01, F14, J02, F15, H03, F16, F04, G13, K01, G15, K02, H16, M01, J15, C01, B04, B03, B01, P14, T16, R15, T15, R13, R12, P11, N11, R11, T12, T11, R10, P09, N09, T10, R09, T09, P08, N08, R08, T08, N07, R07, T07, P06, N06, R06, T06, R05, N05, T05, K13, K15, K16, L16, L15, L13, L14, M16, M15, M13, N16, N15, N13, N14, P16, P15, R16, R14, T14, N10, P13, N12, T13, P03, N03, N04, R03, T01, T02, P04, T03, M02, L03, N02, L04, R01, P02, M04, Active High High High High High High Input Output Input Output Output Input Output Output Output Input Input Input Output Input
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Table 10-2.
Signal Name HRESET L1_TSTCLK(1) L2_TSTCLK(1) LSSD_MODE PLL_CFG[0-3] QACK QREQ RSRV SRESET SYSCLK TBEN TBST TC[0-1] TLBISYNC TRST TSIZ[0-2] TT[0-4]
Signal Pinout Listing (Continued)
CBGA, HiTCE CBGA CI-CGA Number A08, B09, A09, A02, A13, D10, B13, A15, B16, C14, B07, B08, C03, C06, C08, D05, D06, F03, H04,
Active High High High High High High High High
Input Input Input Input Input Input Input Input Output Output Input Input Input Input Input Output Input Input Output Input Input Input Input Output Input Output
VOLTDETGND Notes:
These test signals factory only must pulled OVDD normal machine operation. (not connected) 603e package; internally tied 603R package indicate power supply that low-voltage processor present.
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10.2
OGND OVDD OGND OVDD DBWO AACK QREQ ARTRY OGND OVDD OGND OVDD DL23 DL24 OGND OVDD DL25 DL26 DL27 DL28 OGND
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CERQUAD Package
Figure 10-2. CERQUAD 240: View
VIEW
OVDD DL29 DL30 DL31 DH31 DH30 DH29 OGND OVDD DH28 DH27 DH26 DH25 DH24 DH23 OGND DH22 OVDD DH21 DH20 DH19 DH18 DH17 DH16 OGND DH15 OVDD DH14 DH13 DH12 DH11 DH10 OGND OVDD DL22 DL21 DL20 OGND OVDD DL19 DL18 DL17 OGND OVDD DL16 DL15 DL14 OGND
OVDD OGND QACK TBEN TLBISYNC RSRV OVDD OGND CSE0 OVDD CLK_OUT OGND CKSTP_OUT CKSTP_IN HRESET PLL_CFG0 SYSCLK PLL_CFG1 PLL_CFG2 AVDD PLL_CFG3 LSSD_MODE L1_TSTCLK L2_TSTCLK TRST TSIZ0 TSIZ1 TSIZ2 OVDD OGND TBST SRESET OVDD OGND
OVDD OGND OVDD OGND DRTR DBDIS CSE1 OVDD OGND OVDD OGND OVDD OGND DL10 DL11 DL12 DL13 OVDD
TSPC603R
10.2.1
Pinout Listing Power Ground Pins
CERQUAD Number
Table 10-3.
(AVDD) Internal Logic Output Drivers
122, 137, 147, 157, 167, 177, 104, 112, 121, 128, 138, 148, 163, 173, 183, 194, 222, 229, 19,29, 116, 132, 142, 152, 162, 172, 182, 206, 103, 111, 120, 127, 136, 146, 161, 171, 181, 193, 220, 228,
Table 10-4.
Signal Name A[0-31] AACK AP[0-3] ARTRY CKSTP_IN CKSTP_OUT CLK_OUT CSE[0-1] DBDIS DBWO DH[0-31] DL[0-31] DP[0-7] DRTRY HRESET
Signal Pinout Listing
CERQUAD Number 179, 178, 176, 175, 174, 170, 169, 168, 166, 165, 164, 160, 159, 158, 151, 144, 231,230,227,226 225,150 115, 114, 113, 110, 109, 108, 143, 141, 140, 139, 135, 134, 133, 131, 130, 129, 126, 125, 124, 123, 119, 118, 117, 107, 106, 105, 102, 101, 100,
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Table 10-4.
Signal Name L1_TSTCLK L2_TSTCLK
Signal Pinout Listing (Continued)
CERQUAD Number 213, 211, 210, 224, 197, 196, 191, 190, 185, 184,
LSSD_MODE(1) PLL_CFG[0-3] QACK QREQ RSRV SRESET SYSCLK TBEN TBST TC[0-1] TLBISYNC TRST TSIZ[0-2] TT[0-4] Notes:
These test signals factory only must pulled normal machine operation. OVDD inputs supply power drivers inputs supply power processor core. Future members family different OVDD input levels.
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Table 10-5.
Signal Name Address Data Data
Address Data Signal Index Cerquad, CBGA CI-CGA Packages
Abbreviation A[0-31] DH[0-31] DL[0-31] Signal Function output, physical address data transferred input, represents physical address snoop operation Represents state data, during data write operation output, during data read operation input Represents state data, during data write operation output, during data read operation input Signal Type
Table 10-6.
Signal Name
Signal Index Cerquad, CBGA 255, HiTCE CBGA CI-CGA Packages
Abbreviation AACK Signal Function address phase transaction complete output, 603R address master input, address output, represents parity each bytes physical address transaction input, represents parity each bytes physical address snooping operations Incorrect address parity detected snoop output, detects condition which snooped address tenure must retried input, must retry preceding address tenure May, with proper qualification, assume mastership address Request mastership address single-beat transfer will cached Must terminate operation internally gating clocks, release outputs detected checkstop condition ceased operation Cache replacement element current transaction reloading into writing cache output, 603R data master input, another device master (For write transaction) must release data data parity high impedance during following cycle May, with proper qualification, assume mastership data data tenure output, parity each bytes data write transactions input, parity each byte read data Incorrect data parity Must invalidate data from previous read operation Signal Type Input
Address Acknowledge Address Busy
Address Parity
AP[0-3]
Address Parity Error Address Retry Grant Request Cache Inhibit Checkstop Input Checkstop Output Cache Entry Data Busy Data Disable Data Grant Data Write Only Data Parity Data Parity Error Data Retry
ARTRY CKSTP_IN CKSTP_OUT CSE[0-1] DBDIS DBW0 DP[0-7] DRTRY
Output Input Output Output Input Output Output Input Input Input Output Input
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Table 10-6.
Signal Name Global Hard Reset Interrupt
Signal Index Cerquad, CBGA 255, HiTCE CBGA CI-CGA Packages (Continued)
Abbreviation HRESET LSSD_MODE Signal Function output, transaction global input, transaction must snooped 603R Initiates complete hard reset operation Initiates interrupt register LSSD test control signal factory only LSSD test control signal factory only LSSD test control signal factory only Initiates machine check interrupt operation register EMCP HID0 register Configures operation internal processor clock frequency Available only package Indicates power supply that low-voltage processor present. activity terminated 603R enter quiescent power) state requesting activity normally enter quiescent (low power) state Represents state reservation coherency reservation address register Initiates system management interrupt operation register Initiates processing reset exception Represents primary clock input 603R, clock frequency 603R operation Provides clock output testing monitoring single-beat data transfer completed successfully data beat burst transfer completed successfully timebase should continue clocking output, burst transfer progress input, when snooping single-beat reads Special encoding transfer progress Clock signal IEEE P1149.1 test access port (TAP) Serial data input Serial data output error occurred Instruction execution should stop after execution tlbsync instruction Selects principal operations test-support circuitry Provides asynchronous reset controller memory accesses, these signals along with TBST indicate data transfer size current operation Signal Type Input Input Input Input Input Input Input Output Input Output Output Input Input Input Output Input Input Output Input Input Output Input Input Input Input
Factory Test
L1_TSTCLK L2_TSTCLK
Machine Check Interrupt Configuration Power supply indicator Quiescent Acknowledge Quiescent Request Reservation System Management Interrupt Soft Reset System Clock Test Clock Transfer Acknowledge Timebase Enable Transfer Burst Transfer Code Test Clock Test Data Input Test Data Output Transfer Error Acknowledge TLBI Sync Test Mode Select Test Reset Transfer Size
PLL_CFG[0-3] VOLTDETGND QACK QREQ RSRV SRESET SYSCLK CLK_OUT TBEN TBST TC[0-1] TLBISYNC TRST TSIZ[0-2]
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Table 10-6.
Signal Name
Signal Index Cerquad, CBGA 255, HiTCE CBGA CI-CGA Packages (Continued)
Abbreviation Signal Function output, begun memory transaction address transfer attribute signals valid input, another master begun transaction address transfer attribute signals valid snooping (see GBL) Type transfer progress single-beat transaction write-through Signal Type
Transfer Start
Transfer Type Write-through
TT[0-4]
Output
Electrical Characteristics
11.1 General Requirements
static dynamic electrical characteristics specified inspection purposes relevant measurement conditions given below: Table 11-1: Static electrical characteristics electrical variants Table 11-2: Dynamic electrical characteristics 603R processor core frequency determined (SYSCLK) frequency settings PLL_CFG0 PLL_CFG3 signals. timings respectively specified rising edge SYSCLK. These specifications processor core frequencies CBGA 255, HiTCE CBGA CI-CGA packages processor core frequencies Cerquad package.
11.2
Static Characteristics
Electrical Characteristics with AVDD 2.5V ±5%; OVDD ±5%V, -55°C 125°C
Symbol CVIH CVIL 3.465V 5.5V
(1)(3)
Table 11-1.
Characteristics Input High Voltage (all inputs except SYSCLK) Input Voltage (all inputs except SYSCLK) SYSCLK Input High Voltage SYSCLK Input Voltage Input Leakage Current Hi-Z (off-state) Leakage Current Output High Voltage Output Voltage Capacitance,
Unit
ITSI ITSI
(1)(3) (1)(3)
3.465V
5.5V(1)(3) (excludes ABB, DBB, ARTRY)
Capacitance, MHz(2) (for ABB, DBB, ARTRY) Notes:
Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK, JTAG signals). Capacitance periodically sampled rather than 100% tested.
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Leakage currents measured nominal OVDD both OVDD VDD. Same variation (for example, both OVDD vary either -5%)
11.3
11.3.1
Dynamic Characteristics
Clock Specifications Table 11-2 provides clock timing specifications defined Figure 11-1. Clock Timing Specifications(1)(2)(3)(4) with AVDD 2.5V ±5%; OVDD ±5%V, -55°C 125°C
CBGA 255, HiTCE CBGA 255, CI-CGA CERQUAD
Table 11-2.
CBGA 255, HiTCE CBGA CI-CGA 33.3 13.3 33.3 13.3 33.3 13.3 Unit
Figure Number
Characteristics Processor Frequency Frequency SYSCLK (bus) Frequency 66.7
33.3 13.3 66.7
Note
SYSCLK Cycle Time SYSCLK Rise Fall Time SYSCLK Duty Cycle (1.4V measured) SYSCLK Jitter 603R Internal Relock Time
±150
±150
±150
±150
±150
(3)(4)
Notes:
Rise fall times SYSCLK input measured from 0.4V 2.4V. Cycle-to-cycle jitter guaranteed design. Timing guaranteed design characterization tested. relock time maximum amount time required lock after stable VDD, OVDD, AVDD SYSCLK reached during power-on reset sequence. This specification also applies when been disabled subsequently re-enabled during sleep mode. Also note that HRESET must held asserted minimum clocks after relock time (100 during power-on reset sequence. Caution: SYSCLK frequency PLL_CFG[0-3] settings must chosen that resulting SYSCLK (bus) frequency, (core) frequency, (VCO) frequency exceed their respective maximum minimum operating frequencies. Refer PLL_CFG[0-3] signal description valid PLL_CFG[0-3] settings.
Figure 11-1. SYSCLK Input Timing Diagram
CVih CVil
SYSCLK
Midpoint Voltage (1.4V)
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11.3.2
Input Specifications Table 11-3 provides input timing specifications 603R defined Figure 11-2 Figure 11-3. Input Timing Specifications(1) with AVDD 2.5V ±5%; OVDD ±5%V, -55°C 125°C
CBGA 255, HiTCE CBGA 255, CI-CGA Cerquad Packages
Table 11-3.
CBGA 255, HiTCE CBGA CI-CGA 233, Unit tsyscl
Figure Number Notes:
166, Characteristics Address/data/transfer attribute inputs valid SYSCLK (input setup) other inputs valid SYSCLK (input setup) Mode select inputs valid HRESET (input setup) (for DRTRY, QACK TLBISYNC) SYSCLK address/data/transfer attribute inputs invalid (input hold) SYSCLK other inputs invalid (input hold) HRESET mode select inputs invalid (input hold) (for DRTRY, QACK, TLBISYNC)
Note
(4)(5)(6 )(7)
(4)(6)
input specifications measured from level (0.8 signal question 1.4V rising edge input SYSCLK. Both input output timings measured pin. Figure 11-3. Address/data/transfer attribute input signals composed following: A[0-31], AP[0-3], TT[0-4], TC[0-1], TBST, TSIZ[0-2], GBL, DH[0-31], DL[0-31], DP[9-7]. other input signals composed following: ABB, DBB, ARTRY, AACK, DBG, DBWO, DRTRY, TEA, DBDIS, HRESET, SRESET, INT, SMI, MCP, TBEN, QACK, TLBISYNC. setup hold time with respect rising edge HRESET. Figure 11-3. tsysclk period external clock (SYSCLK) nanoseconds (ns). numbers given table must multiplied period SYSCLK compute actual time duration nanoseconds) parameter question. These values guaranteed design, tested. This specification configuration mode only. Also note that HRESET must held asserted minimum clocks after relock time (100 during power-on reset sequence.
Figure 11-2. Input Timing Diagram
SYSCLK
inputs
Midpoint Voltage (1.4V)
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Figure 11-3. Mode Select Input Timing Diagram
HRESET
MODE PINS Midpoint Voltage (1.4V)
11.3.3
Output Specifications Table 11-4 provides output timing specifications 603R (shown Figure 11-4). Output Timing Specifications(1)(2) with AVDD 2.5V ±5%; OVDD ±5%V, 55°C 125°C
CBGA 255, HiTCE CBGA 255, CI-CGA Cerquad Packages 166,
Table 11-4.
CBGA 255, HiTCE CBGA CI-CGA 233, tSYSCLK tSYSCLK Unit tSYSCLK
(3)(5) (5)(7)
Number
Characteristics SYSCLK output driven (output enable time) SYSCLK output valid (5.5V 0.8V ABB, ARTRY, DBB) SYSCLK output valid (TS, ABB, ARTRY, DBB) SYSCLK output valid (5.5V 0.8V except ABB, ARTRY, DBB) SYSCLK output valid (all except ABB, ARTRY, DBB) SYSCLK output invalid (output hold) SYSCLK output high impedance (all except ARTRY, ABB, DBB) SYSCLK ABB, DBB, high impedance after precharge SYSCLK ARTRY high impedance before precharge SYSCLK ARTRY precharge enable Maximum delay ARTRY precharge SYSCLK ARTRY high impedance after precharge
tSYSCLK
Note
tSYSCLK tSYSCLK
(5)(8)
(6)(8)
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Notes:
output specifications measured from 1.4V rising edge SYSCLK level (0.8V signal question. Both input output timings measured pin. Figure 11-4. maximum timing specifications assume This minimum parameter assumes SYSCLK output valid (5.5V 0.8V) includes extra delay associated with discharging external voltage from 5.5V 0.8V instead from 0.8V CMOS levels instead 3.3V CMOS levels). tsysclk period external clock (SYSCLK) nanoseconds (ns). numbers given table must multiplied period SYSCLK compute actual time duration (ns) parameter question. output signal transitions from 0.8V. nominal precharge width tsysclk. nominal precharge width ARTRY tsysclk.
Figure 11-4. Output Timing Diagram
SYSCLK
OUTPUTS (Except ABB, DBB, ARTRY)
ABB,
ARTRY
Midpoint Voltage (1.4V)
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11.4 JTAG Timing Specifications
JTAG Timing Specifications (independent SYSCLK); AVDD 2.5V ±5%; OVDD ±5%V, -55°C 125°C
Characteristics frequency operation Notes: cycle time clock pulse width measured 1.4V rise fall times TRST setup time rising edge TRST assert time Boundary scan input data setup time Boundary scan input data hold time output data valid output high impedance TMS, data setup time TMS, data hold time data valid high impedance 62.5 Unit
Table 11-5.
Number
Notes
TRST asynchronous signal. setup time test purposes only. Non-test signal input timing with respect TCK. Non-test signal output timing with respect TCK.
Figure 11-5. Clock Input Timing Diagram
Midpoint Voltage (1.4V)
Figure 11-6. TRST Timing Diagram
TRST
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Figure 11-7. Boundary-scan Timing Diagram
Data Inputs Data Outputs Data Outputs Data Outputs Output data valid Output data valid
Input data valid
Figure 11-8. Test Access Port Timing Diagram
TDI, Output Data Valid Output Data Valid
Input Data Valid
Functional Description
12.1 PowerPC Registers Programming Model
PowerPC architecture defines register-to-register operations most computational instructions. Source operands these instructions accessed from registers provided immediate values embedded instruction opcode. three-register instruction format allows specification target register distinct from source operands. Load store instructions transfer data between registers memory. PowerPC processors have levels privilege-supervisor mode operation (typically used operating system) user mode operation (used application software). programming models incorporate GPRs, FPRs, Special-purpose Registers (SPRs) several miscellaneous registers. Each PowerPC microprocessor also unique Hardware Implementation (HID) registers.
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Having access privilege instructions, registers, other resources allows operating system control application environment (providing virtual memory protecting operating system critical machine resources). Instructions that control state processor, address translation mechanism, supervisor registers executed only when processor operating supervisor mode. following sections summarize PowerPC registers that implemented 603R.
12.1.1
General-purpose Registers (GPRs) PowerPC architecture defines user-level, General-purpose Registers (GPRs). These registers either bits wide 32-bit PowerPC microprocessors bits wide 64-bit PowerPC microprocessors. GPRs serve data source destination integer instructions.
12.1.2
Floating-point Registers (FPRs) PowerPC architecture also defines user-level, 64-bit Floating-point Registers (FPRs). FPRs serve data source destination floating-point instructions. These registers contain data objects either single- double-precision floating-point formats.
12.1.3
Condition Register (CR) 32-bit user-level register that consists eight four-bit fields that reflect results certain operations, such move, integer floating-point compare, arithmetic, logical instructions, provide mechanism testing branching.
12.1.4
Floating-Point Status Control Register (FPSCR) Floating-point Status Control Register (FPSCR) user-level register that contains exception signal bits, exception summary bits, exception enable bits, rounding control bits needed compliance with IEEE standard.
12.1.5
Machine State Register (MSR) Machine State Register (MSR) supervisor-level register that defines state processor. contents this register saved when exception taken restored when exception handling completed. 603R implements 32-bit register, 64-bit PowerPC processors implement 64-bit MSR.
12.1.6
Segment Registers (SRs) memory management, 32-bit PowerPC microprocessors implement sixteen 32-bit Segment Registers (SRs). speed access, 603R implements segment registers arrays; main array (for data memory accesses) shadow array (for instruction memory accesses). Loading segment entry with Move Segment Register (STSR) instruction loads both arrays.
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12.1.7
Special-purpose Registers (SPRs) powerPC operating environment architecture defines numerous special-purpose registers that serve variety functions, such providing controls, indicating status, configuring processor, performing special operations. During normal execution, program access registers, shown Figure 12-1 page depending program's access privilege (supervisor user, determined privilege-level (PR) MSR. Note that registers such GPRs FPRs accessed through operands that part instructions. Access registers explicit (that through specific instructions that purpose such Move special-purpose register (mtspr) move from special-purpose register (mfspr) instructions implicit, part execution instruction. Some registers accessed both explicitly implicitly. 603R, SPRs bits wide. User-level SPRs: following 603R SPRs accessible user-level software: Link Register (LR) link register used provide branch target address hold return address after branch link instructions. bits wide 32-bit implementations. Count Register (CTR) decremented tested automatically result branch-and-count instructions. bits wide 32-bit implementations. Integer Exception Register (XER) 32-bit contains summary overflow bit, integer carry bit, overflow bit, field specifying number bytes transferred Load String Word Indexed (LSWX) Store String Word Indexed (STSWX) instruction. Supervisor-level SPRs: 603R also contains SPRs that accessed only supervisor-level software. These registers consist following: 32-bit DSISR defines cause data access alignment exceptions. Data Address Register (DAR) 32-bit register that holds address access after alignment exception. Decrementer register (DEC) 32-bit decrementing counter that provides mechanism causing decrementer exception after programmable delay. 32-bit SDR1 specifies page table format used virtual-to-physical address translation pages. (Note that physical address referred real address architecture specification). machine status Save/Restore Register (SRR0) 32-bit register that used 603R saving address instruction that caused exception, address return when Return from Interrupt (RFI) instruction executed. machine status Save/Restore Register (SRR1) 32-bit register used save machine status exceptions restore machine status when instruction executed. 32-bit SPRG0-SPRG3 registers provided operating system use. External Access Register (EAR) 32-bit register that controls access external control facility through External Control Word Indexed (ECIWX) External Control Word Indexed (ECOWX) instructions.
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Time Base register (TB) 64-bit register that maintains time operates interval timers. consists 32-bit fields Time Base Upper (TBU) Time Base Lower (TBL). Processor Version Register (PVR) 32-bit, read-only register that identifies version (model) revision level PowerPC processor. Block Address Translation (BAT) arrays PowerPC architecture defines registers, divided into four pairs Data BATs (DBATs) four pairs instruction BATs (IBATs). Figure 12-1 list numbers arrays. following supervisor-level SPRs implementation-specific 603R: DMISS IMISS registers read-only registers that loaded automatically upon instruction data miss. HASH1 HASH2 registers contain physical addresses primary secondary Page Table Entry Groups (PTEGs). ICMP DCMP registers contain duplicate first word Page Table Entry (PTE) which table search looking. Required Physical Address (RPA) register loaded processor with second word correct during page table search. hardware implementation (HID0 HID1) registers provide means enabling 603R's checkstops features, allows software read configuration configuration signals. Instruction Address Breakpoint Register (IABR) loaded with instruction address that compared instruction addresses dispatch queue. When address match occurs, instruction address breakpoint exception generated. Figure 12-1 shows 603R registers available user supervisor level. number right SPRs indicate number that used syntax instruction operands access register.
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Figure 12-1. PowerPC Microprocessor Programming Model Register
SUPERVISOR MODEL Configuration Registers USER MODEL General-purpose Registers GPR0 GPR1 Instruction Registers GPR31 IBAT0U IBAT0L IBAT1U Floating-point Registers FPR0 FPR1 IBAT1L IBAT2U IBAT2L IBAT3U IBAT3L GPR31 SDR1 SDR1 Condition Register Exception Handling Registers Floating-point Status Control Register FPSCR Link Register Count Register SPR9 SPR8 SPR1 Data Address Register SPRGs SPRG0 SPRG1 SPRG2 SPRG3 Miscellaneous Registers Time Base Facility (for writing) External Address Register (Optional) Decrementer DSISR DSISR Save Restore SRR0 SRR1 Hardware Implementation Registers(1) HID0 HID1 SPR1 SPR1 Memory Management Registers Data Registers DBAT0U DBAT0L DBAT1U DBAT1L DBAT2U DBAT2L DBAT3U DBAT3L Software Table Search Registers(1) DMISS DCMP HASH1 HASH2 IMISS ICMP Machine State Register Processor Version Register
Segment Registers
Time Base Facility (for reading)
Instruction Address Breakpoint Register(1) IABR 1010
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12.2 Instruction Addressing Modes
following subsections describe PowerPC instruction addressing modes general. 12.2.1 PowerPC Instruction Addressing Modes PowerPC instructions encoded single-word (32-bit) opcodes. Instruction formats consistent among instruction types, permitting efficient decoding occur parallel with operand accesses. This fixed instruction length consistent format greatly simplifies instruction pipelining. PowerPC Instruction PowerPC instructions divided into following categories: Integer Instructions these include computational logical instructions Integer arithmetic instructions Integer compare instructions Integer logical instructions Integer rotate shift instructions Floating-point Instructions these include floating-point computational instructions, well instructions that affect FPSCR Floating-point arithmetic instructions Floating-point multiply/add instructions Floating-point rounding conversion instructions Floating-point compare instructions Floating-point status control instructions Load/Store Instructions these include integer floating-point load store instructions Integer load store instruction Integer load store multiple instructions Floating-point load store Primitives used construct atomic memory operations (lwarx stwcx instructions) Flow Control Instructions these include branching instructions, condition register logical instructions, trap instructions, other instructions that affect instruction flow Branch trap instructions Condition register logical instructions Processor Control Instructions these instructions used synchronizing memory accesses management caches, TLBs, segment registers Move to/from instructions Move to/from Synchronize Instruction synchronize
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Memory Control Instructions these instructions provide control caches, TLBs, segment registers Supervisor-level cache management instructions User-level cache instructions Segment register manipulation instructions Translation lookaside buffer management instructions Note that this grouping instructions does indicate which execution unit executes particular instruction group instructions. Integer instructions operate byte, half-word, word operands. Floating-point instructions operate single-precision (one word) double-precision (one double word) floating-point operands. PowerPC architecture uses instructions that four bytes long word-aligned. provides byte, half-word, word operand loads stores between memory GPRs. also provides word double-word operand loads stores between memory Floating-point Registers (FPRs). Computational instructions modify memory. memory operand computation then modify same another memory location, memory contents must loaded into register, modified, then written back target location with distinct instructions. PowerPC processors follow program flow when they normal execution state. However, flow instructions interrupted directly execution instruction asynchronous event. Either kind exception cause several components system software invoked. Calculating Effective Address Effective Address (EA) 32-bit address computed processor when executing memory access branch instruction when fetching next sequential instruction. PowerPC architecture supports simple memory addressing modes: (RA|0) offset (including offset (register indirect with immediate index) (RA|0) (register indirect with index) These simple addressing modes allow efficient address generation memory accesses. Calculation effective address aligned transfers occurs single clock cycle. memory access instruction, effective address operand length exceeds maximum effective address, memory operand considered wrap around from maximum effective address effective address Effective address computations both data instruction accesses 32-bit unsigned binary arithmetic. carry over from ignored 32-bit implementations.
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12.2.2 PowerPC 603R Microprocessor Instruction 603R instruction defined follows: 603R provides hardware support 32-bit PowerPC instructions. 603R provides implementation-specific instructions used software table search operations following misses: Load Data Entry (tlbld) Load Instruction Entry (tlbli) 603R implements following instructions which defined optional PowerPC architecture External Control Word Indexed (eciwx) External Control Word Indexed (ecowx) Floating Select (fsed) Floating Reciprocal Estimate Single-Precision (fres) Floating Reciprocal Square Root Estimate (frsqrte) Store Floating-Point Integer Word (stfiwx)
12.3
Cache Implementation
following subsections describe PowerPC architecture deals with cache general, 603R's specific implementation.
12.3.1
PowerPC Cache Characteristics PowerPC architecture does define hardware aspects cache implementations. example, some PowerPC processors, including 603R, have separate instruction data caches (harvard architecture). PowerPC microprocessor controls following memory access modes page block basis: Write-back/write-through mode Cache-inhibited mode Memory coherency Note that 603R, cache line defined eight words. defines cache management instructions that provide means which application programmer affect cache contents.
12.3.2
PowerPC 603R Microprocessor Cache Implementation 603R 16-Kbyte, four-way set-associative (instruction data) caches. caches physically addressed, data cache operate either write-back write-through modes specified PowerPC architecture. data cache configured sets four lines each. Each line consists bytes, state bits, address tag. state bits implement three-state (Modified/Exclusive/Invalid) protocol. Each line contains eight 32-bit words. Note that PowerPC architecture defines term block cacheable unit. 603R, block size equivalent cache line. block diagram data cache organization shown Figure 12-2 page
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instruction cache also consists sets lines, each line consists bytes, address tag, valid bit. instruction cache written except through line fill operation. instruction cache snooped, cache coherency must maintained software. fast hardware invalidation capability provided support cache maintenance. organization instruction cache very similar data cache shown Figure 12-2 page Each cache line contains eight contiguous words from memory that loaded from 8-word boundary (that bits A27-A32 effective addresses zero); thus, cache line never crosses page boundary. Misaligned accesses across page boundary incur performance penalty. 603's cache lines loaded four beats bits each. burst load performed "critical double word first". cache that being loaded blocked internal accesses until load completed. critical double word simultaneously written cache forwarded requesting unit, thus minimizing stalls load delays. ensure coherency among caches multiprocessor multiple caching device) implementation, 603R implemements protocol. These three states, modified, exclusive, invalid, indicate state cache block follows: Modified cache line modified with respect system memory; that data this address valid only cache system memory Exclusive this cache line holds valid data that identical data this address insystem memory. other cache this data Invalid this cache line does hold valid data Cache coherency enforced on-chip snooping logic. Since 603R's data cache tags single ported, simultaneous load store snoop access represent resource contention. snoop access granted first access tags. load store then occurs clock following snoop. Figure 12-2. Data Cache Organization
sets
Block Block Block Block
Address Address Address Address
State State State State
Words 0-07 Words 0-07 Words 0-07 Words 0-07 words/block
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12.3.3 Exception Model following subsections describe PowerPC exception model 603R implementation.
12.3.4
PowerPC Exception Model PowerPC exception mechanism allows processor change supervisor state result external singles, errors, unusual conditions arising execution instructions, differ from arithmetic exceptions defined IEEE floating-point operations. When exceptions occur, information about state processor saved certain registers processor begins execution address (exception vector) predetermined each exception. Processing exceptions occurs supervisor mode. Although multiple exception conditions single exception vector, more specific condition determined examining register associated with exception example, DSISR FPSCR. Additionally, some exception conditions explicitly enabled disabled software. PowerPC architecture requires that exceptions handled program order; therefore, although particular implementation recognize exception conditions order, they presented strictly order. When instruction-caused exception recognized, unexecuted instructions that appear earlier instruction stream, including that have entered execute state, must completed before exception taken. exceptions caused such instructions handled first. Likewise, exceptions that asynchronous precise recognized when they occur, handled until instruction currently completion state successfully completes execution generates exception, completed store queue emptied. Unless catastrophe event causes system reset machine check exception, only exception handled time. example, single instruction encounters multiple exception conditions, those conditions encountered sequentially. After exception handler handles exception, instruction execution continues until next exception condition encountered. However, many cases there attempt re-execute instruction. This method recognizing handling exception conditions sequentially guarantees that exceptions recoverable. Exception handlers should save information stored SRR0 SRR1 early prevent program state from being lost system reset machine check exception instruction-caused exception exception handler, before enabling external interrupts. PowerPC architecture supports four types exceptions: Synchronous, Precise these caused instructions. instruction-caused exceptions handled precisely; that machine state time exception occurs known completely restored. This means that (excluding trap system call exceptions) address faulting instruction provided exception handler that neither faulting instruction subsequent instructions code stream will complete execution before exception taken. Once exception processed, execution resumes address faulting instruction alternate address provided exception handler). When exception taken trap system call instruction, execution resumes address provided handler.
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Synchronous, Imprecise PowerPC architecture defines imprecise floating-point exception modes, recoverable nonrecoverable. Even though 603R provides means enable imprecise modes, implements these modes identically precise mode (That enabled floating-point exceptions always precise 603R). Asynchronous, Maskable external, SMI, decrementer interrupts maskable asynchronous exceptions. When these exceptions occur, their handling postponed until next instruction, exceptions associated with that instruction completes execution. there instructions execution units, exception taken immediately upon determination correct restart address (for loading SRR0). Asynchronous, Non-maskable there non-maskable asynchronous exceptions: system reset machine check exception. These exceptions recoverable, provide limited degree recoverability. exceptions report recoverability through SMR[RI] bit. 12.3.5 PowerPC 603R Microprocessor Exception Model specified PowerPC architecture, 603R exceptions described either precise imprecise either synchronous asynchronous. Asynchronous exceptions (some which maskable) caused events external processor's execution; synchronous exceptions, which handled precisely 603R, caused instructions. 603R exception classes shown Table 12-1. Table 12-1. PowerPC 603R Microprocessor Exception Classifications
Precise/Imprecise Imprecise Exception Type Machine check System reset External interrupt Decrementer System management interrupt Instruction-caused exceptions
Synchronous/Asynchronous Asynchronous, Maskable
Asynchronous, Maskable Synchronous
Precise Precise
Although exceptions have other characteristics well, such whether they maskable non-maskable, distinctions shown Table 12-1 define categories exceptions that 603R handles uniquely. Note that Table 12-1 includes synchronous imprecise instructions. While PowerPC architecture supports imprecise handling floating-point exceptions, 603R implements these exception modes precise exceptions. 603R's exceptions, conditions that cause them, listed Table 12-2. Exceptions that specific 603R indicated. Table 12-2. Exceptions Conditions
Vector Offset (hex) 00000 00100 00200 Causing Conditions system reset caused assertion either SRESET HRESET machine check caused assertion signal during data transaction, assertion MCP, address data parity error
Exception Type Reserved System reset Machine check
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Table 12-2. Exceptions Conditions (Continued)
Vector Offset (hex) Causing Conditions cause exception determined settings DSISR, listed follows: translation attempted access found primary hash table entry group (HTEG), rehashed secondary HTEG, range DBAT register; otherwise cleared memory access permitted page DBAT protection mechanism; otherwise cleared eciwx ecowx instruction access address that marked write-through, execution load/store instruction that accesses direct-store segment store operation cleared load operation eciwx ecowx used EAR[E] cleared exception caused when instruction fetch cannot performed following reasons:
Exception Type
00300
00400
effective (logical) address cannot translated. That there page fault this portion translation, exception must taken load (and possibly page) into memory fetch access violates memory protection. bits segment register bits prohibit read access, instructions cannot fetched from this location
External interrupt
00500
external interrupt caused when MSR[EE] signal asserted alignment exception caused when 603e cannot perform memory access reasons described below:
operand floating-point load store instruction word-aligned operand lmw, stmw, lwarx, stwcx, instructions aligned
Alignment 00600
operand single-register load store operation aligned, 603e little-endian mode instruction lmw, stmw, lswi, lwsx, stswi, stswx 603e littleendian mode operand dcbz storage that write-through-required, caching inhibited
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Table 12-2.
Exceptions Conditions (Continued)
Vector Offset (hex) Causing Conditions program exception caused following exception conditions, which correspond settings SRR1 arise during execution instruction:
Exception Type
Floating-point enabled exception floating-point enabled exception condition generated when following condition met: (MSR[FE0] MSR[FE1]) FPSCR[FEX] FPSER[FEX] execution floating-point instruction that causes enabled exception execution "move FPSCR" instructions that results both exception condition corresponding enable being FPSCR Illegal instruction illegal instruction program exception generated when execution instruction attempted with illegal opcode illegal combination opcode extended opcode fields (including PowerPC instructions implemented 603e), when execution optional instruction provided 603e attempted (these include those optional instructions that treated no-ops) Privileged instruction privileged instruction type program exception generated when execution privileged instruction attempted register user privilege bit, MSR[PR], set. 603e, this exception generated mtspr mfspr with invalid field SPR[0] MSR[PR] This true PowerPC processors Trap trap type program exception generated when conditions specified trap instruction
Floating-point unavailable Decrementer Reserved System call Trace Reserved Reserved Instruction translation miss Data load translation miss Data store translation miss 00800 floating-point unavailable exception caused attempt execute floating-point instruction (including floating-point load, store, more instructions) when floatingpoint available disabled, (MSR[FP] decrementer exception occurs when most significant decrementer (DEC) register transitions from Must also enabled with MSR[EE] system call exception occurs when System Call (sc) instruction executed trace execution taken when MSR[SE] when currently completing instruction branch MSR[BE] 603e does generate exception this vector. Other PowerPC processors this vector floating-point assist exceptions instruction translation miss exception caused when effective address instruction fetch cannot translated ITLB data load translation miss exception caused when effective address data load operation cannot translated DTLB data store translation miss exception caused when effective address data store operation cannot translated DTLB; where DTLB occurs, change must data store operation
Program
00700
00900 00A00-00BFF 00C00 00D00 00E00 00E10-00FFF 01000 01100
01200
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Table 12-2. Exceptions Conditions (Continued)
Vector Offset (hex) 01300 Causing Conditions instruction address breakpoint exception occurs when address (bits 0-29) IABR matches next instruction complete completion unit, IABR enable (bit system management interrupt caused when MSR[EE] input signal asserted
Exception Type Instruction address breakpoint System management interrupt Reserved
01400 01500-02FFF
12.4
Memory Management
following subsections describe memory management features PowerPC architecture, 603R implementation, respectively.
12.4.1
PowerPC Memory Management primary functions translate logical (effective) addresses physical addresses memory accesses, provide access protection blocks pages memory. There types accesses generated 603R that require address translation instruction accesses, data accesses memory generated load store instructions. PowerPC exception model support demand-paged virtual memory. Virtual memory management permits execution programs larger than size physical memory; demand-paged implies that individual pages loaded into physical memory from system memory only when they first accessed executing program. hashed page table variable-sized data structure that defines mapping between virtual page numbers physical page numbers. page table size power starting address multiple size. page table contains number Page Table Entry Groups (PTEGs). PTEG contains eight Page Table Entries (PTEs) eight bytes each; therefore, each PTEG bytes long. PTEG addresses entry points table search operations. Address translations enabled setting bits MSR-MSR[IR] enables instruction address translations MSR[DR] enables data address translations.
12.4.2
PowerPC 603R Microprocessor Memory Management instruction data memory management units 603R provide Gbytes logical address space accessible supervisor user programs with Kbyte page size 256M byte segment size. Block sizes range from Kbytes Mbytes software selectable. addition, 603R uses interim 52-bit virtual address hashed page tables generating 32-bit physical addresses. MMUs 603R rely exception processing mechanism implementation paged virtual memory environment enforcing protection designated memory areas. Instruction data TLBs provide address translation parallel with on-chip cache access, incurring additional time penalty event hit. cache most recently used page table entries. software responsible maintaining consistency with memory.
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603R's TLBs 64-entry, 2-way set-associative caches that contain instruction data address translations. 603R provides hardware assistance software table search operations through ashed page table misses. supervisor software invalidate entries selectively. 603R also provides independent four-entry arrays instructions data that maintain address translations blocks memory. These entries define blocks that vary from Kbytes Mbytes. arrays maintained system software. specified PowerPC architecture, hashed page table variable-sized data structure that defines mapping between virtual page numbers physical page numbers. page table size power starting address multiple size. Also specified PowerPC architecture, page table contains number Page Table Entry Groups (PTEGs). PTEG contains eight Page Table Entries (PTEs) eight bytes each; therefore, each PTEG bytes long. PTEG addresses entry points table search operations. 12.4.3 Instruction Timing 603R pipelined superscalar processor. pipelined processor which processing instruction reduced into discrete stages. Because processing instruction broken into series stages, instruction does require entire resources execution unit. example, after instruction completes decode stage, pass next stage, while subsequent instruction advance into decode stage. This improves throughput instruction flow. example, take three cycles floating-point instruction complete, there stalls floating-point pipeline, series floating-point instructions have throughput instruction cycle. instruction pipeline 603R four major pipeline stages, described follows: fetch pipeline stage primarily involves retrieving instructions from memory system determining location next instruction retrieval. Additionally, decodes branches during fetch stage folds branch instructions before dispatch stage possible. dispatch pipeline stage responsible decoding instructions supplied instruction retrieval stage, determining which instructions eligible dispatched current cycle. addition, source operands instructions read from appropriate register file dispatched with instruction execute pipeline stage. dispatch pipeline stage, dispatched instructions their operands latched appropriate execution unit. During execute pipeline stage each execution unit that executable instruction executes selected instruction (perhaps over multiple cycles), writes instruction's result into appropriate rename register, notifies completion stage when instruction finished execution. case internal exception, execution unit reports exception completion/writeback pipeline stage discontinues instruction execution until exception handled. exception signaled until that instruction next completed. Execution most floating-point instructions pipelined within allowing three instructions executing concurrently. pipeline stages floating-point unit multiply, add, round-convert. Execution most load/store instructions also pipelined. load/store unit pipeline stages. first stage effective address calculation translation second stage accessing data cache.
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complete/writeback pipeline stage maintains correct architectural machine state transfers contents rename registers GPRs FPRs instructions retired. completion logic detects instruction causing exception, following instructions cancelled, their execution results rename registers discarded, instructions fetched from correct instruction stream. superscalar processor that issues multiple independent instructions into multiple pipelines allowing instructions execute parallel. 603R five independent execution units, each integer instructions, floating-point instructions, branch instructions, load/store instructions, system register instructions. each have dedicated register files maintaining operands (GPRs FPRs, respectively), enabling integer calculations floating-point calculations occur simultaneously without interference. Because PowerPC architecture applied such wide variety implementations, instruction timing among various PowerPC processors varies accordingly.
Preparation Delivery
13.1 Packaging
Microcircuits prepared delivery accordance with MIL-PRF-38535.
13.2
Certificate Compliance
Atmel offers certificate compliance with each shipment parts, affirming products compliance with MIL-STD-883 standard guaranteeing parameters that tested temperature extremes entire temperature range.
13.3
Handling
devices must handled with certain precautions avoid damage caused accumulation static charge. Input protection devices have been designed chip minimize effect this static buildup. However, following handling practices recommended: devices should handled benches with conductive grounded surfaces. Ground test equipment tools should used. devices should handled leads. devices should stored conductive foam carriers. plastic, rubber, silk areas should avoided. Relative humidity above percent should maintained practical.
13.4
Choice Clock Relationships
603R microprocessors provide customers with numerous clocking options. internal phase-lock loop synchronizes processor (CPU) clock system clock (SYSCLK) various ratios. Inside each PowerPC microprocessor phase-lock loop circuit. Voltage Controlled Oscillator (VCO) precisely controlled frequency phase frequency/phase detector which compares input frequency (SYSCLK frequency) submultiple VCO. ratio SYSCLK frequencies often referred mode (for example, mode).
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Table 13-1, horizontal scale represents frequency (SYSCLK) vertical scale represents PLL-CFG[0-3] signals. given SYSCLK (bus) frequency, configuration signals internal frequency operation. Table 13-1. Frequencies Common Frequencies Multipliers
Frequency (VCO Frequency MHz) specific CBGA 255, HiTCE CBGA CI-CGA Bus-toCore Multiplier 2.5x 3.5x 4.5x 5.5x Core-to Multiplier (300) 33.33 (300) (333) (366) (400) (320) (360) (400) (440) (480) bypass Clock (300) (350) (400) (450) (500) (550) (600) (300) (360) (420) (480) (540) (600) 66.67 (333) (400) (466) (533) (600) (300) (375) (450) (525) (600)
PLL_CFG[0-3] 0100 0101 0110 1000 1110 1010 0111 1011 1001 1101 0011 1111
Frequency (VCO Frequency MHz) specific CERQUAD PLL_CFG[0-3] 0100 0101 0110 1000 1110 Bus-to-Core Multiplier 2.5x 3.5x Core-to Multiplier 33.33 (300) (350) (300) (360) 66.67 (333) (400)
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Frequency (VCO Frequency MHz) specific CERQUAD PLL_CFG[0-3] 1010 0111 1011 1001 1101 0011 1111 Notes: Bus-to-Core Multiplier 4.5x 5.5x Core-to Multiplier (300) 33.33 (300) (333) (366) (400) bypass Clock (320) (360) (400) (400) 66.67
Some configurations select bus, frequencies which supported. PLL-bypass mode, SYSCLK input signal clocks internal processor directly, disabled, mode mode operation. This mode intended factory only. timing specifications given this document apply PLL-bypass mode. clock-off mode, clocking occurs inside 603e regardless SYSCLK input.
System Design Information
14.1 Power Supply Filtering
AVDD power signal implemented 603e provide power clock generation phase-locked loop. ensure stability internal clock, power supplied AVDD input signal should filtered using circuit similar shown Figure 14-1. circuit should placed close possible AVDD ensure filters much noise possible. capacitor should closest AVDD pin, followed capacitor, finally resistor VDD. These traces should kept short direct. Figure 14-1. Power Supply Filter Circuit
AVDD
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14.2
Decoupling Recommendations
603e's dynamic power management feature, large address data buses, high operating frequencies, 603e generate transient power surges high frequency noise power supply, especially while driving large capacitive loads. This noise must prevented from reaching other components 603e system, 603e itself requires clean, tightly regulated source power. Therefore, recommended that system designer place least decoupling capacitor each OVDD 603e. also recommended that these decoupling capacitors receive their power from separate VDD, OVDD, power planes PCB, utilizing short traces minimize inductance. These capacitors should vary value from provide both high frequency filtering, should placed close possible their associated OVDD pin. suggested values pins (ceramic), 0.01 (ceramic) (ceramic). suggested values OVDD pins 0.01 (ceramic), (ceramic), (tantalum). Only (Surface Mount Technology) capacitors should used minimize lead inductance. addition, recommended that there several bulk storage capacitors distributed around PCB, feeding OVDD planes, enable quick recharging smaller chip capacitors. These bulk capacitors should also have (equivalent series resistance) rating ensure quick response time necessary. They should also connected power ground planes through vias minimize inductance. suggested bulk capacitors (AVX tantalum) (AVX tantalum).
14.3
Connection Recommendations
ensure reliable operation, highly recommended connect unused inputs appropriate signal level. Unused active inputs should tied VDD. Unused active high inputs should connected GND. (non-connected) signals must remain unconnected. Power ground connections must made external VDD, OVDD, pins 603e.
14.4
Pull-up Resistor Requirements
603e requires high-resistive (weak: pull-up resistors several control signals interface maintain control signals negated state after they have been actively negated released 603e other master. These signals are: ABB, DBB, ARTRY. addition, 603e three open-drain style outputs that require pull-up resistors (weak stronger: they used system. These signals are: APE, DPE, CKSTP_OUT. During inactive periods bus, address transfer attributes driven master float high-impedance state relatively long periods time. Since 603e must continually monitor these signals snooping, this floating condition cause excessive power drawn input revivers 603e. recommended that these signals pulled through weak pull-up resistors restored some manner system. snooped address transfer attribute inputs are: A[0-3], AP[0-3], TT[0-4], TBST, GBL. data input receivers normally turned when read operation progress require pull-up resistors data bus.
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Package Mechanical Data
following sections provide package parameters mechanical dimensions CBGA, HiTCE CBGA Cerquad packages.
15.1
HiTCE CBGA Package Parameters
package parameters provided following list. package type 255lead HiTCE Ceramic Ball Array (HiTCE CBGA).
Package outline Interconnects Pitch Maximum module height
1.27
3.08
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15.1.1
Mechanical Dimensions HiTCE CBGA Package Figure 15-1 provides mechanical dimensions bottom surface nomenclature HiTCE CBGA package.
Figure 15-1. Mechanical Dimensions HiTCE CBGA Package
Ball Index
603r
0.35
MILLIMETERS
INCHES
2.42 0.80 0.90 0.80 0.82
3.08 1.00 1.14 0.90 0.93
0.095 0.031 0.035 0.031 0.032
0.12 0.039 0.045 0.035 0.037
21.00 BASIC 19.05 BASIC 10.8 8.75 BASIC 5.65 21.00 BASIC 19.05 BASIC 12.0 6.15 BASIC 1.27 BASIC
0.827 BASIC 0.75 BASIC 0.425 0.344 BASIC 0.222 0.827 BASIC 0.75 BASIC 0.472 0.242 BASIC 0.303 0.05 BASIC
255X
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15.2 CBGA Package Parameters
package parameters provided following list. package type 255-lead Ceramic Ball Grid Array (CBGA).
Package outline Interconnects Pitch Maximum module height
1.27
15.2.1
Mechanical Dimensions CBGA Package Figure 15-2 provides mechanical dimensions bottom surface nomenclature CBGA package.
Figure 15-2. Mechanical Dimensions Bottom Surface Nomenclature CBGA Package
0.200
CORNER
-E-T0.150
0.200
Notes: Dimensioning tolerancing ASME Y14.5M 1994 controlling dimension: millimeter
MILLIMETERS INCHES
21.000 21.000 2.450 0.820 3.000 0.930
0.827 0.827 0.097 0.032 0.118 0.036
1.270 0.790 0.990
0.050 0.031 0.039
0.635 5.000 5.000 16.000 16.000
0.025 0.197 0.197 0.630 0.630
255X
0.300 0.150
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15.3
CI-CGA Package Parameters
package parameters provided following list. package type 255-lead ceramic ball grid array (CI-CGA). Package outline Interconnects Pitch Typical module height 1.27 3.84
15.3.1
Mechanical Dimensions CI-CGA Package Figure 15-3 provides mechanical dimensions bottom surface nomenclature CICGA package.
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Figure 15-3. Mechanical Dimensions Bottom Surface Nomenclature CI-CGA Package
CORNER 0.200
Notes: Dimensioning tolerancing ASME Y14.5M-1994 Controlling dimension: millimeter
Millimeters
-T0.150
21.000 21.000 3.84 0.790 1.545 5.000 7.000 3.02 0.10 0.25 0.35 0.990 1.695 1.270 0.635
0.200
255X
0.300 0.150
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15.4
CERQUAD Package
Figure 15-4. Mechanical Dimensions Wire-bond CERQUAD Package
Wire Bonds Ceramic Body Alloy Leads View
VIEW Places
0.08 Section Places
Notes: Dimensioning tolerancing ASMEY14.5M-1994 Controlling dimension: millimeter Datum plane located bottom lead coincident with lead where lead exists ceramic body bottom parting line Datum determined datum plane Dimension determined seating plane Dimension define maximum ceramic body dimensions including glass protrusion bottom mismatch
tips 0.16
0.20
View
Datum Plane
0.10 Seating Plane
Datum
Plane
View
MILLIMETERS 30.86 31.00 30.86 31.00 3.67 3.95 0.185 0.220 3.10 3.50 0.175 0.200 0.50 2.025 2.100 0.130 0.147 0.45 0.50 0.25 34.41 34.58 17.20 17.30 34.41 34.58 0.45 0.70 17.20 17.30 0.122 0.127 1.80 0.95
31.75 31.75 4.15 0.270 3.90 0.225 2.175 0.175 0.55 34.75 17.40 34.75 0.95 17.40 0.132
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Ordering Information
16.1 Ordering Information CBGA, CI-CGA HiTCE Packages
PC603R
Revision level Prefix Prototype Type Temperature range -55, +125°C -40, +110°C Package CBGA CI-CGA HiTCE CBGA Maximum internal processor speed divider confirmed)
Screening level: Standard B/Q: MIL-PRF-38535, class Upscreening
16.2
Ordering Information CERQUAD Package
PC603R Revision level
Prefix Prototype Type Maximum internal processor speed divider confirmed)
Temperature range: -55, +125°C -40, +110°C +70°C Package: CERQUAD
Screening level: Standard MIL-PRF-38535, class
Note:
availability different versions, contact your Atmel sales office.
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Definitions
Datasheet Status Objective specification Target specification This datasheet contains target goal specifications discussion with customer application validation This datasheet contains target goal specifications product development This datasheet contains preliminary data. Additional data published later date could include simulation results This datasheet also contains characterization results This datasheet contains final product specifications Validity Before design phase Valid during design phase Valid before characterization phase Valid before industrialization phase Valid production purpose
Preliminary specification site Preliminary specification site Product specification Limiting Values
Limiting values given accordance with Absolute Maximum Rating System (IEC 134). Stresses above more limiting values cause permanent damage device. These stress ratings only operation device these other conditions above those given Characteristics sections specification implied. Exposure limiting values extended periods affect device reliability. Application Information Where application information given, advisory does form part specification
17.1
Life Support Applications
These products designed life support appliances, devices, systems where malfunction these products reasonably expected result personal injury. Atmel customers using selling these products such applications their risk agree fully indemnify Atmel damages resulting from such improper sale.
Document Revision History
Table 18-1 provides revision history this hardware specification. Table 18-1.
Revision Number
Document Revision History
Date 07/2005 10/2004 Substantive Change(s) Added HiTCE package PowerPC 603R This document merge TSPC603R CBGA255/CI-CGA package (ref 2125B) TSPC603R Cerquad package (ref 2127A)
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Table Contents
Features Features Specific CBGA 255, CBGA HiTCE CI-CGA Features Specific Cerquad Description Screening/Quality/Packaging Block Diagram Overview Signal Description Detailed Specifications Applicable Documents
Design Construction Absolute Maximum Ratings
Thermal Characteristics
CBGA CI-CGA Packages HiTCE CBGA Package CERQUAD Package
Power Consideration
Dynamic Power Management Programmable Power Modes Power Management Modes Power Management Software Considerations Power Dissipation Marking
Assignments
10.1 CBGA CI-CGA Packages 10.2 CERQUAD Package
Electrical Characteristics
11.1 General Requirements 11.2 Static Characteristics 11.3 Dynamic Characteristics
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11.4 JTAG Timing Specifications
Functional Description
12.1 PowerPC Registers Programming Model 12.2 Instruction Addressing Modes 12.3 Cache Implementation 12.4 Memory Management
Preparation Delivery
13.1 Packaging 13.2 Certificate Compliance 13.3 Handling 13.4 Choice Clock Relationships
System Design Information
14.1 Power Supply Filtering 14.2 Decoupling Recommendations 14.3 Connection Recommendations 14.4 Pull-up Resistor Requirements
Package Mechanical Data
15.1 CBGA HiTCE Package Parameters 15.2 CBGA Package Parameters 15.3 CI-CGA Package Parameters 15.4 CERQUAD Package
Ordering Information
16.1 Ordering Information CBGA, CI-CGA HiTCE Packages 16.2 Ordering Information CERQUAD Package
Definitions
17.1 Life Support Applications
Document Revision History
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Features Specific CBGA 255, HiTCE CBGA CI-CGA SPECint95, SPECfp95

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