documentation package TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 c

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TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
documentation package TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 chip consists following documents: UltramapperFamily Register Description Ultramapper Family System Design Guide. These documents available password protected website. Ultraframer Product Description (this document) Ultraframer Hardware Design Guide. These documents available public website shown below. contact Agere, please last page this document. access related documents, including documents mentioned above, please following public website, contact your Agere representative:
THSC Framer CHI/PSB
Rx/Tx Clocks Sync
x84/x63 DS1/J1/E1
System Interfaces
E2AISCLK/ DS2AISCLK
(x3) M13/E13 MRXC DS1/J1/E1 DS2/E2 DS3/E3
(x3) DS3/E3 (x3) NSMI
(framer)
Shared Speed
Miscellaneous
TPG/TPM
Switching modes:
8PSB (x16)- x84/X63 DS1/J1/E1 x2016 DS0/E0 4CHI (x18) x2016 DS0/E0
x84/x63 DS1/E1
JTAG
Transport modes:
4DS1/J1/E1 (x86) -x84/x63 prot. 4DS2/E2 (X86) x63/x36 prot.
JTAG
DS1XCLK, E1XCLK
Power pins shown
10/10/02
Figure 1-1. Ultraframer Block Diagram High-Level Interface Definition
TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
Introduction Features Test Pattern Generator/Monitor (TPG/TPM) (x1) M13/E13 (x3) 2.2.1 2.2.2 DS1/J1/E1 Framing (FRM) (3x28/21) DS3/E3/DS2/E2/DS1/E1 Multirate Cross Connect (MRXC) (x1) DS1/E1 Digital Jitter Attenuation (DJA) (3x28/21) Microprocessor Unit (MPU) (x1) JTAG Overview Application Diagrams DS3/E3 to/from DS1/E1 Application DS3/E3 to/from DS0/E0 Application DS1/E1 to/from DS0/E0 Application Block Description M13/E13 Multiplexer (M13/E13 MUX) 5.1.1 5.1.1.1 Receive Direction 5.1.1.2 Transmit Direction 5.1.2 Multirate Cross Connect (MRXC) Digital Jitter Attenuator (DS1/E1 DJA) Test Pattern Generator/Monitor (TPG/TPM) Clock Generator (CG) Framer (FRM) 5.6.1 Line Decoder/Encoder 5.6.2 Receive Frame Aligner/Transmit Frame Formatter 5.6.3 Receive Performance Monitor 5.6.4 Signaling Processor 5.6.5 Facility Data Link (FDL) Processor 5.6.6 HDLC Unit Glossary
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TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
M13/E13 (x3)
2.2.1 Configurable multiplexer/demultiplexer signals, signals, seven signals to/from signal. Operates either C-bit parity mode. Provisionable time-slot selection DS1, insertion drop. Full alarm monitoring generation (LOS, BPV, EXZ, OOF, SEF, AIS, RAI, FEAC, P-bit C-bit parity errors, FEBE). forced loopback DS2, DS1, forced loopback loopback request generation. Complies with T1.102, T1.107, T1.231, T1.403, T1.404, 499, G.747, G.775. 2.2.2
Features
Versatile supports solutions DS3/E3, DS2/E2, DS1/J1/E1, DS0/J0/E0 applications. Terminates DS1/J1 framed unframed signals. popular framing formats supported. Terminates three DS3/E3, DS2, signals. I/O, CORE, power (<2.5 temperature range allows uncontrolled convection cooled environments. Loopbacks, manual error insertion, internal pattern generator/monitor, internal cross connects simplify debugging diagnostics. Standard 909-pin ball grid array (PBGA) with square with square ball pitch. Complies with appropriate Telcordia ITU, ANSI ETSI, Japanese standards noted.
Test Pattern Generator/Monitor (TPG/TPM) (x1)
Configurable test pattern generator: DS1, formats. Provisionable test pattern data from following options: quasirandom signal source (QRSS), pseudorandom stream length (PRBS15), PRBS20, PRBS23, alternating (ALT_01), ALL_ONES, user pattern bits, repeating). test patterns transmitted either unframed payload framed signal defined ITU-T. Under register control, single framing (DS1/E1 only) errors injected into test pattern. sink receiving channel replaced test pattern monitor, which detect count errors misconfigurations, and/or detect idle conditions AIS. Datalink (DS1-ESF multiframe fields read/writable. Supports Ultraframer modes operation. Complies with T1.107, T1.231, T1.403, G.703, G.704, O.150.
Configurable multiplexer/demultiplexer signals four signals, to/from signal. Independently configurable four multiplexer/demultiplexers signals to/from four signals. Provisionable time-slot selection insertion drop multirate cross connect functional block. multiplexers capable generating alarm indication signal (AIS) remote alarm indicator (RAI) signals. Configurable HDB3 encoder/decoder output/input. transmit path monitors that detect loss-ofclock (LOC) AIS. receive path monitor that detects LOC, AIS, RAI. receive monitor that detects loss-of-signal (LOS), LOC, bipolar violation (BPV), AIS, RAI. loopback modes. Complies with G.703, G.742, G.751, G.775.
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DS1/J1/E1 Framing (FRM) (3x28/21)
28/21 DS1/J1/E1 channels. Line coding: B8ZS, HDB3, ZCS, AMI. Note: Available only channels 84/63. framing modes: ESF, ®-96, DDS, only). framing modes: G.704 basic CRC-4 multiframe consistent with G.706. framing modes: JESF (Japan). Supports unframed transparent transmission format. signaling modes: transparent; register system access 2-state, 4-state, 16-state; 2-state, 4-state, 16-state; SLC-96 2-state, 4-state, 16-state; J-ESF handling groups maintenance signaling; 2-state, 4-state, 16-state. signaling modes: transparent; register system access entire TS16 multiframe structure G.732. Signaling debounce change state interrupt. V5.2 processing. Alarm reporting performance monitoring AT&T ANSI, ITU-T, ETSI standards. Facility data link features: HDLC transparent access either frame formats. Register/stack access SLC-96 transmit receive data. Extended superframe (ESF): automatic transmission performance report messages (PRM). Automatic transmission ANSI T1.403 performance report messages. Automatic detection transmission ANSI T1.403 bit-oriented codes. Register/stack access CEPT bits transmit receive data. HDLC features: HDLC transparent mode. Programmable logical channel assignment: time slot, ISDN channel, also inserts/extracts C-channels V5.1, V5.2 interfaces. logical channels both transmit receive direction (any framing format). Maximum channel data rate kbits/s. Minimum channel data rate kbits/s (DS1/FDL bit). 128-byte FIFO channel both transmit receive directions. loopback supported.
TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
System interfaces: Concentration highway interface: Single clock frame synchronizing signals; programmable clock data rates 8.192 16.384 MHz; programmable clock edges bit/byte offsets. Parallel system interface 19.44 data signaling: single clock frame synchronizing signals. Network serial multiplexed interface (NSMI) minimal count serial interface 51.84 optimized data applications.
DS3/E3/DS2/E2/DS1/E1 Multirate Cross Connect (MRXC) (x1)
Configurable cross point interconnect 84/63 DS1/E1 signals to/from FRM, VTMPR, M13/E13, TPG/TPM, DS1/E1 DJA, external pins. Also supports 21/12 DS2/E2 to/from external pins from/to M13/E13 functional block. Connects three DS3/E3 signals from external pins M13/E13 MUX. Provides grooming capability receive plus transmit) DS1/E1 connections between FRM, M13/E13, DS1/E1 DJA, bidirectional sets pins. This allows cross connect grooming block signal port other signal port different block output pin, same block case groomed loopback. Multicast operation (one many) supported sources destinations. DS2, DS3, signals interconnect. Multirate cross connect allows signals to/from modules from/to framer, TPG/TPM, external pins. There signals to/from from/to external pins. There three signals from/to functional block to/from external pins. Jitter attenuation also inserted in-line channel. (Note that cascading jitter attenuators allowed.) Standard network loopback straight-away facility testing supported DS1/E1 DS3/E3. DS1/E1 testpattern generator capable injecting idle standardsbased, pseudorandom sequence test patterns, (blue) alarm replace source transmitter. test-pattern monitor that detect/count errors pseudorandom test sequence, loss frame synchronization, replace sink receiver.
Agere Systems Inc.
TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
number loopbacks supported 84/63 channels DS1/E1 channels from M13/E13 framer functional blocks. One-to-one loopback supported DS1/E1 channels. One-to-one loopback supported DS3/E3 channels from M13/E13 functional blocks. Loopbacks configured sectionalize circuit identifying faults misconfiguration during service maintenance. Fast alarm channels supported framer interconnects alarm indication signal (AIS blue alarm). This feature reduces propagation delay alarms eliminating multiple integration alarm conditions. Supports framer-only, transport (framer LIU, M13, E13), switching (CHI PSB) modes operation.
Microprocessor Unit (MPU) (x1)
21-bit address/16-bit data microprocessor interface (little-endian). Synchronous MHz)/asynchronous microprocessor interface modes. Microprocessor data parity monitoring. Summary level priority interrupts from block (maskable). Global configuration network performance monitoring counters operation. Global software resets. Global enabling powerdown major functional blocks. Registers provisionable clear read/clear write.
DS1/E1 Digital Jitter Attenuation (DJA) (3x28/21)
bandwidth, damping factor, sampling rates programmable. Configurable meet jitter MTIE requirements. Supports each DS1/E1. (Note that cascaded.) There 28/21 channels block.
Compatible with most industry-standard processors.
JTAG
IEEE 1149.1 JTAG boundary scan.
Agere Systems Inc.
TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
Overview
Ultraframer provides versatile interface DS1/J1/E1, DS3/E3, DS2/E2, DS0/J0/E0 applications. Ultraframer device integrates M13/E13 multiplex/demultiplex functions primary rate framing function. Each interface consists fully integrated, full featured, primary rate framer with HDLC formatter facility data link access. also provides alarm reporting bidirectional performance monitoring. TFRA84J13 provides glueless interconnection analog line interface units time-slot interchangers.
Agere Systems Inc.
TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
Application Diagrams
This section shows several typical Ultraframer applications. Figure through Figure depict system-level diagrams.
DS3/E3 to/from DS1/E1 Application
DS1s/48 input from LIUs, MUXed DS3/E3, framed, output three DS3/E3 LIUs. Similarly, three DS3s/E3s input from LIUs, deMUXed DS1/E1 level, output DS1s/48 E1s. DS3/E3 will received/transmitted device DS3DATAIN/OUT pins. DS1s/E1s will received/transmitted device LINERX/TXDATA pins. three instances 28/21 channel M13/E13 MUXs configured identically M13/E13 mode. three instances 28/21 channel framers configured identically transport mode operation. to/from application also possible.
DS3/E3 DS3/E3
ULTRAFRAMER
DS1/E1 84/48 DS1/E1
TSWC01622
Figure 4-1. DS3s/E3s to/from DS1s/48 Configuration
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TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
DS3/E3 to/from DS0/E0 Application
Figure shows 2016 DS0/1536 input PSB. DS0s/E0s DS1/E1 framed, multiplexed three DS3/ E3s, then framed output DS3/E3 LIUs. following points describe this scenario: 2016 DS0/1536 input from switch, DS1/E1 framed, then MUXed DS3/E3. These then framed output three DS3/E3 LIUs. Similarly, three DS3/E3s input from LIUs, deMUXed DS1/E1 level, output 2016 DS0/1536 E0s. DS3s/E3s will received/transmitted device DS3DATAIN/OUT pins. DS0s/E0s will received/transmitted device CHIRX/TXDATA pins. system interface (concentrated highway interface) (parallel system bus): programmed operate 8.192 16.384 clock data rates. interface consists 16-bit wide parallel operating 19.44 Mbits/s. three instances 28/21 channel M13/E13 MUXs configured identically M13/E13 mode. three instances 28/21 channel framers configured identically switching mode operation. to/from to/from application also possible to/from 2016 E0s).
SYSTEM INTERFACE (CHI PSB)
DS3/E3 DS3/E3 ULTRAFRAMER
DS0/E0 SWITCH
TSWC01622
Figure 4-2. DS3s/E3s to/from 2016 DS0s/1536 Configuration
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DS1/E1 to/from DS0/E0 Application
TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
2016 DS0/E0s input from switch, DS1/E1 framed, output DS1/63 LIUs. Similarly, DS1s/63 input from LIUs, deMUXed, output 2016 DS0s/E0s. DS1s/E1s will received/transmitted device LINERX/TXDATA pins. DS0s/E0s will received/transmitted device CHIRX/TXDATA pins. system interface (concentrated highway interface) (parallel system bus): programmed operate 8.192 16.384 clock data rates. interface consists 16-bit wide parallel operating 19.44 Mbits/s. three instances 28/21 channel framers configured identically switching mode (DS1/E1 to/from DS0/E0) operation. DS1/E1 level performance monitoring capabilities channels direction (DS1/E1 DS0/E0) signal path.
SYSTEM INTERFACE (CHI PSB)
DS1/E1 DS1/E1 84/63 ULTRAFRAMER
DS0/E0 SWITCH (2016)
TSWC01622
Figure 4-3. DS1s/63 to/from 2016 DS0s/E0s Configuration
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TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
This loopback performed automatically, user force loopback. four three signals each into single-bit, 16-word-deep FIFOs synchronize signals frame generation clock. fill level each FIFO determines need stuffing DS1/E1 input. handle DS1/E1 signals with nominal frequency offsets ±130 five unit intervals peak jitter. DS2/DS3 transmit clock used derive clock source frame generation. multiplexer generates transmit frame, fills information bits frame with data from seven select blocks. transmit output either form unipolar clock data, unipolar clock positive negative data. data B3ZS-encoded looped back from receive input. 5.1.2 functional block that performs MUX/deMUX from/to E1s, four E2s, signal compliant with G.742 G.751. functional block highly configurable multiplexer/demultiplexer. operate E12, E13, modes. Each internal MUX/ deMUX MUX/deMUX independently configurable. inputs receive path HDB3encoded dual-rail (bipolar) signals already decoded single-rail signals with without indication input. inputs expected decoded prior functional block. transmit direction output configured HDB3-encoded dual rail (bipolar) single rail. provides status two-level priority maskable interrupt outputs microprocessor. This block also independently configurable multiplexer/demultiplexer signals to/from four signals, provisionable time-slot selection insertion drop multirate cross connect functional block. E12/E23 multiplexers capable generating alarm indicator signal (AIS) remote alarm indicator (RAI) signals. transmit path monitors detect loss-of-clock (LOC) AIS. receive path monitor detects LOC, AIS, RAI. receive monitor detects loss-of-signal (LOS), LOC, bipolar violations (BPV), AIS, RAI. loopback modes also available.
Block Description
M13/E13 Multiplexer (M13/E13 MUX)
M13/E13 block (three blocks device) highly configurable multiplexer/demultiplexer which each block configured operation. features described below. 5.1.1 operate C-bit parity mode, mixed M13/M23 mode. C-bit parity mode, provides far-end alarm control (FEAC) code generator receiver, HDLC transmitter receiver, automatic far-end block error (FEBE) generator. Each internal MUX/deMUX MUX/deMUX configured operate independent MUXes/ deMUXes. inputs groups four) input signals groups three) feed into individual MUXes, while take signals from outputs MUXes, direct inputs, loopback deMUXed DS2s. supports numerous automatic monitoring functions. provide interrupt control system, operate polled mode. complies with T1.102, T1.107, T1.231, T1.403, T1.404, GR-499, G.747, G.775. 5.1.1.1 Receive Direction receive monitored loss clock loss-ofsignal (LOS) according T1.231. B3ZS decoder accepts either unipolar clock data, unipolar clock positive negative data. also checks bipolar coding violations. transmit looped back into receive side after B3ZS decoding. demultiplexer checks valid framing finding frame alignment pattern (F-bits) then locating multiframe alignment signal (M-bits). During each frame, data stream checked presence (1010) idle (1100) pattern. Within demultiplexer, there four performance monitoring counters F-bit M-bit, P-bit, E-bit parity, FEBE errors. Each demultiplexer contains performance monitoring counters. 5.1.1.2 Transmit Direction incoming DS1/E1 clocks first checked activity loss-of-clock (LOC). data signals retimed checked activity. DS1/E1 loopback selectors allow individual DS1/E1 signals within received looped back toward DS2/DS3 input.
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Multirate Cross Connect (MRXC)
multirate cross connect (MRXC) functional block (one device) crosspoint switch DS1/J1/E1/DS2/E2 DS3/E3 signals. multirate cross connect routes signals to/from major functional blocks external pins necessary each application. MRXC multicast, route test patterns, idles, alarm conditions channel, provide system loopbacks. DS1/E1 applications, multirate cross connect interconnect individual DS1/E1 channels between framer, M13/E13 multiplexer, jitter attenuator, external I/O. external pins support application-dependent DS1/E1* interfaces (allowing dedicated protection channels additional DS1/E1 channels), interfaces, four available system interfaces. Independent signal paths remote alarm indication (RAI) alarm indication signal (AIS) channels between M13/E13 framer supported. multirate cross connect independent interfaces subblocks MUX. Full split access external device pins provides capability add, drop, rearrange signals within M13. test-pattern generator/monitor functional block (TPG/ TPM) provides test signals monitors inputs signals to/from multirate cross connect. generate test signals DS1, DS2. There only test pattern generator monitor signal rate. MRXC also provides interface external pins. external pins configured work four modes: transport mode, concentration highway interface (CHI) mode, parallel system (PSB) mode, network serial multiplexed interface (NSMI) mode. first mode used provide dedicated access device DS3/E3/ DS2/E2/DS1/E1 signals, last three modes described below. Concentration highway interface (serial time-division multiplex interface) CHI: Global frame synchronization. Global clock: 8.192 16.384 MHz. transmit receive data ports; data rates: 8.192 Mbits/s 16.384 Mbits/s. Parallel system (parallel time-division multiplex interface/transmit receive) PSB: Global frame synchronization. Global clock: 19.44 MHz. Data rate: 19.44 Mbits/s. bits data associated parity bit. bits signaling bits signaling control parity.
85th 86th only used protection channels with applications which other fixed (see MRXC section Register Description more information). Otherwise, applications practically limited I/O.
TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
Network serial multiplexed (NSMI): Framer-NSMI payload assembled/disassembled into DS1/E1s. 6-pin 8-pin serial interface. Transmit receive clock data 51.84 MHz. Provides minimal count interface data inverse multiplexing A(IMA) applications without slip buffers.
Digital Jitter Attenuator (DS1/E1 DJA)
DS1/E1 digital jitter attenuator (DS1/E1 DJA) block (three device), contains copies digital jitter attenuator total 84/63 DS1/E1 DJAs. These digital jitter attenuator functional blocks operate different modes: jitter attenuator. both modes, digital jitter attenuator provisioned always operate second-order PLL, switch first-order during pointer adjustments help meet MTIE requirements. period time first-order mode provisionable. bandwidth provisionable between damping factor these bandwidths varies between accommodate number different system constraints. DS1/E1 allows automatic pass-through from M13/E13 blocks.
Test Pattern Generator/Monitor (TPG/TPM)
test pattern generator/test pattern monitor functional block (TPG/TPM) consists configurable test pattern generators monitors local self-test, maintenance, troubleshooting operations. feeds more DS1/E1/DS2 test signals (via data, clock, (DS1/E1 only) signal paths) multirate cross connect, which redistribute broadcast these signals valid channel framer, external I/O, M13/E13 MUX. channel arriving multirate cross connect routed test monitor. test monitor automatically detect/count errors pseudorandom test sequence, loss frame (DS1/E1 only), loss synchronization situation. provide interrupt control system, operated polled mode. Simultaneous testing DS1, signals supported with channel each. Supported test patterns quasirandom signal (QRSS), pseudorandom sequence (PRBS23, PRBS20, PRBS15), alternating zeros/ones, all-ones pattern, 16-bit user-provisionable pattern.
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test patterns transmitted either unframed payload framed signal, defined ITU-T Recommendation O.150. patterns unframed only. Under register control, single bit-errors injected into test pattern. SLC-96
TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
J-ESF standard with different CRC-6 algorithm) Nonalign (193 bits-clear channel) CEPT basic frame (ITU G.706) CEPT CRC-4 multiframe with timer (ITU G.706) CEPT CRC-4 multiframe with timer (automatic CRC-4/non-CRC-4 equipment interworking) (ITU G.706 Annex Nonalign (256 bits-clear channel) 2.048 coded mark inversion (CMI) coded interface (TTC standards JJ-20.11) 5.6.3 Receive Performance Monitor receive performance monitor detects following alarms: Loss receive clock Loss-of-signal Note: Only available individual DS1/E1 channels dual-rail mode. Loss-of-frame Alarm indication signal (AIS) Remote frame alarms Remote multiframe alarms These alarms detected defined appropriate ANSI, AT&T, ITU, ETSI standards. Performance monitoring, specified AT&T, ANSI, ITU, provided through counters monitoring following: Bipolar violations Note: Only available individual DS1/E1 channels. Frame errors errors Errored events Errored seconds Bursty errored seconds Severely errored seconds In-band loopback activation deactivation codes transmitted line payload facility data link. In-band loopback activation deactivation codes payload facility data link detected.
Clock Generator (CG)
clock generator block used optionally override device configuration specified MODE[2:0]_PLL device pins. block provisioned, default mode will generate necessary block clocks, based upon logic states MODE[2:0]_PLL pins (see Ultraframer Hardware Design Guide).
Framer (FRM)
DS1/J1/E1 framer block's (three device) internal components described following sections. particular application will determine which components within framer used. 5.6.1 Line Decoder/Encoder line decoder/encoder supports either single-rail dual-rail transmission. dual-rail mode, line codes supported follows: Alternate mark inversion (AMI) binary zero code suppression (B8ZS) ITU-CEPT high-density bipolar order three (HDB3) single-rail mode, line interface unit (LIU) decodes/ encodes data. dual-rail mode, loss-of-signal monitored. case coded mark inversion (CMI) coding (Japanese standard JJ-20.11), decodes data, listing both coding rule violations (CRVs) line coding violations bipolar violations. mode, framer single-rail mode.) Note: Dual-rail mode only supported DS1/E1 channels (out 84/63). 5.6.2 Receive Frame Aligner/Transmit Frame Formatter receive frame aligner transmit frame formatter support following frame formats: superframe superframe: framing only J-D4 superframe with Japanese remote alarm Agere Systems Inc.
TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
5.6.4 Signaling Processor signaling processor supports following modes: Superframe (D4, SLC-96): 2-state, 4-state, 16-state SPE: 2-state, 4-state, 16-state Extended superframe: 2-state, 4-state, 16-state CEPT: common channel signaling (CCS) (TS-16) Transparent (pass through) signaling J-ESF handling groups Signaling features supported channel follows: Signaling debounce Signaling freeze Signaling interrupt upon change state Associated signaling mode (ASM) Signaling inhibit Signaling stomp Voice data channels programmable robbed-bit signaling modes. entire payload forced into data-only signaling channels) mode i.e., transparent mode, achieved programming control bit. Signaling access occurs through on-chip signaling registers system interface. Data associated signaling information accessed through system either CEPT-E1 modes. 5.6.5 Facility Data Link (FDL) Processor receive facility data link processor monitors bit-oriented data-link messages defined ANSI T1.403. transmit facility data link unit overrides FDL-FIFO transmission bit-oriented data-link messages defined ANSI T1.403-1995.
processor extracts stores data link bits from three different frame types follows: D-bits delineator bits from SLC-96 multi-superframe. Data link bits from frames (bit time slot 24). multiframes Sa[4:8] bits from time slot CEPT basic CRC-4 multiframes. respective bits always extracted from framealigned frames stored stack. processor controls notification stack updates through interrupt (maskable) registers. transmit functional block performs transmission D-bits into SLC-96 superframes, Sa-bits CEPT frames, D-bits frames. SLC-96 frames, delineator bits always sourced from this functional block when block enabled insertion. frames, data link bits always sourced from this functional block when this block enabled insertion. This functional block also provides capability transmit BOMs (bit-oriented messages) data link channel links. CEPT frames, bits sourced from either stack within this functional block from system interface. data link functional block only responds with valid data when selected source control bits. 5.6.6 HDLC Unit HDLC processor formats HDLC packets insertion into programmable channels. channel number bits from time slot. maximum number channels maximum channel rate kbits/s. minimum channel rate kbits/s. Each channel allocated bytes storage. HDLC processing data facility data link (PRMs, Sa-bits, otherwise) implemented assigning position logical HDLC channel.
Agere Systems Inc.
TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
FEBE HDB3 HDLC LOPOH MCDR MRXC NSMI PBGA POAC PRBS QRSS TOAC UPSR Far-end block error High-density bipolar order three High-level data link control Line interface unit Loss-of-clock Loss-of-frame Loss-of-signal Low-order path overhead Mate clock data recovery Multirate cross connect Network serial multiplexed interface frame Plastic ball grid array Path overhead access channel Pseudorandom sequence Performance report message Quasirandom signal source Remote alarm indicator Remote defect indication Remote error indication Synchronous digital hierarchy Severely errored frame Tandem connection monitoring Transport overhead access channels Unidirectional path switch ring
Glossary
BLSR B8ZS DACS FEAC Alarm indication signal Alternate mark inversion Automatic protection switch Associated signaling mode error rate Bidirectional line switching ring Bit-oriented message Bipolar violation Bipolar zero substitution Common channel signaling Clock data recovery Concentrated highway interface Coded mark inversion Cyclic redundancy check Coding rule violation Digital access cross connects Digital jitter attenuation Extended superframe Excessive zeros Frame check sequence Facility data link Far-end alarm control
Telcordia Telcordia Technologies registered trademarks Telcordia Technologies, Inc. ANSI registered trademark American National Standards Institute, Inc. registered trademark Lucent Technologies Inc. AT&T registered trademark AT&T other countries. IEEE registered trademark Institute Electrical Electronics Engineers, Inc.
additional information, contact your Agere Systems Account Manager following: INTERNET: Home: http://www.agere.com Sales: http://www.agere.com/sales E-MAIL: docmaster@agere.com AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway Allentown, 18109-9138 1-800-372-2447, 610-712-4106 CANADA: 1-800-553-2448, 610-712-4106) ASIA: CHINA: (86) 21-54614688 (Shanghai), (86) 755-25881122 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6741-9855, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 1344
Agere Systems Inc. reserves right make changes product(s) information contained herein without notice. liability assumed result their application. Agere, Agere Systems, Agere logo registered trademarks Agere Systems Inc. Ultramapper trademark Agere Systems Inc.
Copyright 2005 Agere Systems Inc. Rights Reserved
April 2005 DS03-076BBAC-4 (Replaces DS03-076BBAC-3)

documentation package TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 c

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