33Mhz Local Interface Local Applications local translator AB-2061
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AB-2061G-33
33Mhz Local Interface Local Applications local translator
AB-2061-33 33Mhz Local Interface
Semicon AB-2061-33 local translator
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AB-2061-33 33Mhz Local Interface
Features: High speed 33Mhz Ideal interfacing 32-bit 16-bit local systems Mailbox (Door Bell) Interrupt 100-pin PQFP package Power C-Mos Technology 0.6micron Byte aligned transfers Enhanced interprocessor handshaking
Introduction AB-2061 device described this document intended support subset specification. However this does preclude this device standard buses, electrical specifications same minimum feature supported. device contains number shared registers interprocessor communication mechanisms generating interrupts local buses. device supports transfer blocks which reduces load local processor also makes efficient maintaining sensible size bursts reducing number single data phase transactions minimum. order decouple relative speed differences between buses, device incorporates pair FIFOs First First memory buffers, each direction. Each FIFO hold four 32-bit words. There direct access local memory space provided this device, side cannot transfers which solely under control local processor. Communication between buses byte shared register block mailbox registers. AB-2061-33 3.3v interface which will operate maximum frequency 33MHz. local processor either depending upon power supply.
Chip Structure
Local Control Local Signals Address
Local Data LD(7:0) LD(15:0)
Local Slave Sequencer
Local Datapath
Mailbox Shared Register Register Arbiter Registers Config. Registers FIFO 32x4 FIFO FIFO 32x4 FIFO
Control
Master/ Slave Sequencers
Data Path
Control Signals Figure Functional Block Diagram
PAD(31:0) CBE(3:0)
Applications chip used many different applications where interfacing peripheral device such printer scanner required. device used connect processor systems their respective buses with high speed interface that there degradation processing time either side systems allowing fully asynchronous access from both sides system. Figure gives overview low-cost high-speed network interface applications which this chip suitable. EXAMPLE Network Interface Card Figure shows Network Interface with connector interface printer controller board.
Card
Figure
Printer Controller Board
1:33Mhz
Slot
2061-33 Local
Network Interface Card
Figure
Pin-Out AB-2061-33 following diagram shows pin-out AB-2061-33 local interface chip:
Index corner
Packaging Information
0°7°
Symbol
Control Dimensions Alternative Dimensions millimetres inches Nominal Nominal 2.80 3.40 0.110 0.134 0.25 0.85 0.010 0.033 2.55 3.05 0.100 0.120 23.65 24.15 0.931 0.951 19.80 20.20 0.780 0.795 18.85 REF. 0.742 REF. 17.65 18.15 0.695 0.715 13.80 14.20 0.543 0.559 12.35 REF. 0.486 REF. 0.73 1.03 0.029 0.041 0.65 BSC. 0.026 BSC. 0.22 0.38 0.009 0.015 0.11 0.23 0.004 0.009 features NOTE RECTANGULAR
Conforms JEDEC MO-112 CC-1 Iss.
Note: This package rectangular
Functional Description Signals Signals Name PAD(31:0) GNT/REQ CBE(3:0) PRST INTA IRDY/TRDY DEVSEL IDSEL SERR/PERR FRAME STOP PCLK Local Signals LD(16:0) LA(3:0) LINT MODE(2:0) WAIT Data Read Strobe Data direction Write Strobe Data Strobe Chip Select Address Latch Byte Enable Address Local Interrupt Local Mode Local Wait Signal Function Multiplexed Address/Data Arbitration Command/Byte Enables Reset Interrupt Initiator/Target Ready Device Select Initialisation Select Error Reporting Cycle start/running Stop Transaction Parity Clock Number Pins
Total Active Signals
Chip Resources Configuration Registers specification requires minimum configuration registers, taking some bytes. These registers accessible from configuration cycles, though writable. local processor also requires access configuration registers order them with correct values. These registers specified fully Documentation. Shared Register Block chip contains block registers bytes length. These accessible from address held configuration register, Base Address normal read/write cycles. Again local processor also access these registers. these holds offset register which contains pointers various on-chip resources. Control controller transfers data both directions between card local memory peripheral memory, although only local processor will need coordinate transfers able control registers. Using this manner makes easier transfer data bursts, hence decrease amount bandwidth taken card. This could important certain types device which work heavily loaded. size bytes long words) ideal. potential difference clock speeds bandwidths between local buses, FIFOs necessary allow this. controller allows transfer non-longword aligned blocks DMA_MASK register. Mailbox Registers There mailbox registers interprocessor communications which generate interrupts relevant processor when read from written These interrupts individually maskable.
Accessing Chip Registers Most registers device directly accessible; indirect scheme used whereby internal address register required written REGISTER_ADDRESS register data transferred from register REGISTER_DATAn port. Some registers directly accessible reasons speed. chip appears local processor 8-bit ports starting some system-defined base address. These are: Address Name Base Offset REGISTER_ADDRESS Function
Indirect address register, holds address register accessed through REGISTER_DATA0.3
RESOURCE_STATUS
Read Returns status FIFOs RESOURCE_CONTROL Write DMA/PCI control bits FIFO_DATA0 FIFO_DATA1 only) REGISTER_DATA0 REGISTER_DATA1 REGISTER_DATA2 REGISTER_DATA3 Read Data from through FIFO1 Write Data through FIFO2 Byte indirectly accessed register Byte indirectly accessed register Byte indirectly accessed register Byte indirectly accessed register
RESOURCE_CONTROL Register Name DMA1_ENABLE DMA1_PAUSE Function When channel will start. Writing will stop reset channel. Writing will cause channel pause until written when will recommence. When channel will start Writing will stop reset channel. Writing will cause channel pause until written when will recommence. Setting this will allow controller perform bursts less than four long words. Used flush last bytes from FIFO. When some registers shared register block write protected. When accesses shared register block will terminated with RETRY. after reset. When configuration cycles will terminated with RETRY. Writing will allow configuration cycles proceed normally. after reset.
DMA2_ENABLE
DMA2_PAUSE
FIFO2-FLUSH
PROTECT_REGISTERS LOCK_REGISTERS
CONFIG_ENABLE
RESOURCE_STATUS Register Name DMA1_COMPLETE Function indicates that last word block been placed into FIFO channel indicates that CHANNEL transferred last word block memory space. Local FIFO empty. Local FIFO full. Unrecoverable error during transfer channel Unrecoverable error during transfer channel Undefined. Undefined.
DMA2_COMPLETE
FIFO1_EMPTY FIFO2_FULL DMA1_ERROR DMA2_ERROR SPARE SPARE
Configuration Registers These accessed local processor through indirect method using REGISTER_ADDRESS REGISTER_DATAn. uses configuration cycles these.
Config. Addr. Local Name Indirect Addr. 0(0,1) Vendor 0(3,2) 1(0,1) 1(3,2) 2(0) 2(1) 2(2) 2(3) 3(0) 3(1) 3(2) 3(3) 4(3-0) 5(3-0) 6(3-0) 7(3-0) 8(3-0) 9(3-0) A(3-0) B(0,1) B(3,2) C(3-0) D(3-0) E(3-0) F(0) F(1) F(2) F(3) Device Command Status Revision Interface Register Class Code Base Class Code Cache Line Size Latency Timer Header Type BIST Base Address Base Address Base Address Base Address Base Address Base Address Cardbus Pointer Subsystem Subsystem Vendor Base Address Reserved Reserved Interrupt Line Interrupt Grant Latency Width Function Default
Interface Device Manufacturer code Interface Device code Command register Status register Interface Device Revision Contains index chip's offset register Class code Base Class code IMPLEMENTED Maximum burst duration IMPLEMENTED Base addr. card resources IMPLEMENTED IMPLEMENTED IMPLEMENTED IMPLEMENTED IMPLEMENTED IMPLEMENTED Vendor assigned card Card Manufacturer code IMPLEMENTED IMPLEMENTED IMPLEMENTED Interrupt line routing Interrupt IMPLEMENTED Maximum Latency
1309h 080Dh 0000h 0200h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 0000h 0000h 00000000h 00000000h 00000000h
Only upper bits Base Address writable, giving address range This cannot changed from either local bus. Local addresses given indirect address written REGISTER_ADDRESS followed byte number(s) i.e. Vendor accessed writing REGISTER_ADDRESS then reading writing REGISTER_DATA0 REGISTER_DATA1.
Shared Register Block These accessed local processor through indirect method using REGISTER_ADDRESS REGISTER_DATAn. uses memory accesses BaseAddress0 locate these registers.
Local Name Addr. Indirect Addr. 10(1,0) LPG0 10(3,2) LPG1 11(1,0) 11(3,2) 12(1,0) 12(3,2) 13(1,0) 13(3,2) 14(1,0) 14(3,2) 15(0) 15(1) 15(2) 15(3) 16(3-0) 17(3-0) LPG2 LPG3 LPG4 Reserved Reserved Width Function
(Interprocessor Communication Register)
Default Value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 30343800h 00000000h
Interprocessor Communication Register
Note: PG4, PG3, PG5, write protected when PROTECT_REGISTERS RESOURCE_CONTROL set. LPGn writable local processor writable writable either local shared registers readable either local processor bus.
Control Registers These only accessed local processor through indirect method.
Local Indirect Addr. 18(3-0) 19(1,0) 19(3,2) 1A(3-0) 1B(1,0) 1B(1,0) 24(0) 24(1) Name DMA1_SOURCE_BASE DMA1_LENGTH DMA1_DEST_BASE DMA2_DEST_BASE DMA2_LENGTH DMA2_SOURCE_BASE DMA_MASK RESOURCE_CONF Width Function Base address transfers from Local Length long words Local IMPLEMENTED Base address transfers from Local Length long words Local IMPLEMENTED Byte masks first last word transfers local FIFO endian mode (see section controller units)
Interrupt Control Registers
Local Name Address Indirect Address 1C(3-0) INTERRUPT_SET 1D(3-0) 1E(3-0) INTERRUPT_CLEAR INTERRUPT_STATUS Width Function Written assert LINT Written local assert #INTA. Written clear INTA#. Written local processor clear LINT. zero when card asserting INTA#. zero Local when card asserting Local INT.
values written INTERRUPT_SET INTERRUPT_CLEAR irrelevant. Mailbox Registers These registers located memory space PCI, addresses given offsets from base address assigned chip. Local access through indirect addressing, using REGISTER_ADDRESS REGISTER_DATA0.3 ports.
Addr. Indirect Local Addr. 20h(3-0) 21h(3-0) 22h(3-0) 23h(3-0) 2Ch(3-0) 2Dh(3-0) Name Printer Control Register (PCR) Printer Status Register (PSR) Device Control Register (DCR) Device Status Register (DSR) Printer Handshake Register (PHR) Device Handshake Register (DHR) Width Default Value 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h
Printer Control Register (20h)
Local Access Value Access RD/WR RD/WR RD/WR RD/WR RD/WR Function Enable interrupt local write Enable interrupt local read from Enable interrupt Target Abort Enable interrupt Master Abort Software Reset Generates local interrupt enabled
Printer Status Register (21h)
POR/RST
Value
Local Access Access RD/WR RD/WR
Function When When When When read, read, read, read, Local written DHR, Write clear Local read from PHR, Write clear Target Abort occurred Master Abort occurred
Device Control Register (22h)
Value Local Access RD/WR RD/WR RD/WR RD/WR RD/WR Access Function Enable Enable Enable Enable Enable local local local local local interrupt write interrupt read from interrupt Target Abort interrupt Master Abort interrupt Software Reset
Device Status Register (23h)
POR/RST
Value
Local Access RD/WR RD/WR
Access
Function When When When When When read, read, read, read, read, written PHR, Write clear read from DHR, Write clear Target Abort occurred Master Abort occurred software
Printer Handshake Register (2Ch) This mailbox used pass data from local. When write occurs interrupt local processor generated. When local processor reads register interrupt generated (the interrupt actually generated when byte read, local processor should follow usual convention reading that byte last). Each interrupt individually maskable. Device Handshake Register (2Dh) This mailbox used pass data from local PCI. When local write occurs interrupt generated (again, always write byte last). When reads interrupt local processor generated. Each interrupt individually maskable.
Assignment
Signal
LA<1> LA<0>
Designator
Local Address Local Address (5v)
MODE<2> MODE<1> MODE<0> LD<15> LD<14> LD<13> LD<12> LD<11> LD<10> LD<9> LD<8> LD<7> LD<6> LD<5> LD<4> LD<3>
Read Strobe Write Strobe Address Latch Upper Byte Enable bus) Chip Select Local Mode Local Mode Local Mode Local Data Local Data14 Local Data13 Local Data12 Local Data11 Local Data10 Local Data Local Data Local Data Local Data Local Data Local Data Local Data
Assignment
Signal
Designator
LD<2> LD<1>
Local Data Local Data (5v)
LD<0> LWAIT LINT
Local Data Wait (Local) Interrupt (Local)
PRST PCLK PAD<31> PAD<30> PAD<29>
Reset Clock Arbitration Grant Arbitration Request Address Data Address Data Address Data VssAC
PAD<28>
Address Data VssDC VddDC (3v)
PAD<27> PAD<26> PAD<25> PAD<24> CBE<3> IDSEL PAD<23>
Address Data Address Data Address Data Address Data Command/Byte Enable Initialisation Select Address Data
Assignment
Signal
PAD<22>
Designator
Address Data VssAC VssDC
PAD<21> PAD<20> PAD<19> PAD<18> PAD<17>
Address Data Address Data Address Data Address Data Address Data VddDC (3v)
PAD<16>
Address Data VddAC (3v)
CBE<2> FRAME IRDY TRDY DEVSEL STOP INTA
Command/Byte Enable Cycle Start Initiator Ready Target Ready Device Select Stop Transaction Interrupt VddAC (3v) VssAC
PERR
Parity Error VssDC VddDC (3v)
SERR
System Error Parity
Assignment
PAD<5> PAD<4> PAD<3> PAD<2> PAD<1> PAD<0> DMARREQ DMAWREQ LA<2> PAD<6> PAD<14> PAD<13> PAD<12> PAD<11> PAD<10> PAD<9> PAD<8> CBE<0> PAD<7>
Signal
CBE<1> PAD<15>
Designator
Command/Byte Enable Address Data VddDC (3v) Address Data Address Data Address Data Address Data Address Data Address Data Address Data Command/Byte Enable Address Data VssDC Address Data VssAC VddAC (3v) Address Data Address Data Address Data Address Data Address Data Address Data Read Request Write Request Local Address
minimise noise output pins advisable ensure degree isolation between (noisy) power supply (quiet) supply pins. i.e. they should connected power planes using separate vias'.
Type Read
Trdd
Type Write
Trsu Tasu Tcsh Trcr TIon TIoff Twds Twdh Trdd
Chip select setup time read/write strobe asserted Address setup time read/write strobe asserted Chip select hold time from read/write strobe deasserted Address hold from chip select deasserted Recovery time next assertion chip select Time assert WAIT from chip select Data turnon time from read strobe asserted Data turnoff time from read strobe deasserted Write data setup time Write data hold time Read data valid from WAIT deasserted
6502 Type Read
Trdd
6502 Type Write
Trsu Tasu Tcsh Trcr TIon TIoff Twds Twdh Trdd
Chip select setup time read/write strobe asserted Address setup time read/write strobe asserted Chip select hold time from read/write strobe deasserted Address hold from chip select deasserted Recovery time next assertion chip select Time assert WAIT from chip select Data turnon time from read strobe asserted Data turnoff time from read strobe deasserted Write data setup time Write data hold time Read data valid from WAIT deasserted
Multiplexed Mode
AD(3:0)
ADDR.
Tapw
Tmas Tmah
Tapw Tmas Tmah
Pulse Width Multiplexed address setup Multiplexed address hold
Local Controller Unit Local Controller Unit (LBCU) sequences operations necessary transfer data from microprocessor, both slave mode (register accesses) master mode (DMA transfers). LBCU made three units, Local Slave Sequencer Unit (LSSU), Local Data Path Unit (LDPU) Local Master Sequencer Unit (LMSU). AB-2061 LMSU present active). LSSU handles transactions when microprocessor driving local bus; these transactions exclusively register accesses. When unit requires transfer data from local memory onchip FIFOs vice versa, signals LMSU which obtains control local using BUSREQ BUSGNT lines, then sequences spitting assembly words transfer over bits. (Only local mastering capable variants). LDPU collection multiplexers required split assemble bytes/ words long words. Local Configuration Local configuration determined reset levels MODE[2:0] pins. value these pins MUST change outside period where PRST asserted.
Mode
6502 Type strobes multiplexed data
Type strobes Multiplexed data
Controller Units Controller units (DCUs) contain control logic, pointers counters schedule, sequence provide source destination addresses data passing through FIFOs. These units ensure that maximum burst length possible always used. case AB2061 this longwords bytes). transfers byte aligned within memory space, operation this feature described DMA_MASK section. AB2061 capable directly placing data into memory local bus. retrieving data from writing data FIFOs local processor some other capable device. FIFO access been specially optimised allow transfer local memory relatively simple controllers such those present many microcontroller devices. Initialising Transfers Channel always moves data from memory space FIFOs hence into local memory. Channel moves data from local memory into memory space. Channel1: DMA1_SOURCE_BASE Holds address. This first location memory space block copied local memory. DMA1_LENGTH This register holds length longwords block copied local memory. Holds address. This first location memory space block where data from local memory will placed value which specifies length transfer longwords. This value determines which bytes written first last words block, thus allowing blocks byte aligned.
Channel2: DMA2_DEST_BASE
DMA2_LENGTH
DMA_MASK
Status RESOURCE_STATUS register contains bits that allow local processor monitor progress otherwise ongoing transfers. DMA1_COMPLETE last word data been placed FIFO1 channel This DOES however indicate that data local memory yet. (See FIFO1_EMPTY) DMA2_COMPLETE Channel2 moved last word from FIFO2 into memory space. FIFO1_EMPTY FIFO1 (PCI LOCAL) empty data. there more data expected, local processor must wait until this flag reset. DMA1_COMPLETE FIFO1_EMPTY both program assume whole block been fetched. FIFO2 (LOCAL PCI) full more data should written into
FIFO2_FULL
DMA1_ERROR DMA2_ERROR
These flags indicate that attempt read write memory space failed non-recoverable reason. AB2061 regards Master Abort device responds) Target Abort events non-recoverable.
Starting, Stopping Resetting order either channel re-read BASE LENGTH registers, appropriate ENABLE MUST written '0'. start channel write BASE LENGTH values, write ENABLE bit, followed immediately '1'. Writing channel that already running will disturb operation way. stop channel operation, write appropriate ENABLE bit. Note that this will STOP RESET channel. order pause without resetting counters pointers write appropriate PAUSE bit. pause function will stop burst progress once AB2061 asserted REQuest bus. Channel will normally only initiate burst when FIFO2 full longwords). cases where this undesirable such block
less longwords left, FIFO2_FLUSH must set. This allows DMA2 initiate burst with quantity data FIFO2. forget reset this after completion block transfer dramatically reduce transfer speed efficiency AB2061. NEVER attempt reset CONFIG_ENABLE RESOURCE_CONTROL register when running. Doing causes AB2061 enter factory test mode will cause unpredictable memory space corruption. Reading Writing Data data read from written FIFO_DATA register. This either port depending data width. mode four sucessive reads will retrieve full word from FIFO1 writes will place word into FIFO2. order that bytes written retrieved from fifos determined ENDIAN RESOURCE_CONFIG register. mode FIFO_DATA must read written wide port, reads/writes required word. example, assume word FIFO1 contains value 00C0FFEEh. mode with ENDIAN=0 four reads FIFO_DATA return ENDIAN=1 four reads FIFO_DATA return
mode with ENDIAN=0 reads FIFO_DATA return FFEE, 00C0 ENDIAN=1 reads FIFO_DATA return 00C0, FFEE Writing data FIFO2 follows same ordering convention. internal 'byte/word pointers' this function reset when written associated channel's DMA_ENABLE bit. Local DMAC signals AB2061 request each channel, this allows simple twochannel DMAC local read write fifos without intervention. DMARREQ Active asserted when FIFO1 contains data DMAWREQ Active asserted when FIFO2 space data
Aligned Transfers AB2061 supports transfer word aligned blocks from local processor PCI. aligned transfers from local supported however. This feature implemented through DMA_MASK register which bits wide. lower nibble determines pattern output byte enables when writing first word block (and hence which bytes written). upper nibble same effect last word block. Example: write block shown below, DMA_MASK register should written with value 38h.
109876543210987654321 109876543210987654321 109876543210987654321 109876543210987654321 109876543210987654321 109876543210987654321 109876543210987654321 109876543210987654321 109876543210987654321 109876543210987654321 109876543210987654321
Byte
Byte written
DMA_MASK Bit:
109876543210987654321 109876543210987654321 109876543210987654321 109876543210987654321 109876543210987654321 109876543210987654321 109876543210987654321 109876543210987654321 109876543210987654321 109876543210987654321 109876543210987654321
Shading indicates bytes transferred
Notes possible write contiguous data with this feature, however this strongly discouraged result some targets signalling system error SERR. When local processor writing data FIFO, must always write FIFO_PCI_DATA4 last, regardless whether that byte will written word. Failure this will result loss entire word data. When performing transfers word less), upper lower nibbles DMA_MASK register should written same value.
Electrical Specification VDD_3 VDD_5 GNDc Input Input High Output Output High Input Load +3.3V +5.0V +3.3V 20mA (typ) 40mA (max) 0.7V 1.8V 0.6V 2.6V
Operating Temperature: Range 70°C Humidity (Non condensing) Storage Temperature: Range -10°C +80°C Humidity (Non condensing) Product used within hours after unpacking.
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