2.7V SUPPLY 14-BIT LINEAR CODEC WITH HIGH-PERFORMANCE AUDIO FRONT-END
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STw5093
2.7V SUPPLY 14-BIT LINEAR CODEC WITH HIGH-PERFORMANCE AUDIO FRONT-END
FEATURES: Complete CODEC FILTER system including: LINEAR ANALOG DIGITAL DIGITAL ANALOG CONVERTERS. COMPANDED ANALOG DIGITAL DIGITAL ANALOG CONVERTERS ALAW µ-LAW. TRANSMIT RECEIVE BAND-PASS FILTERS ACTIVE ANTIALIAS NOISE FILTER. Phone Features: MICROPHONE BIASING OUTPUT REMOTE CONTROL (REMOCON) FUNCTION THREE SWITCHABLE MICROPHONE AMPLIFIER INPUTS. GAIN PROGRAMMABLE:0 42.5 AMPLIFIER, STEPS MUTE). EARPIECE AUDIO OUTPUT. ATTENUATION PROGRAMMABLE: STEPS. EXTERNAL AUDIO OUTPUT. ATTENUATION PROGRAMMABLE: STEPS. DRIVING CAPABILITY: 140mW OVER TRANSIENT SUPRESSION SIGNAL DURING POWER DURING AMPLIFIER SWITCHING. INTERNAL PROGRAMMABLE SIDETONE CIRCUIT. ATTENUATION PROGRAMMABLE: RANGE, STEP. INTERNAL RING, TONE DTMF GENERATOR, SINEWAVE SQUAREWAVE WAVEFORMS. ATTENUATION PROGRAMMABLE: 27dB RANGE, STEP. THREE FREQUENCY RANGES: 3.9Hz 996Hz, 3.9Hz STEP 7.8Hz 1992Hz, 7.8Hz STEP 15.6Hz 3984Hz, 15.6Hz STEP PROGRAMMABLE PULSE WIDTH MODULATED BUZZER DRIVER OUTPUT. General Features: SINGLE 2.7V 3.3V SUPPLY EXTENDED TEMPERATURE RANGE OPERATION -40°C 85°C. 1.0µW STANDBY POWER (TYP. 2.7V). 13mW OPERATING POWER (TYP. 2.7V).
TSSOP30 ORDERING NUMBER: STw5093
1.8V 3.3V CMOS COMPATIBLE DIGITAL INTERFACES. PROGRAMMABLE CONTROL INTERFACE MICROWIRE COMPATIBLE.
APPLICATIONS: GSM/DCS1800/PCS1900/JDC DIGITAL CELLULAR TELEPHONES. CDMA CELLULAR TELEPHONES. DECT/CT2/PHS DIGITAL CORDLESS TELEPHONES. BATTERY OPERATED AUDIO FRONT-ENDS DSPs.
Functionality guaranteed range 40°C +85°C; Timing Electrical Specifications guaranteed range 30°C +85°C.
GENERAL DESCRIPTION STw5093 high performance power combined CODEC/FILTER device tailored implement audio front-end functions required voltage/low power consumption digital cellular terminals. STw5093 offers number programmable functions accessed through serial control channel that easily interfaces classical microcontroller. interface supports both non-delayed (normal reverse) delayed frame synchronization modes. STw5093 configurated either 14-bit linear 8-bit companded coder. Additionally CODEC/FILTER function, STw5093 includes Tone/Ring/DTMF generator, sidetone generation, buzzer driver output.STw5093 fulfills exceeds D3/D4 CCITT recommendations ETSI requirements digital handset terminals. Main applications include digital mobile phones, cellular cordless phones, battery powered equipment that requires audio codecs operating single supply voltages.
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CONNECTIONS (Top view)
REMOUT REMIN MIC3+ MIC3MBIAS VCCA MIC1+ MIC1GNDA MIC2+ MIC2VCCP VLrVLr+
D98TL399
MCLK VCCIO AUXCLK CSCCLK GNDP
BLOCK DIAGRAM
REMIN PREAMP 0/20dB MUTE MIC2+ MIC1+ MIC3+ EARA OUTPUT 22.5 1.5dB STEP
REN,RLM,ROI,RDL
REMOCON
REMOUT
MIC3MIC2MIC1-
FILTER
TRANSMIT REGISTER
-30dB, STEP
FILTER
RECEIVE REGISTER
VLr-1
TONE, RING DTMF GENER. FILTER
TONE -27dB STEP
CONTROL INTERFACE µ-WIRE
CSCCLK MCLK
12dB VLr+
EXTA OUTPUT
CLOCK GENERATOR SYNCHRONIZER
MBIAS
MICROPHONE BIAS
SIDETONE -12.5 -27.5dB STEP
INTERFACE LATCH
BUZZER DRIVER
LEVEL ADJUST (PWM)
D98TL408
GNDP
GNDA
VCCA
VCCP
VCCIO
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FUNCTION
14,15 Power supply input digital section. Description
REMOUT Remocon function digital output. REMIN MIC3+ MIC3MBIAS VCCA MIC1+ MIC1GNDA MIC2+ MIC2VCCP VLr-, VLr+ Remocon function input. high level this detected pressed key, while level detected pressed key. Third positive high impedance input transmit preamplifier microphone connection. Third negative high impedance input transmit preamplifier microphone connection. Microphone Biasing Switch. Power supply input analog section. VCCA directly connected together cost applications (see STw5093 Power Supply Notes). Positive high impedance input transmit pre-amplifier microphone connection. Negative high impedance input transmit pre-amplifier microphone connection. Analog Ground: analog signals referenced this pin. GNDA connected together cost applications (see STw5093 Power Supply Notes). Second Positive high impedance input transmit pre-amplifier microphone connection. Second negative high impedance input transmit pre-amplifier microphone connection. Power supply input drivers. VCCP VCCA must connected together. Receive analog extra amplifier complementary outputs. These outputs drive directly earpiece transductor 50nF. signal these outputs Receive Speech signal from Internal Tone generator, Sidetone signal. Power ground. drivers referenced this pin. GNDP GNDA must connected together. Receive analog earpiece amplifier output. This output drive directly earpiece transductor 50nF. signal this output Receive Speech signal from Internal Tone Generator, Sidetone signal. logic written into (CR1) appears logic logic written into (CR1) appears logic Pulse width modulated buzzer driver output. Control Clock input: This clock shifts serial control information into from when input low, depending current instruction. CCLK asynchronous with other system clocks. Chip Select input: When this low, control information written into from STw5093 pins. Control data Input: Serial Control information shifted into STw5093 this when rising edges CCLK.
GNDP
CCLK
CSCI
AUXCLK Auxiliary Clock Input. Values must kHz, 1.536 MHz, 2.048 2.56 selected means Control Register CR0. AUXCLK used shift data
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FUNCTION (continued)
VCCIO Power supply Input Digital I/O's. Control data Output: Serial control/status information shifted from STw5093 this when falling edges CCLK. Ground: digital signals referenced this pin. Transmit Data ouput: Data shifted this during assigned transmit time slots. Elsewhere output high impedance state. delayed non-delayed normal frame synchr. modes, voice data byte shifted from TRISTATE output MCLK rising edge MCLK, while non-delayed reverse frame synchr mode voice data byte shifted falling edge MCLK. Receive data input: Data shifted during assigned Received time slots delayed non-delayed normal frame synchr. modes voice data byte shifted MCLK frequency falling edges MCLK, while non-delayed reverse frame synchr. mode voice data byte shifted MCLK frequency rising edges MCLK. Frame Sync input: This signal 8kHz clock which defines start transmit receive frames. three formats used this signal: delayed normal mode, delayed mode, delayed reverse mode. Master Clock Input: This signal used switched capacitor filters encoder/decoder sequencing logic. Values must kHz, 1.536 MHz, 2.048 2.56 selected means Control Register CR0. MCLK used also shift-in data. Description
MCLK
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FUNCTIONAL DESCRIPTION DEVICE OPERATION 1.1.1 Power initialization: When power first applied, power reset circuitry initializes STw5093 puts into power down state. Gain Control Registers various programmable gain amplifiers programmable switches initialized indicated Control Register description section. CODEC functions disabled. desired selection programmable functions intialized prior power command using MICROWIRE control channel. Note: after register programming, subsequent activation internal Power Reset detected programming register; this sets logic level output. internal Power Reset occurs, automatically switches logic level 1.1.2 Power up/down control: Following power-on initialization, power power down control accomplished writing control instructions listed Table into STw5093 with power power down. Normally, recommended that programmable functions initially programmed while device powered down. Power state control then included with last programming instruction separate single byte instruction. programmable registers also modified while STw5093 powered down setting indicated. When power down control entered single byte instruction, must When power command given, de-activated circuits activated, output will remain high impedance state until second pulse after power 1.1.3 Power down state: Following period activity, power down state reentered writing power down instruction. Control Registers remain their current state changed MICROWIRE control interface. addition power down instruction, detection loss MCLK transition detected) automatically enters device "reset" power down state with output high impedance state. 1.1.4 Transmit section: Transmit analog interface designed stages enable gains 42.5 realized. Stage noise differential amplifier providing selectable gain (PG) register CR4. microphone capacitevely connected MIC1+, MIC1- inputs, while MIC2+ MIC3+ MIC3- inputs used capacitively connect second microphone third microphone respectively auxiliary audio circuit. MIC1 MIC2 transmit mute selected with bits register CR4. mute case, analog transmit signal grounded sidetone path also disabled. Following first stage programmable gain amplifier which provides from 22.5 additional gain 1.5dB step. total transmit gain should adjusted that, reference point Block Diagram description, internal dBm0 voltage 0.49 Vrms (overload level Vrms). Second stage amplifier gain programmed with bits CR5. active prefilter then precedes order band pass switched capacitor filter. converter either 14-bit linear (bit register CR0) have compressing characteristics (bit register CR0) according CCITT MU255 coding laws. precision chip voltage reference ensures accurate highly stable transmission levels. offset voltage arising gain-set amplifier, filters comparator cancelled internal autozero circuit. Each encode cycle begins immediatly beginning selected Transmit time slot. total signal delay referenced start time slot approximatively (due transmit filter) plus (due encoding delay), which totals Voice data shifted during selected time slot trans-
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rising edges MCLK delayed non-delayed normal mode falling edges MCLK non-delayed reverse mode.A separate MBIAS output used bias microphone (bit register CR10) 1.1.5 Receive section: Voice Data shifted into decoder's Receive voice data Register during selected time slot falling edges MCLK delayed non-delayed normal mode rising edges MCLK nondelayed reverse mode. decoder consists either 14-bit linear expanding with MU255 decoding characteristic. Following Decoder 3400 order band-pass switched capacitor filter with integral correction sample hold. dBmO voltage this reference point (see Block Diagram description) 0.49 Vrms. transcient suppressing circuitry ensure interference noise suppression power analog speech signal output routedeither earpiece (VFR output) extra analog output (VLr+, VLr- outputs) setting bits OE1, OE2, CR4). Total signal delay approximatively 190µs (filter plus decoding delay) plus 62.5µs (1/2 frame) which gives approximatively 252µs. Output intended directly drive earpiece. Preceding outputs programmable attenuation amplifier, which must writing bits register CR6. Attenuations range relative maximum level step programmed. input this programmable amplifier several signals which selected writing register CR4.: Receive speech signal which been decoded filtered, Internally generated tone signal, (Tone amplitude programmed with bits register CR7), Sidetone signal, amplitude which programmed with bits register capable driving output power levels 16.5mW into load impedance capacitively connected between VFr+ GND. Piezoceramic receivers 50nF also driven. Differential outputs VLr+,VLr- intended directly drive extra output. Preceding outputs programmable attenuation amplifier, which must writing bits register CR6. Attenuations range relative maximum level step programmed. input this programmable amplifier signals which selected writing register CR4: Receive speech signal which been decoded filtered, Internally generated tone signal, (Tone amplitude programmed with bits register CR7), Sidetone signal, amplitude which programmed with bits register CR5. VLr+ VLr- outputs capable driving output power level to140mW into differentially connected load impedance Piezoceramic receivers 50nF also driven. BUZZER OUTPUT: Single ended output intended drive buzzer, external BJT, with squarewave pulse width modulated (PWM) signal frequency which stored into register CR8. some applications also possible amplitude modulate this signal with squarewave signal having frequency stored register CR9. Maximum load 50pF. 1.1.6 Digital Interface (Fig. Frame Sync input determines beginning frame. have duration from single cycle MCLK squarewave. Three different relationships established between Frame Sync input first time slot frame setting bits register CR1. delayed data mode (long frame timing) first time slot begins nominally coincident with rising edge Alternative delayed data mode (short frame sync timing) which input must high least half cycle MCLK earlier frame beginning case linear code (bit register CR0) first that transmitted received.
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case companded code only (bit register CR0) time slot assignment circuit chip used with timing modes, allowing connection voice data channels. data formats available: Format time slot corresponds MCLK cycles following immediately rising edge while time slot corresponds MCLK cycles following immediately time slot Format time slot identical Format Time slot appears slots after time slot This bits space left available insertion channel data. Data format selected register CR0. Time slot selected Control Register CR1. control register enables disables voice data transfer appropriate. During assigned time slot, output shifts data from voice data register rising edges MCLK case delayed non-delayed normal modes falling edges MCLK case non-delayed reverse mode. Serial voice data shifted into input during same time slot falling edges MCLK case delayed non-delayed normal modes rising edges MCLK case nondelayed reverse mode. high impedance Tristate condition when selected time slots. Figure Digital Interface Format (significant only companded code)
FORMAT
(delayed timing)
(non delayed timing)
MCLK
FORMAT
(delayed timing)
(non delayed timing)
MCLK
D98TL394
1.1.7 Control Interface: Control information data written into read-back from STw5093 serial control port consisting control clock CCLK, serial data input output Chip Select input, CS-. control instructions require bytes listed Table with exception single byte power-up/down command. shift control data into STw5093, CCLK must pulsed high times while low. Data input shifted into serial input register rising edge each CCLK pulse. After data shifted content input shift register decoded, indicate that byte control data will follow. This second byte either defined second byte-wide pulse follow first contiguously, i.e. mandatory return high between first second control bytes. control byte, data loaded into appropriate programmable register. must return high byte.
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read-back status information from STw5093, first byte appropriate instruction strobed during first pulse, defined Table must further CCLK cycles, during which data shifted falling edges CCLK. When high, high impedance Tri-state, enabling pins several devices multiplexed together. Thus, summarise, byte READ WRITE instructions either 8-bit wide pulses single wide pulse. 1.1.8 Control channel access interface: possible access channel previously selected Register case companded code only. byte written into Control Register will automatically transmitted from output following frame place transmit data. byte written into Control Register will beautomatically sent through receive path Receive amplifiers. order implement continuous data flow from Control MICROWIRE interface channel, necessary send control byte each frame. current byte received input read register CR2. order implement continuous data flow from channel MICROWIRE interface, necessary read register each frame. 1.1.9 AUXCLK usage: Auxiliary clock AUXCLK only used keep active tone buzzer generation functions Earpiece Extra amplifier outputs when Master Clock MCLK available, there voice activity both transmit receive channels. When AUXCLK selected, digital interface inactive tristate read). selection between AUXCLK MCLK done register CR1The input frequency AUXCLK selected bits register MCLK signal. 1.1.10REMOCON function: REMOCON (Remote Control) function used detect status headset button. REMOCON function enabled setting CR10). enabled, this function active also when STw5093 Power-down state. REMIN input high level detected pressed button, while level detected pressed button. "Pressed Button" information treated ways depending CR10): (Transparent mode) information REMIN seen REMOUT after debounce time 50ms maximum. (Latched Mode) information stored CR10) seen REMOUT.When level REMIN detected after debounce time 50ms maximum.RDL reset power reset also reset writing CR10. REMOUT output polarity inverted setting CR10):the pressed button information presented REMOUT output logic polarity inverted. PROGRAMMABLE FUNCTIONS programmable functions configured writing number registers using 2-byte write cycle. Most these registers also read-back verification. Byte always register address, while byte Data. Table lists register their respective adresses.
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Table Programmable Register Intructions
Address byte Function Single byte Power up/down Write Read-back Write Read-back Write Data receive path Read data from Write Data Write Read-back Write Read-back Write Read-back Write Read-back Write Read-back Write Read-back Write CR10 Read-back CR10 Write CR11 Read-back CR11 Write Test Register CR12 Write Test Register CR13 Write Test Register CR14 none TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE CR10 TABLE CR10 CR11 TABLE CR11 reserved reserved reserved Data byte
Notes: address byte data byte always first clocked into from: pins when MICROWIRE serial port enabled. reserved: write Power up/down Control bit. Means Power Down.Bit indicates, set, presence second byte. write/read select bit. Registers CR12, CR13, CR14 accessible.
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Table Control Register Functions
Function MCLK AUXCLK MCLK AUXCLK 1.536 MCLK AUXCLK 2.048 MCLK AUXCLK 2.560 Linear code Companded code Linear Code
(1): state power initialization significant companded mode only
Companed Code MU-law: CCITT D3-D4 MU-law: Bare Coding A-law including even inversion A-law: Bare Coding
2-complement sign magnitude 2-complement 1-complement consecutive separated bits time-slot bits time-slot Normal operation Digital Loop-back
Table Control Register Functions
(1): state power initialization significant companded mode only reserved: write
Function delayed data timing non-delayed normal data timing non-delayed reverse data timing latch latch connected rec. path connected rec. path Trans path connected connected voice data transfer disable voice data transfer enable channel selected channel selected
MCLK Master Clock Frame Sync inputs selected AUXCLK Auxiliary Clock input selected
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Table Control Register Functions
Significant companded mode only.
Function Data sent Receive path Data received from input
Table Control Registers Functions
Significant companded mode only.
Function data transmitted
Table Control Register Functions
state power initialization
Function Transmit input muted MIC1 Selected MIC2 Selected MIC3 Selected Internal sidetone disabled Internal sidetone enabled Receive output muted output selected output selected ALLOWED Ring Tone disabled Ring Tone enabled Receive High Pass filter enabled Receive High Pass filter disabled Receive Signal disabled Receive Signal enabled
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Table Control Register Functions
Function Transmit amplifier
state power initialization
Sidetone amplifier gain gain step 22.5 gain -12.5 gain -13.5 gain step -27.5 gain
Table Control Register Functions
Function Extra amplifier [EXTA]
state power initialization
Earpiece ampifier [EARA]
gain gain step gain gain gain step gain
Table Control Register Functions
(2):
Attenuation
Function 1.6(2) 1.26(2)
Tone gain
0.066
0.053
muted selected selected summed mode Squarewave signal selected Sinewave signal selected Normal operation Tone Ring Generator connected toTransmit path
state power initialization value provided selected alone.if selected summed mode, f1=0.89 while f2=0.7 Vpp. reserved: write
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Table Control Register Functions
Function Binary equivalent decimal number used calculate
Table Control Register Functions
Function Binary equivalent decimal number used calculate
Table Control Register CR10 Functions
Function
Default values inserted into Register Power
Remocon Function disabled Remocon Function enabled Remocon output transparent mode Remocon output latched mode Remocon output inverted Remocon output inverted Remocon detection latch reset Remocon detection latch internal logic 20dB preamplifier gain preamplifier gain MBIAS output disabled MBIAS output enabled Standard Frequency Tone Range Halved Frequency Tone Range Doubled Frequency Tone Range Forbidden
Table Control Register CR11 Functions
state power initialization
Function Buzzer output disabled (set Buzzer output enabled
Duty Cycle intended relative width logic Duty cycle intended relative width logic
Binary equivalent decimal number used calculate duty cycle.
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CONTROL REGISTER First byte READ WRITE instruction Control Register shown TABLE Second byte shown TABLE Master Clock Auxiliary Clock Frequency Selection master clock must provided STw5093 activate functions. case MCLK absent, AUXCLK provide STw5093 activating tone buzzer functions only. MCLK AUXCLK frequency either kHz, 1.536 MHz, 2.048 2.56 MHz. must during initialization select correct internal divider.Default value kHz. clock different from default must selected prior Power-Up instruction. Coding Selection Bits permit selection Mu-255 coding with without even inversion companded code (bit selected. Bits MA(4) IA(3) permit selection 2-complement, 1-complement sign magnitude linear code (bit selected. Coding Selection permits selection either linear coding (14-bit) companded coding (8-bit). Default value linear coding. Digital Interface format FF(2) selects digital interface Format where channel consecutive. FF=1 selects Format where channel separated bits. (See digital interface format section.) 56+8 selection 'B7' selects capability STw5093 take into account only seven most significant bits data byte selected. When 'B7' set, ignored high impedance. This function allows connection external band" data generator directly connected Digital Interface. Digital loopback Digital loopback mode entered setting bit(0) equal Digital Loopback mode, data written into Receive Data Register from selected received time-slot read-back from that Register selected transmit time-slot decoding encoding takes place this mode. Transmit Receive amplifier stages muted. CONTROL REGISTER First byte READ WRITE instruction Control Register shown TABLE Second byte shown TABLE Digital Interface Timing DM1(7) selects digital interface delayed timing mode, while selects non-delayed normal data timing mode, selects non-delayed reverse data timing mode.Default delayed data timing.
Significant companded mode only
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Latch output control controls directly logical status latch output "ZERO" written puts output logical while "ONE" written sets output zero. Microwire access channel receive path selects access from MICROWIRE Register Receive path. When high, data written register decoded each frame, sent receive path data input ignored. other direction, current data input received read from register each frame. Microwire access channel transmit path selects access from MICROWIRE write only Register output. When high, data written output every frame output encoder ignored.
True even inversion without even inversion
full scale full scale
always first shifted STw5093.
Transmit/Receive enabling/disabling 'EN' enables disables voice data transfer pins. When disabled, data from decoded time-slots high impedance Default value disabled. B-channel selection TS(1) permits selection between channels. Default value channel. Clock Selection SLC(0) allows selection between MCLK AUXCLK. Default value MCLK. CONTROL REGISTER CR2(1) Data sent receive path data received from input. Refer MR(4) "Control Register CR1" paragraph. CONTROL REGISTER data transmitted. Refer MX(3) "Control Register CR1" paragraph. CONTROL REGISTER First byte READ WRITE instruction Control Register shown TABLE Second byte shown TABLE
Significant companded mode only
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Transmit Input Selection MIC1 MIC2 MIC3 transmit mute selected with bits TE). Transmit gain adjusted within 22.5 range step with Register CR5. Sidetone Selection "SI" enables disables Sidetone circuitry. When enabled, sidetone gain adjusted with Register (CR5). When Transmit path disabled, sidetone circuit also disabled. Output Driver Selection Bits OE1(4) OE2(3) provide selection among earpiece output extra amplifier output both outputs muted.OE1 allowed. Ring/Tone signal selection provide select capability connect on-chip Ring/Tone generator either extra amplifier input earpiece amplifier input. Receiver High Pass Filter Selection HPB(1) provides selection receiver high pass filter cutoff frequency. receive data selection Bits "SE" provide select capability connect received speech signal either extra amplifier input earpiece amplifier input.
CONTROL REGISTER First byte READ WRITE instuction Control Register shown TABLE Second byte shown TABLE Transmit gain selection Transmit amplifier programmed gain from 22.5dB 1.5dB step with bits dBmO level output transmit amplifier reference point) 0.492 Vrms (overload voltage 0.707 Vrms). Sidetone attenuation selection Transmit signal picked after switched capacitor pass filter back into both Receive amplifiers. Attenuation signal output sidetone attenuator programmed from -27.5dB relative reference point step with bits
CONTROL REGISTER First byte READ WRITE instruction Control Register shown TABLE Second byte shown TABLE
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Earpiece amplifier gain selection: Earpiece Receive gain programmed step from relative maximum with bits dBmO voltage output amplifier 0.9825 Vrms when gain selected down 30.925 Vrms when -30dB gain selected. Extra amplifier gain selection: Extra Receive amplifier gain programmed step from relative maximum with bits dBmO voltage output amplifier pins VLr+ VLr- 1.965 Vrms when gain selected down 61.85 mVrms when gain selected.
CONTROL REGISTER CR7: First byte READ WRITE instruction Control Register shown TABLE Second byte shown TABLE Tone/Ring amplifier gain selection Output level Ring/Tone generator, before attenuation programmable attenuator Vpk-pk when generator selected alone summed with generator 1.26 Vpk-pk when generator selected alone. Selected output level attenuated down programmable attenutator setting bits Frequency mode selection Bits 'F1' 'F2' permit selection and/or frequency generator according TABLE When selected, output Ring/Tone squarewave sinewave) signal frequency selected CR9) Register. When selected summed mode, output Ring/Tone generator signal where frequency summed. order meet DTMF specifications, output level attenuated relative output level. Frequency temporization must controlled microcontroller. Waveform selection 'SN' selects waveform output Ring/Tone generator. Sinewave squarewave signal selected. DTMF selection permits connection Ring/Tone/DTMF generator Transmit Data path instead Transmit Amplifier output. Earpiece extra receive output feed-back provided sidetone circuitry setting directly setting Register CR4. Loudspeaker feed-back provided directly setting Register CR4.
CONTROL REGISTERS First byte READ WRITE instruction Control Register shown TABLE Second byte respectively shown TABLE "standard frequency tone range" selected, Tone Ring signal frequency value defined formula: 0.128
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0.128 where decimal equivalents binary values registers respectively. Thus, frequency between 1992 selected step. "halved frequency tone range"is selected, Tone Ring signal frequency value defined formula: 0.256 0.256 This frequency between 3.9Hz 996Hz selected 3.9Hz step. "doubled frequency tone range"is selected, Tone Ring signal frequency value defined formula: 0.064 0.064 Thus frequency between 15.6Hz 3984Hz selected 15.6Hz step. TABLE gives examples main frequencies usual Tone Ring generation.
CONTROL REGISTER CR10 Remocon Function Enable REN(7) enables disables RemoconFunction. Default value disabled. Remocon Mode Selection RLM(6) used select between transparent pressed button information latched pressed button information REMOUT. both cases debounce circuit (50ms max.) active. Remocon Output Inversion ROI(5) used invert information REMOUT. Default value inverted (i.e. pressed button information logic REMOUT. Remocon Detection Latch RDL(4) internal Remocon Function logic, after debounce time, when level REMIN detected. reset writing CR10. Preamplifier Gain Selection PG(3) provides selection between 20dB gain preamplifier. Default value 20dB. Microphone Bias Disabling/Enabling enables disables switch microphone biasing. Default value disabled. Tone Frequency Range Selection DFT(1) HFT(0) permits selection among "standard frequency tone range" (i.e. from 7.8Hz 1992Hz 7.8Hz step), "halved frequency tone range" (i.e. from 3.9Hz 996Hz 3.9Hz step), "doubled frequency
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tone range" (i.e. from 15.6Hz 3984Hz 15.6Hz step) according values described CONTROL REGISTER CR9.
CONTROL REGISTER CR11 BE(7) permits connection squarewave Ring signal, amplitude modulated squarewave signal, buzzer driver output Bits define duty cycle squarewave, according following formula: Duty Cycle CR11(5 0.78125% where CR11(5 decimal equivalent binary value BZ0. When bits register CR7, ring signal present buzzer output, while bits register ring signal also amplitude modulated squarewave frequency. allows chose logic level which duty cycle referred: means that duty cycle intended relative width logic1, while means that duty cycle intended relative width logic When during power down)
Table Examples Usual Frequency Selection (Standard frequency tone range)
Description Tone Tone Tone Tone Tone Tone 1330 DTMF 697Hz DTMF DTMF DTMF DTMF 1209 DTMF 1336 DTMF 1477 DTMF 1633 flat sharp sharp value (decimal) Theoretic value (Hz) 1330 1209 1336 1477 1633 523.25 587.33 622.25 659.25 698.5 830.6 987.8 1046.5 1174.66 1318.5 Typical value (Hz) 328.2 421.9 437.5 796.9 1328.1 695.3 773.4 851.6 937.5 1210.9 1335.9 1476.6 1632.8 390.6 437.5 492.2 523.5 586.0 625.0 656.3 695.3 742.2 781.3 828.2 882.9 984.4 1046.9 1171.9 1320.4 Error% -.00 -.56 -.73 -.56 -.39 -.14 -.24 +.44 -.05 -.37 +.16 -.01 -.30 -.56 -.34 +.04 -.23 +.45 -.45 -.45 +.30 -.34 -.29 +.33 -.34 +.04 -.23 +.14
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TIMING DIAGRAM Figure Delayed Data Timing Mode (Normal)
Figure Delayed Data Timing Mode
case companded code timing applied bits instead bits.
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TIMING DIAGRAM Figure Delayed Reverse Data Timing Mode
tHMFR
tWMM
MCLK
tSFMR tHMFR
tWML
tDFD tDMDR tDMZR
tSDM
tHMDR
D93TL076A
case companded code timing applied bits instead bits.
Figure Serial Control Timing (MICROWIRE MODE)
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ABSOLUTE MAXIMUM RATINGS
Parameter Voltage (VCC 3.3V) Current Current digital output Voltage digital input (VCCIO 3.3V); limited 50mA Storage temperature range Lead Temperature (wave soldering, 10s) Value +0.5 -0.5 VCCIO -0.5 Unit
OPERATIVE SUPPLY VOLTAGES
Symbol VCCA VCCP VCCIO Min. Max. Unit
TIMING SPECIFICATIONS (unless otherwise specified, VCCIO 1.8V 3.3V ,Tamb -30°C 85°C typical characteristics specified VCCIO 3.0V, Tamb signals referenced GND, Note timing definitions) NOTICE: timing specifications changed. MASTER CLOCK TIMING
Symbol Parameter Test Condition Selection frequency programmable (see table Min. Typ. 1.536 2.048 2.560 Max. Unit
fMCLK
Frequency MCLK
tWMH tWML
Period MCLK high Period MCLK Rise Time MCLK Fall Time MCLK
Measured from Measured from Measured from Measured from
INTERFACE TIMING
Symbol tHMF tSFM tDMD Parameter Hold Time MCLK Setup Time, high MCLK Delay Time, MCLK high data valid Load 20pF Test Condition Min. Typ. Max. Unit
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TIMING SPECIFICATIONS (continued) INTERFACE TIMING (continued)
Symbol tDMZ tDFD Parameter Delay Time, MCLK disabled Delay Time, high data valid Load 20pF; Applies only rises later than MCLK rising edge Delayed Mode only Load 20pF Test Condition Min. Typ. Max. Unit
tSDM tHMD tHMFR tSFMR tDMDR tDMZR tHMDR
Setup Time, valid MCLK receive edge Hold Time, MCLK invalid Hold Time MCLK High Setup Time, high MCLK High Delay Time, MCLK data valid Delay Time, MCLK High disabled Hold Time, MCLK High invalid
SERIAL CONTROL PORT TIMING
Symbol fCCLK tWCH tWCL tHCS tSSC tSDC tHCD tDCD tDSD Parameter Frequency CCLK Period CCLK high Period CCLK Rise Time CCLK Fall Time CCLK Hold Time, CCLK high Setup Time, CCLK high Setup Time, valid CCLK high Hold Time, CCLK high invalid Delay Time, CCLK data valid Delay Time, CS-low data valid Load 20pF Measured from Measured from Measured from Measured from Test Condition Min. Typ. Max. 2.048 Unit
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TIMING SPECIFICATIONS (continued) SERIAL CONTROL PORT TIMING (continued)
Symbol tDDZ Parameter Delay Time CS-high CCLK high impedance whichever comes first Hold Time, CCLK high CShigh Time, high CCLK high Test Condition Min. Typ. Max. Unit
tHSC tSCS
Note
signal valid above below invalid between VIH. purposes this specification following conditions apply: input signal defined 0.2VCCIO, 0.8VCCIO, 10ns, 10ns. Delay times measured from inputs signal valid output signal valid. Setup times measured from data input valid clock input invalid. Hold times measured from clock signal valid data input invalid.
ELECTRICAL CHARACTERISTICS (unless otherwise specified, VCCIO 1.8V 3.3V, Tamb -30°C 85°C; typical characteristic specified VCCIO 3.0V, Tamb 25°C signals referenced GND) DIGITAL INTERFACES
Symbol Parameter Input Voltage Test Condition digital inputs except REMIN digital inputs except REMIN 0.7VCCIO 0.8VCCIO REMIN input REMIN input digital outputs, 10µA digital outputs, digital outputs, 10µA digital outputs, digital input, digital input, VCCIO VCCIO-0.1 VCCIO-0.4 Min. Typ. Max. 0.3VCCIO 0.2VCCIO Unit
Input High Voltage
VILREM VIHREM
Input Voltage Input High Voltage Output Voltage
Output High Voltage
Input Current Input High Current Output Current High impedance (Tri-state)
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Figure A.C. TESTING INPUT, OUTPUT WAVEFORM
INTPUT/OUTPUT
0.8VCCIO 0.7VCCIO TEST POINTS 0.2VCCIO 0.3VCCIO 0.3VCCIO
D93TL077A
0.7VCCIO
Testing: inputs driven 0.8VCCIO logic "1"and 0.2VCCIO logic Timing measurements made 0.7VCCIO logic "1"and 0.3VCCIO logic "0".
ANALOG INTERFACES
Symbol RMBIAS IMIC RMIC RLVFr CLVFr ROVFr0 RLvLr CLvLr ROLVrO VOSVLrO Parameter Switch Resistance Microphone bias Input Leakage Input Resistance Load Resistance Load Capacitance Output Resistance Load Resistance Load Capacitance Output Resistance Differential offset Voltage VLr+, VLrSteady zero code applied ±1mA VLr+ VLrfrom VLr+ VLrSteady zero code applied Alternating zero code applied maximum receive gain; Test Condition MBIAS 100mV under VMIC VMIC -100 Min. Typ. Max. +100 Unit
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TRANSMISSION CHARACTERISTICS (unless otherwise specified, 2.7V 3.3V, Tamb -30°C 85°C; typical characteristics specified 3.0V, Tamb 25°C, MIC1/2/3 0dBm0, -6dBm0 code, 1015.625 signal referenced GND) AMPLITUDE RESPONSE (Maximum, Nominal, Minimum Levels) Transmit path Absolute levels MIC1 MIC2 MIC3
Symbol Parameter dBm0 level Overload level dBm0 level Overload level Transmit Amps connected 42.5dB gain Test Condition Transmit Amps connected 20dB gain Min. Typ. 49.26 70.71 3.694 5.302 Max. Unit mVRMS mVRMS mVRMS mVRMS
AMPLITUDE RESPONSE (Maximum, Nominal, Minimum Levels) Receive path Absolute levels
Symbol Parameter dBM0 level dBM0 level Test Condition Receive programmed attenuation Receive programmed for30dB attenuation Min. Typ. 0.9825 30.925 Max. Unit VRMS mVRMS
AMPLITUDE RESPONSE (Maximum, Nominal, Minimum Levels) Receive path Absolute levels (Differentially measured)
Symbol Parameter dBM0 level dBM0 level Test Condition Receive programmed attenuation Receive programmed 30dB attenuation Min. Typ. 1.965 61.85 Max. Unit VRMS mVRMS
AMPLITUDE RESPONSE Transmit path
Symbol Parameter Transmit Gain Absolute Accuracy Test Condition Transmit Gain Programmed minimum.Measure deviation Digital Code from ideal 0dBm0 code Measure Transmit Gain over range from Maximum minimum setting.Calculate deviation from programmed gain relative GXA, i.e. GAXG actual prog. Measured relative GXA. min. gain Max. gain Measured relative Minimum gain Min. -0.5 Typ. Max. Unit
GXAG
Transmit Gain Variation with programmed gain
-0.5
GXAT GXAV
Transmit Gain Variation with temperature Transmit Gain Variation with supply
-0.1
-0.1
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AMPLITUDE RESPONSE(continued) Transmit path (continued)
Symbol GXAF Parameter Transmit Gain Variation with frequency Test Condition Relative 1015,625 multitone test technique used.min. gain Max. gain 3000 3400 4000 4600 8000 Sinusoidal Test method.Reference Level dBm0 VMIC dBm0 dBm0 VMIC dBm0 dBm0 VMIC dBm0 dBm0 Min. Typ. Max. Unit
-1.5 -0.5 -1.5
GXAL
Transmit Gain Variation with signal level
-0.5 -0.5 -1.2
limit frequencies between 4600Hz 8000Hz lies straight line connecting frequencies linear (dB) scale versus (Hz) scale.
Receive path
Symbol GRAE Parameter Receive Gain Absolute Accuracy Test Condition Receive gain programmed maximum Apply dBm0 code Measure Receive gain programmed maximum Apply dBm0 code Measure VLr± Measure Gain over range from Maximum minimum setting. Calculate deviation from programmed gain relative GRAE, i.e. GRAGE actual prog. GRAE Measure Gain over range from Maximum minimum setting.Calculate deviation from programmed gain relative GRAL, i.e. GRAGL actual prog. GRAL Measured relative GRA. (VLr VFr) min. gain Max. gain Min. -0.5 Typ. Max. Unit
GRAL
Receive Gain Absolute Accuracy
-0.5
GRAGE
Receive Gain Variation with programmed gain
-0.5
GRAGL
Receive Gain Variation with programmed gain
-0.5
GRAT
Receive Gain Variation with temperature
-0.1
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AMPLITUDE RESPONSE(continued) Receive path (continued)
Symbol GRAV Parameter Receive Gain Variation with Supply Test Condition Measured relative GRA. (VLr VFr) Maximum Gain Relative 1015,625 multitone test technique used. min. gain Max. gain 60Hz 100Hz 3000 3400 4000 Relative 1015,625 multitone test technique used. Min. gain Max. gain 50Hz 3000 3400 4000 Sinusoidal Test Method Reference Level dBm0 dBm0 dBm0 dBm0 dBm0 dBm0 dBm0 Sinusoidal Test Method Reference Level dBm0 dBm0 dBm0 dBm0 dBm0 dBm0 dBm0 Min. -0.1 Typ. Max. Unit
GRAF
Receive Gain Variation with frequency (VLr VFr)
-1.5 -0.5 -1.5
Receive Gain Variation with frequency (VLr VFr)
-1.5 -0.5 -1.5
GRAL
Receive Gain Variation with signal level (VFr)
-0.5 -0.5 -1.2
GRAL
Receive Gain Variation with signal level (VLr)
-0.5 -0.5 -1.2
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ENVELOPE DELAY DISTORTION WITH FREQUENCY
Symbol Parameter Delay, Absolute Delay, Relative Test Condition 1600 1000 1000 1600 1600 2600 2600 2800 2800 3000 1600 1000 1000 1600 1600 2600 2600 2800 2800 3000 Min. Typ. Max. Unit
Delay, Absolute Delay, Relative
NOISE
Symbol Parameter Noise, weighted 35dB) Noise, linear weighted (max. gain) Noise, Single Frequency Test Condition VMIC Receive code Positive Zero Loop-around measurament from mVrms; 100Hz 50KHz Code equals Positive Zero, 3.0VDC mVrms, input dBm0 code 3400 Input Code applied 4600 5600 5600 7600 7600 8400 Min. Typ. Max. Unit dBm0p µVrms dBm0
PPSRx
PSRR,
PPSRp
PSRR,
Spurious Out-Band signal output
3400Hz bandwidth
CROSSTALK
Symbol CTx-r Parameter Transmit Receive Test Condition Transmit Level dBm0, 3400 Quiet Code Receive Level dBm0, 3400 Min. Typ. -100 Max. Unit
CTr-x
Receive Transmit
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DISTORTION
Symbol STDX(*) Parameter Signal Total Distortion 35dB gain) Test Condition Sinusoidal Test Method (measured using linear 3400 weighting) Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 dBm0 input signal Sinusoidal Test Method (measured using linear 3400 weighting) Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 dBm0 input signal Sinusoidal Test Method (measured using linear 3400 weighting) Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 dBm0 input signal Loop-around measurement Voltage dBm0 dBm0, Frequencies range 3400 Min. Typ. Max. Unit
Typical values measured with 30.5dB gain
37.5 28.5
SDFx
Single Frequency Distortion transmit
STDRE(*) Signal Total Distortion (VFr) 20dB attenuation)
Typical values measured with 20dB attenuation.
SDFr
Single Frequency Distortion receive (VFr)
STDRL(*) Signal Total Distortion (VLr) 20dB attenuation) Typical values measured with 20dB attenuation
SDLr
Single Frequency Distortion receive (VLr) Intermodulation
limit curve shall determined straight lines joining successive coordinates given table. Lower limits used during automatic testing avoid unrealistic yield loss imprecision time-limited noise measurements.
POWER DISSIPATION
Symbol ICC0 Parameter Power down Current Test Condition CCLK,CI 0.1V; VCCIO-0.1V REMOCON function disabled (REN CCLK,CI 0.1V; VCCIO-0.1V REMOCON function enabled (REN REMIN VILREM REMIN VIHREM VLr+, VLr- loaded Min. Typ. Max. Unit
ICC0R
Power down Current
ICC1
Power Current
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AUDIO CODEC APPLICATIONS Figure Application Note Microphone Connections.
SINGLE ENDED MODE MBIAS
DIFFERENTIAL MODE MBIAS
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MICP 22µF 0.47µF
22µF
STw5093
MICP 0.47µF
MICN
MICN 0.47µF
D98TL395
0.47µF
D98TL396
Figure Application Note Connections.
CERAMIC RECEIVERS (50nF) VLr+ VLr+
D98TL397A
must greater then highes capacitor transducers, lower values used
DYNAMIC RECEIVERS
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VLr-
STw5093
VLrD98TL398
Figure Application Note Connections.
CERAMIC RECEIVERS (50nF)
DYNAMIC RECEIVERS (30) C=100µF
STw5093
STw5093
D98TL409A
must greater then highes capacitor transducers, lower values used
D98TL410
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POWER SUPPLY NOTES different strategies used minimize power supply noise/interference. Recommended strategy: keep analog digital power supply rails separate. This requires sets capacitors, from AVCC AGND other from DVCC DGND. Figure
AVCC VCCP 10µF 100nF AGND AGND VCCA
DVCC
100nF
STw5093
DGND GNDP GNDA DGND
D98TL412
AGND
cost strategy: analog digital power supplies together close possible pins. This allows only capacitors between GND. Figure
VCCP VCCA
100nF 10µF
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GNDP GNDA
D98TL413
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DIM. MIN. 4.30 0.50 0.05 0.85 0.17 0.09 7.70 7.80 6.40 0.50 4.40 0.60 4.50 0.70 0.169 0.020 0.90 TYP. MAX. 1.10 0.15 0.95 0.27 0.20 7.90 0.002 0.033 0.007 0.004 0.303 MIN.
inch TYP. MAX. 0.043 0.006 0.035 0.037 0.011 0.008 0.307 0.252 0.0197 0.173 0.024 0.177 0.028 0.311
OUTLINE MECHANICAL DATA
TSSOP30 (Thin Shrink)
(min.) (max.)
0.010 0.004 inch SEATING PLANE
Gage Plane 0.25mm identification SEATING PLANE
TSSO30M
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Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. logo registered trademark STMicroelectronics. other names property their respective owners 2004 STMicroelectronics rights reserved STMicroelectronics GROUP COMPANIES Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States www.st.com
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