Single-Chip Worldwide iDTV Processor DATABRIEF SD/HD Digital

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Single-Chip Worldwide iDTV Processor DATABRIEF SD/HD Digital

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STD2000
Single-Chip Worldwide iDTV Processor
DATABRIEF
SD/HD Digital Video SD/ID Analog Video Dual DDEC Comb
Video Display Pipeline (TNR, DEI, Scaling, IQI) Compositor Display Driver Display
Video Display Pipeline (TNR, DEI, Scaling, IQI) Graphics
Peripherals On-Chip Interconnect Digital Encoder
Recorder
Dual Transport Demux
Video Decoder MPEG-2 MP@HL MP@MLx2
Audio MPEG Dolby Digital Decoder
ST40 MIPS 32K-D
Gamma Graphics
Digital Audio MPEG-2 Audio Video Dual C.I. CableCard
Chassis Control
TimeBase Clock Generator
Digital Audio SDRAM Flash
Dual-Channel High Definition Video Processor
Dual DVB-CI/one CableCARDinterface MP@ML Dual Channel MP@HL Single Channel MPEG-2 Video decoder 24-bit audio Core, MPEG-1 (Layers MPEG2, Dolby® Digital Decoder Gamma Graphics Engine Middleware graphics On-Screen Display Auxiliary Video/Graphics Sub-System Monitor output Exhaustive peripherals Chassis Control DDR333 Unified Memory Interface (LMI) Programmable External Memory Interface (EMI) Flat Panel Display Video Outputs Crystal Oscillator
Rev.
12-bit Video Processing Digital Luma/Chroma Noise Reduction Motion Adaptive Pixel-based Advanced Deinterlacing with Diagonal Compensation Contour Sensitive De-interlacing CSDiFlexible Scaling Engine with Multi Window management capabilities Image Quality Improvement Engine crystal clear crisp pictures
Dual Digital Chroma Decoder (PAL/SECAM/NTSC) with 3D/2D Comb Filter Dual Data Slicer Powerful 32-bit RISC ST40 (266 MHz, MIPS) Dual Transport Stream Demux with DES, Multi2 Descrambler
January 2006
1/11
STD2000
Dual Channel Video Input Processor
Analog Video Inputs
Zoom Zoom independent linear factors from x0.25 Panoramic mode crop independent rescaling Compositor supporting Monochrome Graphics planes Video two-channel processing for: PIP/POP, Picture Picture (Perfect PAP), Picture Graphic (PIG) Color Space Translator (conversion YCrCb 4:4:4 coding) Gamma Correction with programmable anycurve correction Perfect Color Engine (spatio-temporal dithering down 4-to-8 bits) 3x10-bit Digital output flat panel analog outputs Color warping color gammut correction
CVBS, Y/C, 1H/2H/2.14H YPrPb, 1H/2H analog inputs D1/HD Digital video input (CCIR 601-656 SMPTE 274M, SMPTE 296M, SMPTE 260M) Digital video input (proprietary port; YCrCb-4:2:2, off-chip Motioncompensated Video Processing) YCrCb 4:2:2 conversion Dual Digital Chroma Decoder (PAL/NTSC/SECAM) Comb Filter support channel, adaptative 4H/2D comb filter second channel Dual data slicer Teletext, other systems 3:2/2:2 Pulldown, Video/Movie Scene Change Detection Digital Luma Chroma Motion Adaptive Noise Reduction Automatic Letterbox Detection
Digital Video Inputs
Video Output Control
Analog Video Pre-Processing
Sub-System
32-bit RISC ST40 (266 MHz, 480MIPs) Kbytes I-Cache Kbytes D-Cache Floating Point Unit (FPU) Memory Management Unit (MMU)
Dual Channel High Definition Video Processor
Image Processing
On-Chip Memory Kbytes SRAM) Services
100, Field up-rate conversion Motion-adaptive pixel-based advanced deinterlacing with diagonal compensation (CSDiTM: Contour Sensitive Desinterlacer) Contrast Enhancer: Black-White Stretch Blue Stretch Green Boost, Auto-Flesh Tint Control Peaking: Adaptive Peaking Coring Horizontal/Vertical Format Conversion Support 16:9 display aspect ratios
Test Access Port link (JTAG based) Diagnostic Controller Unit (for intrusion, real-time debugging) Advanced User Debug support System Analyzer (SBAG)
Image Quality Improvements
Dual Transport Stream Processor
Dual Transport Stream Demux DES, Multi2 descramblers Dual Transport processing: ATSC (ISO/IEC 13818-x A53) DVB-CI interface (Dual Slot support) CableCARDinterface (Single Slot support)
Video Scaling Composition
2/11
STD2000
MPEG2 Digital Video Decoder
Chassis Control
MPEG2 Video (ISO/IEC 13818-2, ATSC-A54) MP@ML Dual-channel Decode MP@HL Single-channel Decode Data Extraction (closed caption,.)
UARTs Smartcard interface channels each) Four-channel with input capture compare Real-time Clock WatchDog timer Infrared Receiver/Transmitter 10-bit, 8-channel low-speed Converter external interrupt channels with Interrupt Level Controller More than General Purpose Low-power mode wake-up controller
Digital Audio Decoder
24-bit audio Core (with embedded Software Patch RAM) MPEG1 (layers MPEG2, Dolby® Digital ATSC-A52 Lt/Rt Downmix standard Stereo digital outputs Triple channel outputs PCM/Stream Input (S/PDIF external receiver HDMI) S/PDIF Digital Output (IEC60958 IEC61937)
Interfaces
Local Memory Interface (LMI)
64-bit, dual-port memory interface 32-bit DDR-SDRAM device support support Support devices Mbits
Gamma Graphic Processor
Full Screen windowed Bitmap area ARGB-4444 Graphics plane mixed mode 2D-Graphics hardware accelerator GFx/Video programmable alpha-blending Background Color Plane Horizontal and/or Vertical Scrolling, controlled software
Programmable External Memory Interface (EMI)
16-bit/8-bit External Memory Interface supporting Flash optional peripherals Support Flash devices Mbits separately configurable banks Support external memory-mapped sub-systems 3x10-bit digital output flat panel analog outputs
Auxiliary Video/Graphics Processor
On-chip PAL/NTSC/SECAM Encoder monitor output Encoding Teletext, WSS, Closed Caption Graphics plane optional Subtitle support Macrovision Copy Protection (Factory Disable option)
Video Outputs
3/11
General Information
STD2000
General Information
Introduction
STD2000 highly-integrated, high performance system-on-chip iDTV processor that combines Set-top decoding facility with powerful processor. dual-channel PIP/PAP video processor supports High Definition formats. advanced integration drastically reduces integrated Digital costs removing redundancy between Analog Digital source video processing. Compliant with worldwide standards such ATSC, DVB-T, ISDB-T Chinese Digital Terrestrial Standard, STD2000 also includes built-in CableCARDinterface OpenCablespecifications dual DVB-CI interface European DVB-T specifications.
Typical Applications
Typical applications STD2000 system-on-chip illustrated following diagrams:
Figure Digital Cable Ready HDTV
4/11
STD2000
Figure China Digital Cable HDTV
General Information
Chinese C.I.
Figure Europe iDTV
Optional
5/11
STD2000 List
STD2000
STD2000 List
General Package Information
STD2000 delivered 745-ball package.
Table Package Information
Package Type Body Size Ball Count Ball Pitch Ball Matrix Center Matrix MCM-BGA 1.27 (5-row perimeter) Balls Balls Balls
Figure STD2000 Package Overview
AA10 AB10 AC10 AA11 AB11 AC11 AA12 AB12 AC12 AA13 AB13 AC13 AA14 AB14 AC14 AA15 AB15 AC15 AA16 AB16 AC16 AA17 AB17 AC17 AA18 AB18 AC18 AA19 AB19 AC19 AA20 AB20 AC20 AA21 AB21 AC21 AA22 AB22 AC22 AA23 AB23 AC23 AA28 AB28 AC28 AD28 AE28 AF28 AG28 AH28 AJ28 AK28 AL28 AA29 AB29 AC29 AD29 AE29 AF29 AG29 AH29 AJ29 AK29 AL29 AA30 AB30 AC30 AD30 AE30 AF30 AG30 AH30 AJ30 AK30 AL30
2.5V Supply
Feed_Back 2.5V
3.3V Supply
AA27 AB27 AC27 AD27 AE27 AF27
test
System
(NC)
AA31 AB31 AC31 AD31 AE31 AF31 AG31 AH31 AJ31
Supply 1.0V
Denc
Test
Audio
COMs
Supply 1.8V 3.3V Supply
Supply 3.3VA
Supply 1.8VA
Analog
AG10 AH10 AJ10 AK10 AL10 AG11 AH11 AJ11 AK11 AL11 AG12 AH12 AJ12 AK12 AL12 AG13 AH13 AJ13 AK13 AL13
Analog
AG14 AH14 AJ14 AK14 AL14 AG15 AH15 AJ15 AK15 AL15 AG16 AH16 AJ16 AK16 AL16 AG17 AH17 AJ17 AK17 AL17 AG18 AH18 AJ18 AK18 AL18
Power supply feedback
2.5V Analog Supply
AG19 AH19 AJ19 AK19 AL19 AG20 AH20 AJ20 AK20 AL20 AG21 AH21 AJ21 AK21 AL21 AG22 AH22 AJ22 AK22 AL22 AG23 AH23 AJ23 AK23 AL23 AG24 AH24 AJ24 AK24 AL24 AG25 AH25 AJ25 AK25 AL25 AG26 AH26 AJ26 AK26 AL26
AG27 AH27 AJ27 AK27 AL27
AK31 AL31
PIOs
Scan
Analog
Analog
Denc
System1
Audio
COMs
6/11
STD2000
Ballout Description
ball DDR2_DQS3 DDR2_D25 DDR2_D24 DDR_REXT VDD33P EMI_OE EMI_D0 EMI_FLA_CSN EMI_A0 DDR2_D31 DDR2_D30 DDR2_D27 DDR2_D29 DDR2_D28 VDD33P EMI_CSN0 EMI_CSN1 EMI_WAIT (NC-15)
signal
ball
signal
ball
signal
ball
signal
ball
signal
ball
signal
ball
signal
ball
signal
Figure Ballout Information (Part
DDR2_CAS DDR2_BA1 DDR2_AD3 DDR2_BA0 DDR2_D13 DDR2_D8 DDR2_DQS0 DDR2_D4 DDR2_D0 DDR1_D28 DDR1_D24 DDR1_DM2 DDR1_D21 DDR1_D17 DDR1_AD6 DDR1_AD8 DDR1_CLK DDR1_AD5 DDR1_CS DDR1_AD3 DDR1_RAS DDR1_D14 DDR1_D10 DDR1_DM1 DDR1_D7 DDR1_D3 EMI_A2 EMI_A6 EMI_A18 EMI_R/WN EMI_A20 DDR2_VREF DDR2_CS DDR2_AD2 DDR2_AD10 DDR2_D14 DDR2_D9 DDR2_DM0 DDR2_D5 DDR2_D1 DDR1_D29 DDR1_D25 DDR1_DM3 DDR1_D22 DDR1_D18 DDR1_AD4 DDR1_AD11 DDR1_AD12 DDR1_VREF DDR1_BA1 DDR1_AD1
DDR2_CLK DDR2_AD12 DDR2_AD9 DDR2_AD1 DDR2_D15 DDR2_D10 DDR2_DM1 DDR2_D6 DDR2_D2 DDR1_D30 DDR1_D26 DDR1_DQS3 DDR1_D23 DDR1_D19 DDR1_D16 DDR1_CKE DDR1_AD9 DDR1_CAS DDR1_AD0 DDR1_AD10 DDR1_D15 DDR1_D12 DDR1_D8 DDR1_DQS0 DDR1_D5 DDR1_D1 EMI_A4 EMI_A13 EMI_A12 EMI_A14 EMI_A15 DDR2_AD11 DDR2_CLKN DDR2_CKE DDR2_WE DDR2_D11 DDR2_DQS1 VDD25P VDD25P VDD25P VDD25P VDD25P VDD25P VDD25P VDD25P VDD25P VDD25P VDD25P VDD25P VDD25P
VDD33P (NC-9) (NC-10) (NC-8) (NC-7) SBA_SYNC AUD_CK AUD_DAT2 AUD_DAT0 AUD_DAT1 VDD33P (NC-5) (NC-6) (NC-4) (NC-3) SBA_CK SBA_DAT0 SBA_DAT3 SBA_DAT1 SBA_DAT2 VDD10P
MS_TDI VDD33P CI2_MDI0 CI1_MISTRT CI1_MDI0 CI2_MDI1 YCL_VAL YCL_VSYNC D1O_BI_CBI_2 D1O_BI_CBI_0 CI1_MOVAL D1O_BI_CBI_1 CI2_MOVAL VDD10P CI2_MDO5 CI1_MDO5 D1I_HD_CK D1I_HD_HSYNC D1I_HD_VSYNC MS_TMS AA10 MS_TSTRSTN AA11 AA12 MS_SCANMODE AA13 MS_TSTMODE AA14 AA15 TST_AFE0 DENC_VREF AA16 TST_AFE1 CI1_WAIT AA17 TST_AFE2 CI2_MIVAL AA18 TST_AFE3 CI2_WAIT AA19 CI1_MIVAL AA20 MS_TSTCK27 CI2_MISTRT_POD_OOB_DI AA21 MS_TSTCK54 D1O_BI_CBI_3 AA22 MS_TSTCK81 D1O_BI_CBI_4 AA23 D1O_BI_CBI_7 AA27 CI2_IREQ D1O_BI_CBI_5 AA28 CI1_IREQ D1O_BI_CBI_6 AA29 CI1_MDO3 VDD10P AA30 CI2_MDO4 AA31 CI1_MDO4 INT7 SDA1 SCL1 MS_TRST
AC30 CI1_MDO0 AC31 CI2_MDO1 MAFEIF_FSI SC_CLK SC_DATA SC_RST SC_CMD_VCC AD27 CI1_CE1_POD_CE2 AD28 CI_OE AD29 CI2_CE1_POD_CE1 AD30 CI_IORD AD31 CI_IOWR SC_DETECT CDA_REQ_RXD CDA_DAT_CTS CDA_CK_TXD CDA_DVAL_RTS AE27 CI2_MDI6 AE28 CI1_MDI6 AE29 CI1_MDI5 AE30 CI2_MDI7 AE31 CI1_MDI7 INT0 INT1 GPIO2 GPIO0 GPIO1 AF27 CI1_MDI3 AF28 CI2_MDI4 AF29 CI2_MDI3 AF30 CI1_MDI4 AF31 CI2_MDI5 TIMER1_PWM4 V10_REG_OUT V18_REG_OUT SDA0 SCL0 VDD33S VDD33S VDD33S VDD33S AG10 IREF_ABE AG11 GNDREF_ABE AG12 VREF_ABE AG13 REFP_AFE_F AG14 REFN_AFE_F AG15 RREF_AFE AG16 RREF_GND_AFE AG17 VREF_AFE AG18 REFP_AFE_S AG19 VCC10P
AH31 TS2_DIN1 FPD_B5 FPD_B4 FPD_B3 FPD_G7 FPD_G4 FPD_G0 FPD_R6 FPD_R2 FPD_DE_PWM3 AJ10 HOUTA_PWM2 AJ11 HCLKVBK AJ12 ROUT AJ13 AJ14 CVBS2_Y2_N AJ15 R1_C1_PR1_P AJ16 VSYNC AJ17 DENC_Y AJ18 SSCG_CKI AJ19 XTALOUT AJ20 CLKXTP AJ21 I2SO_DAT2 AJ22 I2SO_MCK AJ23 INT3 AJ24 AJ25 TIMER0_BLAST_OUT AJ26 SDA2 AJ27 TS1_DIN6 AJ28 TS1_DIN2 AJ29 TS1_CK AJ30 TS2_DIN5 AJ31 TS2_DIN4 FPD_B2 FPD_B1 FPD_G8 FPD_G6 FPD_G2 FPD_R8 FPD_R4 FPD_R0 FPD_CK1_VFLYBACK AK10 HS_OUT AK11 AK12 BOUT AK13 C2_PR2_N AK14 CVBS1_Y1_PB2_N AK15 G1_CVBS1P_Y1P_P AK16 B1_PB1_N AK17 AK18 AK19
STD2000 List
7/11
8/11
ball signal ball signal ball signal ball signal ball signal ball signal
STD2000 List
ball
signal
ball
signal
Figure Ballout Information (Part
DDR1_WE DDR1_D13 DDR1_D9 DDR1_DM0 DDR1_D6 DDR1_D2 EMI_A3 EMI_A7 EMI_A21 EMI_A19 EMI_A8 DDR2_AD7 DDR2_AD5 DDR2_AD0 DDR2_RAS DDR2_D12 DDR2_D7 DDR2_D3 DDR1_D31 DDR1_D27 DDR1_DQS2 DDR1_D20 DDR1_CLKN DDR1_AD7 DDR1_AD2 DDR1_BA0 DDR1_D11 DDR1_DQS1 DDR1_D4 EMI_A1 EMI_A5 EMI_A17 EMI_A9 EMI_A10 EMI_A11 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29 AG30 AG31 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 AH30 AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27 AK28 AK29 AK30 AK31 AL10 AL11 AL12 AL13 AL14 AL15 AL16 AL17 AL18 AL19 AL20 AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30 AL31
VDD25P VDD25P VDD25P VDD25P VDD25P DDR1_D0 EMI_A22 EMI_A16 EMI_CSN2 EMI_D15 EMI_D7 DDR2_D17 DDR2_D16 DDR2_AD8 DDR2_AD4 DDR2_AD6 EMI_D6 EMI_D13 EMI_D14 EMI_D5 EMI_D12 DDR2_D21 DDR2_D20 DDR2_D18 DDR2_D19 VDD33P EMI_D11 EMI_D4 EMI_D3 EMI_D10 DDR2_DM3 DDR2_DM2 DDR2_D22 DDR2_DQS2 DDR2_D23 VDD33P EMI_D9 EMI_D2 EMI_D1 EMI_D8 DDR2_D26
V25_REG_OUT ASEBRK RESETN VDD33P (NC-13) (NC-14) (NC-12) (NC-11) AUD_DAT3 AUD_SYNC TRST CORE_TST
VDD33P (NC-1) (NC-2) CI1_CI2_CS CI1_CD2 YCL_RI_CRI_4 YCL_RI_CRI_3 YCL_RI_CRI_0 YCL_RI_CRI_2 YCL_RI_CRI_1 VDD10P VDD33P CI1_MDI2 CI2_CD2 CI2_MDI2 CI1_MDI1 YCL_RI_CRI_5 YCL_RI_CRI_6 YCL_REQ YCL_RI_CRI_7 YCL_CK VDD10P
AB10 AB11 AB12 AB13 AB14 AB15 DENC_IREF AB16 CI2_MCLKI_POD_OOB_ AB17 CI1_MCLKI_POD_A14 AB18 CI1_MDO7 AB19 CI2_RESET AB20 CI1_RESET AB21 D1O_CK AB22 AB23 D1I_GI_YI82 AB27 D1I_GI_YI_0 AB28 D1I_GI_YI_1 AB29 VDD10P AB30 AB31 AC10 AC11 AC12 AC13 AC14 AC15 AC16 CI1_MCLKO AC17 CI2_MDO6 AC18 CI2_MCLKO_POD_RC74AC19 CI1_MDO6 AC20 CI2_MDO7 AC21 D1I_GI_YI_3 AC22 D1I_GI_YI_4 AC23 D1I_GI_YI_7 AC27 D1I_GI_YI_5 AC28 D1I_GI_YI_6 AC29
CI2_MDO2 CI1_MDO2 CI1_MDO1 CI_WE CI2_MDO3 INT6 MAFEIF_DOUT MAFEIF_DIN MAFEIF_HC1 MAFEIF_SCLK MS_TCK MS_TDO VDD18S VDD18S VDD18S VDD18S VCC33S VCC33S VCC33S VCC18S VCC18S VCC18S VCC18S CI1_MOSTRT CI2_MDO0_POD_A8 CI2_MOSTRT_POD_A9
VCC10P VCC25P I2SO_SCK INT2 INT5 TS1_DIN7 TS2_CK TS2_DIN0 CI2_CD1 CI1_CD1 FPD_B9 FPD_B8 FPD_B6 FPD_B7 FPD_G3 FPD_R9 FPD_R5 FPD_R1 FPD_CK2_PWM0 VS_OUT BCL_SAF GOUT CVBS2_Y2_P R1_C1_PR1_N DENC_CVBS REFN_AFE_S VCC10P VCC25P VCC25P I2SO_LRCK SCL3 TIMER3_INT4 TS1_STR TS1_DIN3 TS2_DIN3 TS2_DIN2
I2SO_DAT0 SDA3 TIMER2_PWM5 TS1_VDAT TS1_DIN4 TS1_DIN0 TS2_STR TS2_DIN6 FPD_B0 FPD_G9 FPD_G5 FPD_G1 FPD_R7 FPD_R3 FPD_GFX_PWM1 HDRIVE VMEAS ICATH BLANKOUT C2_PR2_P CVBS1_Y1_PB2_P G1_CVBS1P_Y1P_N B1_PB1_P HCSYNC DENC_C SSCG_CKO XTALIN CLKXI2SO_DAT1 SPDIF_OUT GPIO3 SCL2 TS1_DIN5 TS1_DIN1 TS2_VDAT TS2_DIN7
STD2000
STD2000
Package Mechanical Data
Package Mechanical Data
9/11
Revision History
STD2000
Revision History
Date
1-Mar-2005 2-Jan 2006
Revision
Initial release
Changes
Small changes applied block diagram, features, figures
10/11
STD2000
NOTES:
Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. logo registered trademark STMicroelectronics other names property their respective owners 2006 STMicroelectronics rights reserved STMicroelectronics Group Companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States www.st.com
11/11

Single-Chip Worldwide iDTV Processor DATABRIEF SD/HD Digital

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