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8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA + 80C51 8-bit microcontroller family

8K­64K / 256­1K OTP / ROM / ROMless, low voltage (2.7V­5.5V), low power, high speed (33 MHz)

INTEGRATED CIRCUITS
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA + 80C51 8-bit microcontroller family
8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33 MHz)
Product specification Supersedes data of 1998 Jun 04 IC20 Data Handbook 1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33 MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
DESCRIPTION
Three different Single-Chip 8-Bit Microcontroller families are presented in this datasheet:
FEATURES
· 80C32 / 8XC52 / 8XC54 / 8XC58 · 80C51FA / 8XC51FA / 8XC51FB / 8XC51FC · 80C51RA+ / 8XC51RA+ / 8XC51RB+ / 8XC51RC+ / 8XC51RD+
For applications requiring 4K ROM / EPROM, see the 8XC51 / 80C31 8-bit CMOS (low voltage, low power, and high speed) microcontroller families datasheet. All the families are Single-Chip 8-Bit Microcontrollers manufactured in advanced CMOS process and are derivatives of the 80C51 microcontroller family. All the devices have the same instruction set as the 80C51. These devices provide architectural enhancements that make them applicable in a variety of applications for general control systems. ROM / EPROM Memory Size (X by 8) 80C31 / 8XC51 0K / 4K 80C32 / 8XC52 / 54 / 58 0K / 8K / 16K / 32K 256 No No 128 No No RAM Size (X by 8) Programmable Timer Counter (PCA) Hardware Watch Dog Timer
· 80C51 Central Processing Unit · Speed up to 33MHz · Full static operation · Operating voltage range: 2.7V to 5.5V @ 16MHz · Security bits:
- ROM - 2 bits - OTP-EPROM - 3 bits
· Encryption array - 64 bytes · RAM expandable to 64K bytes · 4 level priority interrupt · 6 or7 interrupt sources, depending on device · Four 8-bit I / O ports · Full-duplex enhanced UART
- Framing error detection - Automatic address recognition
· Power control modes
- Clock can be stopped and resumed - Idle mode - Power down mode
80C51FA / 8XC51FA / FB / FC 0K / 8K / 16K / 32K 256 Yes No
80C51RA+ / 8XC51RA+ / RB+ / RC+ 0K / 8K / 16K / 32K 8XC51RD+ 64K 1024 Yes Yes 512 Yes Yes
· Programmable clock out · Second DPTR register · Asynchronous port reset · Low EMI (inhibit ALE)
The ROMless devices, 80C32, 80C51FA, and 80C51RA+ can address up to 64K of external memory. All the devices have four 8-bit I / O ports, three 16-bit timer / event counters, a multi-source, four-priority-level, nested interrupt structure, an enhanced UART and on-chip oscillator and timing circuits. For systems that require extra memory capability up to 64k bytes, each can be expanded using standard TTL-compatible memories and logic. Its added features make it an even more powerful microcontroller for applications that require pulse width modulation, high-speed I / O and up / down counting capabilities such as motor control. It also has a more versatile serial channel that facilitates multiprocessor communications.
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33 MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
BLOCK DIAGRAM
P0.0-P0.7 P2.0-P2.7
PORT 0 DRIVERS VCC VSS RAM ADDR REGISTER RAM PORT 0 LATCH
PORT 2 DRIVERS
PORT 2 LATCH
ROM / EPROM
8 B REGISTER STACK POINTER
PROGRAM ADDRESS REGISTER
ALU SFRs TIMERS PSW P.C.A. (FA & RA+ only) 8
BUFFER
PC INCREMENTER 16 PROGRAM COUNTER
PSEN ALE / PROG EAVPP RST PD TIMING AND CONTROL
INSTRUCTION REGISTER
PORT 1 LATCH
PORT 3 LATCH
OSCILLATOR PORT 1 DRIVERS XTAL1 XTAL2 P1.0-P1.7 PORT 3 DRIVERS
P3.0-P3.7
SU00831B
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33 MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
LOGIC SYMBOL
VCC XTAL1 PORT 0 ADDRESS AND DATA BUS VSS
PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS
XTAL2 T2 T2EX PORT 1 RST EA / VPP PSEN SECONDARY FUNCTIONS ALE / PROG RxD TxD INT0 INT1 T0 T1 WR RD
18 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function NIC P1.0 / T2 P1.1 / T2EX P1.2 / ECI P1.3 / CEX0 P1.4 / CEX1 P1.5 / CEX2 P1.6 / CEX3 P1.7 / CEX4 RST P3.0 / RxD NIC P3.1 / TxD P3.2 / INT0 P3.3 / INT1 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Function P3.4 / T0 P3.5 / T1 P3.6 / WR P3.7 / RD XTAL2 XTAL1 VSS NIC P2.0 / A8 P2.1 / A9 P2.2 / A10 P2.3 / A11 P2.4 / A12 P2.5 / A13 P2.6 / A14
28 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function P2.7 / A15 PSEN ALE / PROG NIC EA / VPP P0.7 / AD7 P0.6 / AD6 P0.5 / AD5 P0.4 / AD4 P0.3 / AD3 P0.2 / AD2 P0.1 / AD1 P0.0 / AD0 VCC
PORT 3
PORT 2
ADDRESS BUS
SU00830
PIN CONFIGURATIONS DUAL IN-LINE PACKAGE PIN FUNCTIONS
T2 / P1.0 1 T2EX / P1.1 2 ECI / P1.2 3 CEX0 / P1.3 4 CEX1 / P1.4 5 CEX2 / P1.5 6 CEX3 / P1.6 7 CEX4 / P1.7 8 RST 9 RxD / P3.0 10 TxD / P3.1 11 INT0 / P3.2 12 INT1 / P3.3 13 T0 / P3.4 14 T1 / P3.5 15 WR / P3.6 16 RD / P3.7 17 XTAL2 18 XTAL1 19 VSS 20 DUAL IN-LINE PACKAGE 40 VCC 39 P0.0 / AD0 38 P0.1 / AD1 37 P0.2 / AD2 36 P0.3 / AD3 35 P0.4 / AD4 34 P0.5 / AD5 33 P0.6 / AD6 32 P0.7 / AD7 31 EA / VPP 30 ALE / PROG 29 PSEN 28 P2.7 / A15 27 P2.6 / A14 26 P2.5 / A13 25 P2.4 / A12 24 P2.3 / A11 23 P2.2 / A10 22 P2.1 / A9 21 P2.0 / A8
NO INTERNAL CONNECTION
SU00023
PLASTIC QUAD FLAT PACK PIN FUNCTIONS
12 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function P1.5 / CEX2 P1.6 / CEX3 P1.7 / CEX4 RST P3.0 / RxD NIC P3.1 / TxD P3.2 / INT0 P3.3 / INT1 P3.4 / T0 P3.5 / T1 P3.6 / WR P3.7 / RD XTAL2 XTAL1 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Function VSS NIC P2.0 / A8 P2.1 / A9 P2.2 / A10 P2.3 / A11 P2.4 / A12 P2.5 / A13 P2.6 / A14 P2.7 / A15 PSEN ALE / PROG NIC EA / VPP P0.7 / AD7
22 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function P0.6 / AD6 P0.5 / AD5 P0.4 / AD4 P0.3 / AD3 P0.2 / AD2 P0.1 / AD1 P0.0 / AD0 VCC NIC P1.0 / T2 P1.1 / T2EX P1.2 / ECI P1.3 / CEX0 P1.4 / CEX1
SU00021
NO INTERNAL CONNECTION
SU00024
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33 MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
PIN DESCRIPTIONS
P1.0-P1.7
1 2 3 4 5 6 7 8 P2.0-P2.7 21-28
P3.0-P3.7
ALE / PROG
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33 MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
PIN DESCRIPTIONS (Continued)
PIN NUMBER MNEMONIC PSEN DIP 29 LCC 32 QFP 26 TYPE O NAME AND FUNCTION Program Store Enable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. External Access Enable / Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations starting with 0000H. If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 8k Devices (IFFFH), 16k Devices (3FFFH) or 32k Devices (7FFFH). Since the RD+ has 64k Internal Memory, the RD+ will execute only from internal memory when EA is held high. This pin also receives the 12.75V programming supply voltage (VPP) during EPROM programming. If security bit 1 is programmed, EA will be internally latched on Reset. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier.
XTAL1 XTAL2
NOTE: To avoid "latch-up" effect at power-on, the voltage on any pin at any time must not be higher than VCC + 0.5V or VSS - 0.5V, respectively.
1999 Apr 01
Philips Semiconductors
1999 Apr 01 7
8XC52 / 54 / 58 AND 80C32 ORDERING INFORMATION
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
Note: For Multi Time Programmable devices, See P89C51RX+ Flash datasheet.
Product specification
Philips Semiconductors
1999 Apr 01 8
8XC51FA / FB / FC AND 80C51FA ORDERING INFORMATION
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
Note: For Multi Time Programmable devices, See P89C51RX+ Flash datasheet.
Product specification
Philips Semiconductors
1999 Apr 01 9
87C51RA+ / RB+ / RC+ / RD+ AND 80C51RA+ ORDERING INFORMATION
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
2.7V 5.5V 2 7V to 5 5V
SOT187-2 SOT187 2
2.7V 5.5V 2 7V to 5 5V
SOT307-2 SOT307 2
2.7V 5.5V 2 7V to 5 5V
SOT129-1 SOT129 1
2.7V 5.5V 2 7V to 5 5V
SOT187-2 SOT187 2
2.7V 5.5V 2 7V to 5 5V
SOT307-2 SOT307 2
SOT129 1 SOT129-1
SOT187-2 SOT187 2
SOT307-2 SOT307 2
SOT129-1 SOT129 1
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
SOT187-2 SOT187 2
SOT307-2
Note: For Multi Time Programmable devices, See P89C51RX+ Flash datasheet.
Product specification
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
Table 1.
SYMBOL ACC AUXR# AUXR1# B DPTR: DPH DPL IE IP IPH# P0 P1 P2 P3 PCON#1 PSW RCAP2H# RCAP2L# SADDR# SADEN# SBUF SCON SP TCON T2CON T2MOD# TH0 TH1 TH2# TL0 TL1 TL2#
8XC52 / 54 / 58 / 80C32 Special Function Registers
DESCRIPTION Accumulator Auxiliary Auxiliary 1 B register Data Pointer (2 bytes) Data Pointer High Data Pointer Low Interrupt Enable Interrupt Priority Interrupt Priority High Port 0 Port 1 Port 2 Port 3 Power Control Program Status Word Timer 2 Capture High Timer 2 Capture Low Slave Address Slave Address Mask Serial Data Buffer Serial Control Stack Pointer Timer Control Timer 2 Control Timer 2 Mode Control Timer High 0 Timer High 1 Timer High 2 Timer Low 0 Timer Low 1 Timer Low 2 DIRECT ADDRESS E0H 8EH A2H F0H 83H 82H AF A8H B8H B7H 80H 90H A0H B0H 87H D0H CBH CAH A9H B9H 99H 9F 98H 81H 8F 88H C8H C9H 8CH 8DH CDH 8AH 8BH CCH TF1 CF TF2 - 8E TR1 CE EXF2 - 8D TF0 CD RCLK - 8C TR0 CC TCLK - 8B IE1 CB EXEN2 - 8A IT1 CA TR2 - 89 IE0 C9 C / T2 T2OE 88 IT0 C8 CP / RL2 DCEN 00H xxxxxx00B 00H 00H 00H 00H 00H 00H 00H 00H
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB E7 - - F7 E6 - - F6 E5 - - F5 E4 - LPEP3 F4 E3 - GF3 F3 E2 - 0 F2 E1 - - F1 E0 AO DPS F0
RESET VALUE 00H xxxxxxx0B xxx0xxx0B 00H 00H 00H
AE - BE - B6 - 86 AD6 96 - A6 AD14 B6 WR SMOD0 D6 AC
AD ET2 BD PT2 B5 PT2H 85 AD5 95 - A5 AD13 B5 T1 - D5 F0
AC ES BC PS B4 PSH 84 AD4 94 - A4 AD12 B4 T0 POF2 D4 RS1
AB ET1 BB PT1 B3 PT1H 83 AD3 93 - A3 AD11 B3 INT1 GF1 D3 RS0
AA EX1 BA PX1 B2 PX1H 82 AD2 92 - A2 AD10 B2 INT0 GF0 D2 OV
A9 ET0 B9 PT0 B1 PT0H 81 AD1 91 T2EX A1 AD9 B1 TxD PD D1 -
A8 EX0 B8 PX0 B0 PX0H 80 AD0 90 T2 A0 AD8 B0 RxD IDL D0 P 000000x0B 00H 00H 00H 00H xxxxxxxxB FFH 00xx0000B FFH FFH FFH xx000000B xx000000B 0x000000B
EA BF - B7 - 87 AD7 97 - A7 AD15 B7 RD SMOD1 D7 CY
9E SM1
9D SM2
9C REN
9B TB8
9A RB8
98 RI 00H 07H
TMOD Timer Mode 89H GATE SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. - Reserved bits. 1. Reset value depends on reset source. 2. Bit will not be affected by Reset. 3. LPEP - Low Power OTP-EPROM only operation.
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
Table 2.
SYMBOL ACC AUXR# AUXR1# B CCAP0H# CCAP1H# CCAP2H# CCAP3H# CCAP4H# CCAP0L# CCAP1L# CCAP2L# CCAP3L# CCAP4L# CCAPM0# CCAPM1# CCAPM2# CCAPM3# CCAPM4#
8XC51FA / FB / FC, 8XC51RA+ / RB+ / RC+ / RD+ Special Function Registers
DESCRIPTION Accumulator Auxiliary Auxiliary 1 B register Module 0 Capture High Module 1 Capture High Module 2 Capture High Module 3 Capture High Module 4 Capture High Module 0 Capture Low Module 1 Capture Low Module 2 Capture Low Module 3 Capture Low Module 4 Capture Low Module 0 Mode Module 1 Mode Module 2 Mode Module 3 Mode Module 4 Mode DIRECT ADDRESS E0H 8EH A2H F0H FAH FBH FCH FDH FEH EAH EBH ECH EDH EEH DAH DBH DCH DDH DEH - - - - - DF ECOM ECOM ECOM ECOM ECOM DE CR CAPP CAPP CAPP CAPP CAPP DD - CAPN CAPN CAPN CAPN CAPN DC CCF4 MAT MAT MAT MAT MAT DB CCF3 TOG TOG TOG TOG TOG DA CCF2 PWM PWM PWM PWM PWM D9 CCF1 ECCF ECCF ECCF ECCF ECCF D8 CCF0 00x00000B 00H 00H 00xxx000B 00H 00H AF AE EC BE PPC B6 PPCH 86 AD6 96 CEX3 A6 AD14 B6 WR SMOD0 AD ET2 BD PT2 B5 PT2H 85 AD5 95 CEX2 A5 AD13 B5 T1 - AC ES BC PS B4 PSH 84 AD4 94 CEX1 A4 AD12 B4 T0 POF2 AB ET1 BB PT1 B3 PT1H 83 AD3 93 CEX0 A3 AD11 B3 INT1 GF1 AA EX1 BA PX1 B2 PX1H 82 AD2 92 ECI A2 AD10 B2 INT0 GF0 A9 ET0 B9 PT0 B1 PT0H 81 AD1 91 T2EX A1 AD9 B1 TxD PD A8 EX0 B8 PX0 B0 PX0H 80 AD0 90 T2 A0 AD8 B0 RxD IDL FFH 00xx0000B FFH FFH FFH x0000000B x0000000B 00H EA BF - B7 - 87 BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB E7 - - F7 E6 - - F6 E5 - - F5 E4 - LPEP3 F4 E3 - GF3 F3 E2 - 0 F2 E1
EXTRAM (RX+ only)
LSB E0 AO DPS F0
RESET VALUE 00H xxxxxx00B xxx0xxx0B 00H xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB x0000000B x0000000B x0000000B x0000000B x0000000B
CCON# CH# CL# CMOD# DPTR: DPH DPL IE IP IPH#
PCA Counter Control PCA Counter High PCA Counter Low PCA Counter Mode Data Pointer (2 bytes) Data Pointer High Data Pointer Low Interrupt Enable Interrupt Priority Interrupt Priority High
D8H F9H E9H D9H 83H 82H A8H B8H B7H
Port 0 Port 1 Port 2 Port 3
80H 90H A0H B0H
AD7 97 CEX4 A7 AD15 B7 RD
PCON#1 Power Control 87H SMOD1 SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. - Reserved bits. 1. Reset value depends on reset source. 2. Bit will not be affected by Reset. 3. LPEP - Low Power OTP-EPROM only operation. 1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
Table 2.
SYMBOL
8XC51FA / FB / FC, 8XC51RA+ / RB+ / RC+ / RD+ Special Function Registers (Continued)
DESCRIPTION DIRECT ADDRESS D0H CBH CAH A9H B9H 99H 9F 9E SM1 8E TR1 CE EXF2 - 9D SM2 8D TF0 CD RCLK - 9C REN 8C TR0 CC TCLK - 9B TB8 8B IE1 CB EXEN2 - 9A RB8 8A IT1 CA TR2 - 99 TI 89 IE0 C9 C / T2 T2OE 98 RI 88 IT0 C8 CP / RL2 DCEN 00H xxxxxx00B 00H 00H 00H 00H 00H 00H GATE C / T M1 M0 GATE C / T M1 M0 00H 00H 00H 07H 8F TF1 CF 98H 81H 88H
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB D7 D6 AC D5 F0 D4 RS1 D3 RS0 D2 OV D1 - D0 P CY
RESET VALUE 000000x0B 00H 00H 00H 00H xxxxxxxxB
PSW RACAP2H# RACAP2L# SADDR# SADEN# SBUF SCON SP TCON
Program Status Word Timer 2 Capture High Timer 2 Capture Low Slave Address Slave Address Mask Serial Data Buffer Serial Control Stack Pointer Timer Control
T2CON T2MOD# TH0 TH1 TH2# TL0 TL1 TL2# TMOD WDTRST
Timer 2 Control Timer 2 Mode Control Timer High 0 Timer High 1 Timer High 2 Timer Low 0 Timer Low 1 Timer Low 2 Timer Mode
C8H C9H 8CH 8DH CDH 8AH 8BH CCH 89H
HDW Watchdog 0A6H Timer Reset (RX+ only) SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. - Reserved bits.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed.
RESET
A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. To insure a good power-on reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-on, the voltage on VCC and RST must come up at the same time for a proper start-up. Ports 1, 2, and 3 will asynchronously be driven to their reset condition when a voltage above VIH1 (min.) is applied to RESET.
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
LOW POWER MODES Stop Clock Mode
The static design enables the clock speed to be reduced down to 0 MHz (stopped). When the oscillator is stopped, the RAM and Special Function Registers retain their values. This mode allows step-by-step utilization and permits reduced system power consumption by lowering the clock frequency down to any value. For lowest power consumption the Power Down mode is suggested.
POWER OFF FLAG
The Power Off Flag (POF) is set by on-chip circuitry when the VCC level on the 8XC51FX / 8XC51RX+ rises from 0 to 5V. The POF bit can be set or cleared by software allowing a user to determine if the reset is the result of a power-on or a warm start after powerdown. The VCC level must remain above 3V for the POF to remain unaffected by the VCC level.
Design Consideration
Idle Mode
In the idle mode (see Table 3), the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset.
· When the idle mode is terminated by a hardware reset, the device
normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.
ONCE Mode
The ONCE ("On-Circuit Emulation") Mode facilitates testing and debugging of systems without the device having to be removed from the circuit. The ONCE Mode is invoked by: 1. Pull ALE low while the device is in reset and PSEN is high 2. Hold ALE low as RST is deactivated. While the device is in ONCE Mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator circuit remains active. While the device is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied.
Power-Down Mode
To save even more power, a Power Down mode (see Table 3) can be invoked by software. In this mode, the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values down to 2.0V and care must be taken to return VCC to the minimum specified operating voltages before the Power Down Mode is terminated. Either a hardware reset or external interrupt can be used to exit from Power Down. Reset redefines all the SFRs but does not change the on-chip RAM. An external interrupt allows both the SFRs and the on-chip RAM to retain their values. To properly terminate Power Down the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10ms). With an external interrupt, INT0 and INT1 must be enabled and configured as level-sensitive. Holding the pin low restarts the oscillator but bringing the pin back high completes the exit. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down.
Programmable Clock-Out
The LPEP bit (AUXR.4), only needs to be set for applications operating at VCC less than 4V.
Table 3. External Pin Status During Idle and Power-Down Mode
MODE Idle Idle Power-down Power-down PROGRAM MEMORY Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT 0 Data Float Data Float PORT 1 Data Data Data Data PORT 2 Data Address Data Data PORT 3 Data Data Data Data
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
TIMER 2 OPERATION Timer 2
Timer 2 is a 16-bit Timer / Counter which can operate as either an event timer or an event counter, as selected by C / T2 in the special function register T2CON (see Figure 1). Timer 2 has three operating modes: Capture, Auto-reload (up or down counting), and Baud Rate Generator, which are selected by bits in the T2CON as shown in Table 4.
Capture Mode
Auto-Reload Mode (Up or Down Counter)
In the 16-bit auto-reload mode, Timer 2 can be configured (as either a timer or counter C / T2 in T2CON) then programmed to count up or down. The counting direction is determined by bit DCEN (Down Counter Enable) which is located in the T2MOD register (see
(MSB) TF2 Symbol TF2 EXF2 Position T2CON.7 T2CON.6 EXF2 RCLK TCLK EXEN2 TR2 C / T2
(LSB) CP / RL2
SU00728
RCLK TCLK EXEN2
T2CON.5 T2CON.4 T2CON.3
T2CON.2 T2CON.1
T2CON.0
Figure 1. Timer / Counter 2 (T2CON) Control Register 1999 Apr 01 14
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
Table 4. Timer 2 Operating Modes
RCLK + TCLK 0 0 1 X CP / RL2 0 1 X X TR2 1 1 1 0 16-bit Auto-reload 16-bit Capture Baud rate generator (off) MODE
T2 Pin
Control
TR2 Transition Detector
Capture Timer 2 Interrupt RCAP2L RCAP2H
T2EX Pin
Control
EXEN2
SU00066
Figure 2. Timer 2 in Capture Mode
T2MOD
DCEN 0
Symbol - T2OE DCEN
Function Not implemented, reserved for future use. Timer 2 Output Enable bit. Down Count Enable bit. When set, this allows Timer 2 to be configured as an up / down counter.
User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Figure 3. Timer 2 Mode (T2MOD) Control Register
SU00729
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
T2 PIN
CONTROL
RELOAD
TRANSITION DETECTOR
RCAP2L
RCAP2H TF2 TIMER 2 INTERRUPT
T2EX PIN
CONTROL
EXEN2
SU00067
(DOWN COUNTING RELOAD VALUE) FFH FFH
TOGGLE EXF2
T2 PIN
(UP COUNTING RELOAD VALUE)
SU00730
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
Timer 1 Overflow
RX Clock
Transition Detector
RCAP2L
RCAP2H
TX Clock
T2EX Pin
Timer 2 Interrupt
Control EXEN2 Note availability of additional external interrupt.
SU00068
Figure 6. Timer 2 in Baud Rate Generator Mode
Table 5.
Timer 2 Generated Commonly Used Baud Rates
Timer 2 Osc Freq 12MHz 12MHz 12MHz 12MHz 12MHz 12MHz 12MHz 6MHz 6MHz RCAP2H FF FF FF FF FE FB F2 FD F9 RCAP2L FF D9 B2 64 C8 1E AF 8F 57
Ba d Rate Baud 375K 9.6K 2.8K 2.4K 1.2K 300 110 300 110
Baud Rate Generator Mode
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
When Timer 2 is in the baud rate generator mode, one should not try to read or write TH2 and TL2. As a baud rate generator, Timer 2 is incremented every state time (osc / 2) or asynchronously from pin T2 under these conditions, a read or write of TH2 or TL2 may not be accurate. The RCAP2 registers may be read, but should not be written to, because a write might overlap a reload and cause write and / or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers. Table 5 shows commonly used baud rates and how they can be obtained from Timer 2.
If Timer 2 is being clocked internally , the baud rate is: Baud Rate + f OSC 65536 (RCAP2H, RCAP2L)
Summary Of Baud Rate Equations
Timer 2 is in baud rate generating mode. If Timer 2 is being clocked through pin T2(P1.0) the baud rate is: Baud Rate + Timer 2 Overflow Rate 16
Timer / Counter 2 Set-up
Except for the baud rate generator mode, the values given for T2CON do not include the setting of the TR2 bit. Therefore, bit TR2 must be set, separately, to turn the timer on. See Table 6 for set-up of Timer 2 as a timer. Also see Table 7 for set-up of Timer 2 as a counter.
Table 6. Timer 2 as a Timer
T2CON MODE 16-bit Auto-Reload 16-bit Capture Baud rate generator receive and transmit same baud rate Receive only Transmit only INTERNAL CONTROL (Note 1) 00H 01H 34H 24H 14H EXTERNAL CONTROL (Note 2) 08H 09H 36H 26H 16H
Table 7. Timer 2 as a Counter
TMOD MODE 16-bit Auto-Reload INTERNAL CONTROL (Note 1) 02H 03H EXTERNAL CONTROL (Note 2) 0AH 0BH
NOTES: 1. Capture / reload occurs only on timer / counter overflow. 2. Capture / reload occurs on timer / counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate generator mode.
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
Enhanced UART
Slave 1
1100 0000 1111 1110 1100 000X
Slave 1
Slave 2
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
Symbol FE SM0 SM1
REN TB8 RB8 Tl Rl
SU00043
Figure 7. SCON: Serial Port Control Register
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
START BIT
DATA BYTE
ONLY IN MODE 2, 3
STOP BIT
SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR) SM0 TO UART MODE CONTROL
SCON (98H)
SMOD1
SMOD0
PCON (87H)
SU01191
Figure 8. UART Framing Error Detection
SCON (98H)
RECEIVED ADDRESS D0 TO D7 PROGRAMMED ADDRESS COMPARATOR
SU00045
Figure 9. UART Multiprocessor Communication, Automatic Address Recognition
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
Interrupt Priority Structure
The 8XC51FA / FB / FC and 8XC51RA+ / RB+ / RC+ / RD+ have a 7-source four-level interrupt structure (see Table 8). The 80C52 / 54 / 58 and 80C32 only have a 6-source four-level interrupt structure because these devices do not have a PCA. There are 3 SFRs associated with the four-level interrupt. They are the IE, IP, and IPH. (See Figures 10, 11, and 12.) The IPH (Interrupt Priority High) register makes the four-level interrupt structure possible. The IPH is located at SFR address B7H. The structure of the IPH register and a description of its bits is shown in Figure 12. The function of the IPH SFR is simple and when combined with the IP SFR determines the priority of each interrupt. The priority of each interrupt is determined as shown in the following table: PRIORITY BITS IPH.x 0 0 1 1 IP.x 0 1 0 1 INTERRUPT PRIORITY LEVEL Level 0 (lowest priority) Level 1 Level 2 Level 3 (highest priority)
The priority scheme for servicing the interrupts is the same as that for the 80C51, except there are four interrupt levels rather than two as on the 80C51. An interrupt will be serviced as long as an interrupt of equal or higher priority is not already being serviced. If an interrupt of equal or higher level priority is being serviced, the new interrupt will wait until it is finished before being serviced. If a lower priority level interrupt is being serviced, it will be stopped and the new interrupt serviced. When the new interrupt is finished, the lower priority level interrupt that was stopped will be completed.
Table 8.
Interrupt Table
SOURCE
SU00840
Figure 10. IE Registers
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
7 IP (0B8H) -
7 IPH (B7H) -
6 PPCH
5 PT2H
3 PT1H
2 PX1H
1 PT0H
0 PX0H
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
Reduced EMI Mode
The AO bit (AUXR.0) in the AUXR register when set disables the ALE output.
be quickly toggled simply by executing an INC DPTR instruction without affecting the GF3 or LPEP bits.
Reduced EMI Mode
AUXR (8EH)
7 - 6 - 5 - 4 - 3 - 2 - 1 EXTRAM 0 AO DPH (83H) DPL (82H) DPS BIT0 AUXR1
DPTR1 DPTR0 EXTERNAL DATA MEMORY
AUXR.1 AUXR.0
EXTRAM AO
(RX+ only) Turns off ALE output.
SU00745A
Dual DPTR
Figure 13.
· New Register Name: AUXR1# · SFR Address: A2H · Reset Value: xxxx00x0B
DPTR Instructions The instructions that refer to DPTR refer to the data pointer that is currently selected using the AUXR1 / bit 0 register. The six instructions that use the DPTR are as follows: INC DPTR MOV DPTR, #data16 Increments the data pointer by 1 Loads the DPTR with a 16-bit constant Move code byte relative to DPTR to ACC Move external RAM (16-bit address) to ACC Move ACC to external RAM (16-bit address) Jump indirect relative to DPTR
MOV A, @ A+DPTR MOVX A, @ DPTR MOVX @ DPTR , A JMP @ A + DPTR
The DPS bit status should be saved by software when switching between DPTR0 and DPTR1. The GF3 bit is a general purpose user-defined flag. Note that bit 2 is not writable and is always read as a zero. This allows the DPS bit to
The data pointer can be accessed on a byte-by-byte basis by specifying the low or high byte in an instruction which accesses the SFRs. See application note AN458 for more details.
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
(8XC51FX and 8XC51RX+ ONLY) Programmable Counter Array (PCA) (8XC51FX and 8XC51RX+ only)
16 BITS MODULE 0 P1.3 / CEX0
MODULE 1 16 BITS PCA TIMER / COUNTER TIME BASE FOR PCA MODULES MODULE 3 MODULE FUNCTIONS: 16-BIT CAPTURE 16-BIT TIMER 16-BIT HIGH SPEED OUTPUT 8-BIT PWM WATCHDOG TIMER (MODULE 4 ONLY) MODULE 2
P1.4 / CEX1
P1.5 / CEX2
P1.6 / CEX3
MODULE 4
P1.7 / CEX4
SU00032
Figure 14. Programmable Counter Array (PCA)
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
(8XC51FX and 8XC51RX+ ONLY)
TO PCA MODULES
OSC / 4 CH TIMER 0 OVERFLOW EXTERNAL INPUT (P1.2 / ECI) 00 01 10 11 CL
OVERFLOW INTERRUPT
16-BIT UP COUNTER
DECODE
IDLE CIDL WDTE -- -- -- CPS1 CPS0 ECF CMOD (D9H)
CCON (D8H)
SU00033
Figure 15. PCA Timer / Counter
CF PCA TIMER / COUNTER
CCON (D8H)
MODULE 0 IE.6 EC MODULE 1 IE.7 EA TO INTERRUPT PRIORITY DECODER
MODULE 2
MODULE 3
MODULE 4
CMOD.0
CCAPMn.0
ECCFn
SU00034
Figure 16. PCA Interrupt System
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
(8XC51FX and 8XC51RX+ ONLY)
CIDL Bit: Symbol CIDL WDTE - CPS1 CPS0 Function 7
WDTE 6
CPS1 2
CPS0 1
SU00035
Figure 17. CMOD: PCA Counter Mode Register
PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but can only be cleared by software. PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA counter off. Not implemented, reserved for future use. PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
NOTE: User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
SU00036
Figure 18. CCON: PCA Counter Control Register
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
(8XC51FX and 8XC51RX+ ONLY)
NOTE: User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. SU00037
Figure 19. CCAPMn: PCA Modules Compare / Capture Registers - X X X X X X X X ECOMn 0 X X X 1 1 1 1 CAPPn 0 1 0 1 0 0 0 0 CAPNn 0 0 1 1 0 0 0 0 MATn 0 0 0 0 1 1 0 1 TOGn 0 0 0 0 0 1 0 X PWMn 0 0 0 0 0 0 1 0 ECCFn 0 X X X X X 0 X No operation 16-bit capture by a positive-edge trigger on CEXn 16-bit capture by a negative trigger on CEXn 16-bit capture by a transition on CEXn 16-bit Software Timer 16-bit High Speed Output 8-bit PWM Watchdog Timer MODULE FUNCTION
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
(8XC51FX and 8XC51RX+ ONLY)
CCON (D8H)
PCA INTERRUPT (TO CCFn) PCA TIMER / COUNTER CH CL
CAPTURE
CCAPnH
CCAPnL
ECOMn 0
CAPPn
CAPNn
MATn 0
TOGn 0
PWMn 0
ECCFn
SU00749
Figure 21. PCA Capture Mode
CF WRITE TO CCAPnH RESET
CCON (D8H)
WRITE TO CCAPnL 0 1 ENABLE
CCAPnH
CCAPnL
PCA INTERRUPT (TO CCFn)
16-BIT COMPARATOR
MATCH
PCA TIMER / COUNTER
ECOMn
CAPPn 0
CAPNn 0
TOGn 0
PWMn 0
ECCFn
SU00750
Figure 22. PCA Compare Mode
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
(8XC51FX and 8XC51RX+ ONLY)
CF WRITE TO CCAPnH RESET CCAPnH
CCON (D8H)
WRITE TO CCAPnL 0 1 ENABLE
CCAPnL
PCA INTERRUPT (TO CCFn)
MATCH 16-BIT COMPARATOR
TOGGLE CH CL CEXn
PCA TIMER / COUNTER
ECOMn
CAPPn 0
CAPNn 0
TOGn 1
PWMn 0
ECCFn
CCAPMn, n: 0.4 (DAH - DEH)
SU00751
Figure 23. PCA High Speed Output Mode
CCAPnH
ECOMn
CAPPn 0
CAPNn 0
MATn 0
TOGn 0
ECCFn 0
CCAPMn, n: 0.4 (DAH - DEH)
SU00752
Figure 24. PCA PWM Mode
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
(8XC51FX and 8XC51RX+ ONLY)
CIDL WRITE TO CCAP4H RESET
CMOD (D9H)
WRITE TO CCAP4L 0 1 ENABLE
CCAP4H
CCAP4L
MODULE 4
MATCH 16-BIT COMPARATOR RESET
PCA TIMER / COUNTER
ECOMn
CAPPn 0
CAPNn 0
MATn 1
TOGn X
PWMn 0
ECCFn X
CCAPM4 (DEH)
SU00832
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
(8XC51FX and 8XC51RX+ ONLY)
ORL CMOD, #40H
Module 4 in compare mode Write to low byte first Before PCA timer counts up to FFFF Hex, these compare values must be changed Set the WDTE bit to enable the watchdog timer without changing the other bits in CMOD
Main program goes here, but CALL WATCHDOG periodically. WATCHDOG: CLR EA Hold off interrupts MOV CCAP4L, #00 Next compare value is within MOV CCAP4H, CH 255 counts of the current PCA SETB EA timer value RET Figure 26. PCA Watchdog Timer Initialization Code
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
(8XC51RX+ ONLY) Expanded Data RAM Addressing (8XC51RX+ ONLY)
EXTRAM
NOTE: User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
SU01003
Figure 27. AUXR: Auxiliary Register (RX+ only)
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
(8XC51RX+ ONLY)
2FF (RD TO RD+)
HARDWARE WATCHDOG TIMER (ONE-TIME ENABLED WITH RESET-OUT FOR 89C51RC+ / RD+)
The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer reset (WDTRST) SFR. The WDT is disabled at reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator is running and there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output reset HIGH pulse at the RST-pin.
Using the WDT
1999 Apr 01
ERAM 256 BYTES
UPPER 128 BYTES INTERNAL RAM
SPECIAL FUNCTION REGISTER
EXTERNAL DATA MEMORY
LOWER 128 BYTES INTERNAL RAM 300 (RD+ only) 00 00 0100 0000
SU00834
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
ABSOLUTE MAXIMUM RATINGS1, 2, 3
PARAMETER Operating temperature under bias Storage temperature range Voltage on EA / VPP pin to VSS Voltage on any other pin to VSS Maximum IOL per I / O pin RATING 0 to +70 or -40 to +85 -65 to +150 0 to +13.0 -0.5 to +6.5 15 UNIT °C °C V V mA
Power dissipation (based on package heat transfer limitations, not device power consumption) 1.5 W NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
AC ELECTRICAL CHARACTERISTICS
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
DC ELECTRICAL CHARACTERISTICS
VIL VIH VIH1 VOL VOL1
Input low voltage Input high voltage (ports 0, 1, 2, 3, EA) Input high voltage, XTAL1, RST Output low voltage, ports 1, 2 8 Output low voltage, port 0, ALE, PSEN8, 7
Output high voltage, ports 1, 2, 3 voltage 1 2
VOH1 IIL ITL ILI ICC
Output high voltage (port 0 in external bus mode), ALE9, PSEN3 Logical 0 input current, ports 1, 2, 3 Logical 1-to-0 transition current, ports 1, 2, 36 Input leakage current, port 0 Power supply current (see Figure 36): Active mode @ 16MHz (all except 8XC51RD+) 87C51RD+ Idle mode @ 16MHz Power-down mode or clock stopped (see Figure 40 for f conditions) diti ) Internal reset pull-down resistor capacitance10
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
DC ELECTRICAL CHARACTERISTICS
RRST CIO
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
AC ELECTRICAL CHARACTERISTICS
VARIABLE CLOCK MIN 3.5 MAX 16 UNIT MHz ns ns ns 4tCLCL-100 tCLCL-30 3tCLCL-45 ns ns ns 3tCLCL-105 0 tCLCL-25 5tCLCL-105 10 6tCLCL-100 6tCLCL-100 ns ns ns ns ns ns ns 5tCLCL-165 0 2tCLCL-60 8tCLCL-150 9tCLCL-165 3tCLCL-50 4tCLCL-130 tCLCL-50 tCLCL-50 7tCLCL-150 3tCLCL+50 ns ns ns ns ns ns ns ns ns ns 0 tCLCL-40 20 20 tCLCL+40 tCLCL-tCLCX tCLCL-tCHCX 20 20 12tCLCL 10tCLCL-133 2tCLCL-117 0 ns ns ns ns ns ns ns ns ns ns
FIGURE 29 29 29 29 29 29 29 29 29 29 29 29 30, 31 30, 31 30, 31 30, 31 30, 31 30, 31 30, 31 30, 31 30, 31 30, 31 30, 31 31 30, 31 30, 31 33 33 33 33 32 32 32 32
PARAMETER Oscillator frequency5 Speed versions : 4 5 S ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data hold after WR Data valid to WR high RD low to address float RD or WR high to ALE high High time Low time Rise time Fall time Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge
2tCLCL-40 tCLCL-40 tCLCL-30
tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tQVWH tRLAZ tWHLH tCHCX tCLCX tCLCH tCHCL Shift Register tXLXL tQVXH tXHQX tXHDX
External Clock
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
AC ELECTRICAL CHARACTERISTICS
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
EXPLANATION OF THE AC SYMBOLS
tLHLL
tAVLL
tLLPL
tPLPH tLLIV tPLIV tPLAZ tPXIX
INSTR IN
tLLAX
tPXIZ
PORT 0
A0-A7
tAVIV
PORT 2 A0-A15 A8-A15
SU00006
Figure 29. External Program Memory Read Cycle
tWHLH
tLLDV tLLWL
tRLRH
tAVLL
PORT 0
tLLAX tRLAZ
A0-A7 FROM RI OR DPL
tRLDV tRHDX
DATA IN
tRHDZ
A0-A7 FROM PCL
INSTR IN
tAVWL tAVDV
PORT 2 P2.0-P2.7 OR A8-A15 FROM DPF A0-A15 FROM PCH
SU00025
Figure 30. External Data Memory Read Cycle
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
tWHLH
tLLWL
tWLWH
tAVLL
PORT 0
tLLAX
tQVWX tQVWH
tWHQX
A0-A7 FROM RI OR DPL
DATA OUT
A0-A7 FROM PCL
INSTR IN
tAVWL
PORT 2
P2.0-P2.7 OR A8-A15 FROM DPF
A0-A15 FROM PCH
SU00026
Figure 31. External Data Memory Write Cycle
INSTRUCTION ALE
tXLXL
CLOCK
tQVXH
OUTPUT DATA 0 WRITE TO SBUF
tXHQX
tXHDV
INPUT DATA VALID CLEAR RI VALID
tXHDX
SET TI VALID VALID VALID VALID VALID VALID
SET RI
SU00027
Figure 32. Shift Register Mode Timing
VCC-0.5 0.45V
0.7VCC 0.2VCC-0.1
tCHCL
tCLCX tCLCL
tCHCX tCLCH
SU00009
Figure 33. External Clock Drive
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
VCC-0.5
0.2VCC+0.9 VLOAD 0.2VCC-0.1
VLOAD+0.1V VLOAD-0.1V
TIMING REFERENCE POINTS
VOH-0.1V VOL+0.1V
0.45V
SU00717
SU00718
Figure 34. AC Testing Input / Output
Figure 35. Float Waveform
10 MAX IDLE MODE 5 TYP IDLE MODE 4 8 12 16 20 24 28 32 36
FREQ AT XTAL1 (MHz)
SU00837A
Figure 36. ICC vs. FREQ Valid only within frequency specifications of the device under test
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
VCC ICC VCC VCC P0 EA (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS VCC RST P0 EA VCC
VCC ICC
SU00719
SU00720
Figure 37. ICC Test Condition, Active Mode All other pins are disconnected
Figure 38. ICC Test Condition, Idle Mode All other pins are disconnected
VCC-0.5 0.45V
0.7VCC 0.2VCC-0.1
tCHCL
tCLCX tCLCL
tCHCX tCLCH
SU00009
VCC ICC VCC RST P0 EA (NC) XTAL2 XTAL1 VSS VCC
SU00016
1999 Apr 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 8K-64K / 256-1K OTP / ROM / ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz)
8XC52 / 54 / 58 / 80C32 8XC51FA / FB / FC / 80C51FA 8XC51RA+ / RB+ / RC+ / RD+ / 80C51RA+
EPROM CHARACTERISTICS
All these devices can be programmed by using a modified Improved Quick-Pulse Programming algorithm. It differs from older methods in the value used for VPP (programming supply voltage) and in the width and number of the ALE / PROG pulses. The family contains two signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as being manufactured by Philips. Table 9 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the security bits. The circuit configuration and waveforms for quick-pulse programming are shown in Figures 41 and 42. Figure 43 shows the circuit configuration for normal program memory verification.
Quick-Pulse Programming