Precision JFET-Input Operational Amplifiers OP15/OP17 ADI-JFET in

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Precision JFET-Input Operational Amplifiers OP15/OP17 ADI-JFET in

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FEATURES Significant Performance Advantages over LF155 LF157 Devices Input Offset Voltages: Input Offset Voltage Drift: Minimum Slew Rate Guaranteed Models Temperature-Compensated Input Bias Currents Bias Current Specified Warmed-Up Over Temperature Internal Compensation Input Noise Current: 0.01 pA/÷Hz High Common-Mode Rejection Ratio: Models with MIL-STD Processing Available OP15 Speed with Dissipation: Wide Bandwidth: High Slew Rate: Fast Settling ±0.1%: 1,200 OP17 Highest Slew Rate: Fastest Settling ±0.1%: Highest Gain Bandwidth Product (AVCL Min): Guaranteed Input Bias Current
Precision JFET-Input Operational Amplifiers OP15/OP17
ADI-JFET input series devices offer clear advantages over industry-generic devices superior both cost performance many dielectrically-isolated hybrid amps. devices offer offset voltages with TCVOS guaranteed mV/C. unique input bias cancellation circuit reduces factor over conventional designs. addition specifies with devices warmed operating ambient. These devices were designed provide real precision performance along with high speed. Although they nulled, design objective provide offset-voltage without nulling. Systems generally become more cost effective number trim circuits decreased. achieves this performance improved bipolar compatible JFET process coupled with chip, zener-zap offset trimming. OP15 provides excellent combinations high speed input offset voltage. addition, OP15 offers speed 156A with power dissipation 155A. combination input offset voltage slew rate V/ms, settling time 1,200 0.1% makes OP15 both precision speed. additional features supply current coupled with input bias current makes OP15 ideal wide range applications. OP17 slew rate V/ms best choice applications requiring high closed-loop gain with high speed. OP42 datasheet unity gain applications OP215 datasheet dual configuration OP15.
NULL
NULL
*R7, ELECTRONICALLY ADJUSTED CHIP MINIMUM OFFSET VOLTAGE.
NONINVERTING INPUT -INV INPUT
OUTPUT
7.4pF
3.6k
3.6k
Figure Simplified Schematic
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2002
OP15/OP17-SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
unless otherwise noted)
OP15A, OP15E OP17A, OP17E 1012 OP15F OP17F 1012 12.7 10.5 0.01 0.01 0.01 0.01 0.01 0.01 10.3 OP15G OP17G 1012 12.7
Parameter Input Offset Voltage Input Offset Current OP15 OP17 Input Bias Current OP15 OP17 Input Resistance Large-Signal Voltage Gain Output Voltage Swing Supply Current Slew Rate2 Gain Bandwidth3 Product Closed-Loop Bandwidth Settling Time OP15
Symbol
Conditions 25C1 Device Operating 25C1 Device Operating
Unit V/mV V/ms V/ms mV/V mV/V nV/÷Hz nV/÷Hz pA/÷Hz pA/÷Hz
25C1 Device Operating 25C1 Device Operating CLBW 0.01% 0.05% 0.10% 0.01% 0.05% 0.10% CMRR PSRR 10.5 10.3 10.5 OP15 OP17 AVCL OP15 AVCL OP17 OP15 OP17 AVCL OP15 AVCL OP17
12.7
OP17
Input Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio Input Noise Voltage Density Input Noise Current Density Input Capacitance
NOTES Input bias current specified different conditions. specification with junction ambient temperature; device operating specification with device operating warmed-up condition ambient. warmed-up bias current value correlated junction temperature value curves versus versus bias current compensation circuit which gives improved bias current over standard JFET input amps. measured Settling time defined here unity gain inverter connection using resistors. time required error voltage (the voltages inverting input amplifier) settle within specified percent final value from time step input applied inverter. settling time test circuit. Sample tested. Settling time defined here connection with time required error voltage (the voltage inverting input amplifier) settle within 0.01% final value from time step input applied inverter. settling time test circuit.
REV.
OP15/OP17 Electrical Characteristics unless otherwise noted.)
Parameter Input Offset Voltage Average Input Offset Voltage Drift Without External Trim With External Trim Input Offset Current2 OP17 Input Bias Current2 OP17 Input Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage Swing
Symbol TCVOS TCVOS CMRR PSRR
Conditions
Units mV/C mV/C
125C 125C, device operating 125C 125C, device operating 10.4 10.4
mV/V V/mV
NOTES Sample tested. Input bias current specified different conditions. specification with junction ambient temperature; device operating specification with device operating warmed-up condition ambient. warmed-up bias current value correlated junction temperature value curves versus versus bias current compensation circuit which gives improved bias current over standard JFET input amps. measured
ELECTRICAL CHARACTERISTICS unless otherwise noted)
Parameter Input Offset Voltage Symbol Conditions
grades, grades
OP15F/OP17F 0.55 OP15G/OP17G
OP15E/OP17E 0.75
Unit
Average Input Offset Voltage Drift1 Without External Trim TCVOS With External Trim TCVOSn Input Offset Current2 OP15 OP17 Input Bias Current2 OP15 OP17 Input Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage Swing CMRR PSRR
70C, Device Operating 70C, Device Operating 70C, Device Operating 70C, Device Operating 10.4 10.4 10.25
0.04 0.06 0.04 0.07 0.10 0.13 0.10 0.15
0.30 0.55 0.30 0.70 0.40 0.75 0.40 0.90 10.4
0.06 0.08 0.06 0.10 0.12 0.16 0.12 0.20
0.45 0.80 0.45 0.60 0.60 10.25
0.08 0.10 0.08 0.15 0.14 0.19 0.14 0.25
0.85 0.85 0.80 0.80
mV/C mV/C
mV/V mV/V V/mV
NOTES Sample tested. Input bias current specified different conditions. specification with junction ambient temperature; device operating specification with device operating warmed-up condition ambient. warmed-up bias current value correlated junction temperature value curves versus versus bias current compensation circuit which gives improved bias current over standard JFET input amps. measured
REV.
OP15/OP17-SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Devices Except (Packaged) Grades (Packaged) Grades Operating Temperature Grade -55C +125C Grades Grade -40C +85C Maximum Junction Temperature 150C Differential Input Voltage Devices Except Grades Grades Input Voltage2 Devices Except Grades Grades Input Voltage OP15E, OP15F OP15G OP17A, OP17E, OP17F OP17G Output Short-Circuit Duration Indefinite Storage Temperature Range -65C +150C Lead Temperature Range (Soldering, sec) 300C
NOTES *Absolute Maximum Ratings apply packaged parts, unless otherwise noted.
Package Type 8-Lead Hermetic 8-Lead TO-99
Unit
specified worst-case mounting conditions, i.e., specified device socket CERDIP PDIP packages; specified device soldered printed circuit board packages.
+20V
-20V
Figure Burn-In Circuit
8-Lead CERDIP (Z-Suffix)
8-Lead SOIC (S-Suffix)
8-Lead TO-99 (J-Suffix)
ORDERING GUIDE
(mV)
Package Options TO-99 OP17EJ OP15FJ* OP17FJ OP15GJ* CERDIP OP15EZ OP17EZ OP15FZ* OP17FZ OP15GZ* OP17GZ OP15GS* SOIC
Operating Temperature Range XIND
military processed devices, please refer Standard Microcircuit Drawing (SMD) available Part Number 5962-8954201GA* 5962-8954201PA* 5962-8954301GA* 5962-8954301PA* Equivalent OP15AJMDA OP15AZMDA OP16AJMDA OP16AZMDA
*Not recommended designs. Obsolete April 2002.
REV.
Typical Performance Characteristics -OP15/OP17
PEAK-TO-PEAK OUTPUT SWING
WARMED-UP FREE
+125 OUTPUT LOAD RESISTANCE 100k
INPUT BIAS CURRENT
UNDERCANCELLED +16pA PERFECTLY CANCELLED UNDERCANCELLED -16pA
INPUT COMMON-MODE VOLTAGE
Maximum Output Swing Load Performance
Input Bias Current Common-Mode Voltage
COMMON-MODE INPUT VOLTAGE RANGE
OPEN-LOOP VOLTAGE GAIN
500k 400k 300k 200k
100k
POSITIVE FROM -125 CHANGE CMVR 0.2V NEGATIVE
SUPPLY VOLTAGE
SUPPLY VOLTAGE
Common-Mode Input Voltage Range Supply Voltage
Open-Loop Voltage Gain Supply Voltage
100Hz 10kHz 10Hz 10kHz AMPLIFIER NOISE JOHNSON RESISTOR NOISE AMPLIFIER NOISE MEASURED WITH SOURCE RESISTOR
INPUT NOISE VOLTAGE
PEAK-TO-PEAK OUTPUT SWING
0.01 100k
100M SOURCE RESISTANCE
SUPPLY VOLTAGE
Voltage Noise Source Resistance
Output Voltage Swing Supply Voltage
REV.
OP15/OP17
4.0mA CURVES 2.5mA CURVES
INPUT BIAS CURRENT
NULLED OFFSET VOLTAGE DRIFT
155A OP15A 100p 155A
TYPICAL DRIFT BAND
OP15
100k RP-TRIMMING POTENTIOMETER VALUE
TIME AFTER POWER APPLIED
Nulled Offset Voltage Drift Potentiometer Size
OP15 Bias Current Time Free
156A/157A
INPUT BIAS CURRENT
OFFSET VOLTAGE
156A/157A 100p OP17A 6.7mA CURVES 5.0mA CURVES
OP17A TIME AFTER POWER APPLIED
TEMPERATURE
Offset Voltage Drift Temperature Representative Units
OP17 Bias Current Time Free
100n
100n UNITS WARMED
INPUT BIAS CURRENT
155A
155A
INPUT BIAS CURRENT
155A OP15A OP15A
155A OP15A MAXP
OP15
100p
100p
AMBIENT TEMPERATURE
AMBIENT TEMPERATURE
Input Bias Current Ambient Temperature (Units Warmed Free Air)
OP15 Input Bias Current Ambient Temperature (Units Warmed Free Air)
REV.
OP15/OP17
100n 156A/157A OP17A
VOLTAGE 5V/DIV
INPUT BIAS CURRENT
156A/157A
OP17A 100p
TIME 500ns/DIV
AMBIENT TEMPERATURE
OP17 Input Bias Current Ambient Temperature (Units Warmed Free Air)
OP15 Large Signal Transient Response
SUPPLY CURRENT
VOLTAGE 20mV/DIV
SUPPLY VOLTAGE
TIME 100ns/DIV
OP15 Supply Current Supply Voltage
OP15 Small Signal Transient Response
SUPPLY CURRENT
OUTPUT VOLTAGE SWING FROM
10mV
10mV SUPPLY VOLTAGE
SUPPLY VOLTAGE
OP17 Supply Current Supply Voltage
OP15 Settling Time
REV.
OP15/OP17
PHASE MARGIN
VOLTAGE GAIN
PHASE SHIFT Degrees
PEAK-TO-PEAK OUTPUT SWING
100k
FREQUENCY
100M
FREQUENCY
OP15 Closed-Loop Bandwidth Phase Frequency
OP15 Maximum Output Swing Frequency
BANDWIDTH VARIATION FROM
SLEW RATE
BANDWIDTH
NEGATIVE
CLOSED-LOOP BANDWIDTH
GAIN BANDWIDTH PRODUCT
POSITIVE
TEMPERATURE
AMBIENT TEMPERATURE
OP15 Bandwidth Temperature
OP15 Slew Rate Temperature
COMMON-MODE REJECTION RATIO
OPEN-LOOP VOLTAGE GAIN
100k FREQUENCY
100M
100k FREQUENCY
100M
OP15 Open-Loop Gain Frequency
OP15 Common-Mode Rejection Ratio Frequency
REV.
OP15/OP17
POWER SUPPLY REJECTION RATIO
POSITIVE SUPPLY NEGATIVE SUPPLY
VOLTAGE 5V/DIV
100k FREQUENCY
TIME 200ns/DIV
OP15 Power Supply Rejection Ratio Frequency
OP17 Large Signal Transient Response
OUTPUT IMPEDANCE
VOLTAGE 20mV/DIV
100k FREQUENCY
TIME 100ns/DIV
OP15 Output Impedance Frequency
OP17 Small Signal Transient Response
OUTPUT VOLTAGE SWING FROM
VOLTAGE NOISE DENSITY
10mV
CORNER FREQUENCY
10mV
100k FREQUENCY
SUPPLY VOLTAGE
OP15 Voltage Noise Density Frequency
OP17 Settling Time
REV.
OP15/OP17
POWER SUPPLY REJECTION RATIO
POSITIVE SUPPLY
PEAK-TO-PEAK OUTPUT SWING
NEGATIVE SUPPLY
100k
FREQUENCY
100k FREQUENCY
OP17 Maximum Output Swing Frequency
OP17 Power Supply Rejection Ratio Frequency
NEGATIVE
SLEW RATE
OUTPUT IMPEDANCE
POSITIVE
AMBIENT TEMPERATURE
100k FREQUENCY
OP17 Slew Rate Temperature
OP17 Output Impedance Frequency
COMMON-MODE REJECTION RATIO
VOLTAGE NOISE DENSITY
CORNER FREQUENCY
100k FREQUENCY
100M
100k FREQUENCY
OP17 Common-Mode Rejection Ration Frequency
OP17 Voltage Noise Frequency
-10-
REV.
OP15/OP17
TEST CIRCUITS
0.1% +15V
100k
0.1% -15V
0.1%
OP17
2N4416 100pF
VOUT
SUMMING NODE
NOTE: TRIMMED WITH POTENTIOMETERS RANGING FROM MOST UNITS TCVOS WILL MINIMIZED WHEN ADJUSTED WITH 100k POTENTIOMETER
0.1%
SCOPE
2N4416
+15V
Figure Input Offset Voltage Nulling
0.1% +15V 0.1% -15V SUMMING NODE 0.1% 0.1%
Figure OP17 Settling Time Test Circuit
APPLICATION INFORMATION Dynamic Operating Considerations
2N4416 100pF
OP15
VOUT
with most amplifiers, care should taken with lead dress, component placement supply decoupling order ensure stability. example, resistors from output input should placed with body close input minimize "pick-up" maximize frequency feedback pole minimizing capacitance input ground. feedback pole created when feedback around amplifier resistive. parallel resistance capacitance from input device (usually inverting input) ground frequency this pole. many instances frequency this pole much greater than expected, frequency close-loop gain, consequently there negligible effect stability margin. However, feedback pole less than approximately times expected frequency, lead capacitor should placed from output negative input amp. value added capacitor should such that time-constant this capacitor resistance parallels greater than, equal original feedback pole time constant.
30pF
SCOPE
2N4416
+15V
Figure OP15 Settling Time Test Circuit
DIGITAL INPUTS +10V
+15V
RREF
VREF+
VREF-
DAC08E
OP15F
+15V
-15V
-15V
Figure Current-to-Voltage Amplifier Output
REV.
-11-
OP15/OP17
OUTLINE DIMENSIONS
Dimensions shown millimeters (inches).
8-Lead Ceramic Glass Hermetic Seal [CERDIP] (Q-8)
0.13 (0.0051) 1.40 (0.0551)
8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8)
5.00 (0.1968) 4.80 (0.1890)
7.87 (0.3089) 5.59 (0.2201)
4.00 (0.1574) 3.80 (0.1497)
6.20 (0.2440) 5.80 (0.2284)
2.54 (0.1000) 10.29 (0.4051) 5.08 (0.2000) 5.08 (0.2000) 3.18 (0.1252) 0.58 (0.0228) 0.36 (0.0142) 1.52 (0.0600) 0.38 (0.0150) 3.81 (0.1500) SEATING 1.78 (0.0701) PLANE 0.76 (0.0299) 0.38 (0.0150) 0.20 (0.0079) 8.13 (0.3201) 7.37 (0.2902)
1.27 (0.0500) 0.25 (0.0098) 0.10 (0.0040) COPLANARITY SEATING 0.10 PLANE
1.75 (0.0688) 1.35 (0.0532) 0.25 (0.0098) 0.19 (0.0075)
0.50 (0.0196) 0.25 (0.0099)
0.51 (0.0201) 0.33 (0.0130)
1.27 (0.0500) 0.41 (0.0160)
CONTROLLING DIMENSIONS MILLIMETERS; INCH DIMENSIONS PARENTHESES) ROUNDED-OFF MILLIMETER EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN
CONTROLLING DIMENSIONS MILLIMETERS; INCH DIMENSIONS PARENTHESES) ROUNDED-OFF MILLIMETER EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN COMPLIANT JEDEC STANDARDS MS-012AA
8-Lead Metal [TO-99] (H-08)
REFERENCE PLANE 4.70 (0.1850) 4.19 (0.1650) 12.70 (0.5000) 6.35 (0.2500) 1.27 (0.0500) 9.40 (0.3700) 8.51 (0.3350) 8.51 (0.3350) 7.75 (0.3050) 5.08 (0.2000) 0.48 (0.0190) 0.41 (0.0160) 0.53 (0.0210) 0.41 (0.0160) BASE SEATING PLANE 2.54 (0.1000) 0.86 (0.0340) 0.71 (0.0280) 1.14 (0.0450) 0.69 (0.0270) 2.54 (0.1000) 4.06 (0.1600) 3.56 (0.1400)
1.02 (0.0400) 1.02 (0.0400) 0.25 (0.0100)
CONTROLLING DIMENSIONS MILLIMETERS; INCH DIMENSIONS PARENTHESES) ROUNDED-OFF MILLIMETER EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN
Revision History
Location
COMPLIANT JEDEC STANDARDS MO-002AK
9/02-Data Sheet changed from REV. REV.
Deleted OP16 .Universal Edits FEATURES Edits GENERAL DESCRIPTION Edits SPECIFICATIONS Edits ORDERING GUIDE Edits ABSOLUTE MAXIMUM RATINGS Edits DICE CHARACTERISTICS Edits WAFER TEST LIMITS Deleted TPCs 11-12 Updated OUTLINE DIMENSIONS -12- REV.
PRINTED U.S.A.
Page
C02789-0-9/02(A)

Precision JFET-Input Operational Amplifiers OP15/OP17 ADI-JFET in

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