128M-BIT Voltage, Serial Mask Memory with 50MHz Interface 128Mbit

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128M-BIT Voltage, Serial Mask Memory with 50MHz Interface 128Mbit

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MX23L12854
128M-BIT Voltage, Serial Mask Memory with 50MHz Interface
128Mbit Mask 3.6V Single Supply Voltage Compatible Serial Interface 50MHz Clock Rate (maximum)
DESCRIPTION
MX23L12854 128Mbit (16M Serial Mask accessed high speed SPI-compatible bus.
CONFIGURATIONS 16-PIN (300 mil)
HOLD#
DESCRIPTION
SYMBOL HOLD# DESCRIPTION Serial Clock Serial Data Input Serial Data Output Chip Select Hold Supply Voltage Ground
Note: NC=No Connection page (onwards) package dimensions, identify pin-1.
ORDER INFORMATION
Part MX23L12854MC-20G Speed 20ns Package 16-SOP Remark Pb-free
P/N: PM1141
REV. 1.1, MAY. 2005
MX23L12854
MEMORY ORGANIZATION
memory organized bytes bits each)
BLOCK DIAGRAM
HOLD# Control Logic
Shift Register
Address Register Counter
Byte Data Buffer
Decoder
Size read-only memory area
Decoder
P/N: PM1141
REV. 1.1, MAY. 2005
MX23L12854
SIGNAL DESCRIPTION
Serial Data Output (Q). This output signal used transfer data serially device. Data shifted falling edge Serial Clock (C). Serial Data Input (D). This input signal used transfer data serially into device. receives instructions, addresses, data programmed. Values latched rising edge Serial Clock (C). Serial Clock (C). This input signal provides timing serial interface. Instructions, addresses, data present Serial Data Input latched rising edge Serial Clock (C). Data Serial Data Output changes after falling edge Serial Clock (C). Chip Select (S#). When this input signal High, device deselected. Driving Chip Select (S#) enables device, placing active power mode. After Power-up, falling edge Chip Select (S#) required prior start instruction. Hold (HOLD#). Hold (HOLD#) signal used pause serial communications with device without deselecting device. During Hold condition, Serial Data Output high impedance, Serial Data Input Serial Clock Don't Care. start Hold condition, device must selected, with Chip Select (S#) driven Low.
P/N: PM1141
REV. 1.1, MAY. 2005
MX23L12854
MODES
These devices driven microcontroller with peripheral running either following modes: CPOL=0, CPHA=0 CPOL=1, CPHA=1 these modes, input data latched rising edge Serial Clock (C), output data available from falling edge Serial Clock (C). difference between modes, shown Figure clock polarity when master Stand-by mode transferring data: remains (CPOL=0, CPHA=0) remains (CPOL=1, CPHA=1)
Figure Master Memory Devices
Interface with (CPOL, CPHA) Master (ST6, ST7, ST9, ST10, Others) Memory Device HOLD# HOLD# HOLD# Memory Device Memory Device
Note: Hold (HOLD#) signals should driven, High appropriate.
Figure Modes Supported
CPOL
CPHA
P/N: PM1141
REV. 1.1, MAY. 2005
MX23L12854
OPERATING Active Power, Stand-by Power When Chip Select (S#) Low, device enabled, Active Power mode. When Chip Select (S#) High, device disabled, could remain Active Power mode until internal cycles have completed. device then goes Stand-by Power mode. device consumption drops ICC1 Hold condition starts falling edge Hold (HOLD) signal, provided that this coincides with Serial Clock being shown Figure Hold condition ends rising edge Hold (HOLD#) signal, provided that this coincides with Serial Clock being Low. falling edge does coincide with Serial Clock being Low, Hold condition starts after Serial Clock next goes Low. Similarly, rising edge does coincide with Serial Clock being Low, Hold condition ends after Serial Clock next goes Low. (This shown Figure During Hold condition, Serial Data Output high impedance, Serial Data Input Serial Clock Don't Care. Normally, device kept selected, with Chip Select (S#) driven Low, whole duration Hold condition. This ensure that state internal logic remains unchanged from moment entering Hold condition. Chip Select (S#) goes High while device Hold condition, this effect resetting internal logic device. restart communication with device, necessary drive Hold (HOLD#) High, then drive Chip Select (S#) Low. This prevents device from going back Hold condition.
Protection Modes
environments where non-volatile memory devices used very noisy. device operate correctly presence excessive noise. help combat this, MX23L12854 boasts following data protection mechanisms: Power-On Reset internal timer (tPUW) provide protection against inadvertant changes while power supply outside operating specification.
Hold Condition
Hold (HOLD#) signal used pause serial communications with device without resetting clocking sequence. enter Hold condition, device must selected, with Chip Select (S#) Low.
Figure Hold Condition Activation (for data output only)
HOLD#
HOLD#
P/N: PM1141
REV. 1.1, MAY. 2005
MX23L12854
INSTRUCTIONS
instructions, addresses data shifted device, most significant first. Serial Data Input sampled first rising edge Serial Clock after Chip Select (S#) driven Low. Then, one-byte instruction code must shifted device, most significant first, Serial Data Input (D), each being latched rising edges Serial Clock (C). instruction listed Table Every instruction sequence starts with one-byte instruction code. Depending instruction, this might followed address bytes, data bytes, both none. case Read Data Bytes (READ), Read Data Bytes Higher Speed (Fast_Read), shifted-in instruction sequence followed data-out sequence. Chip Select (S#) driven High after data-out sequence being shifted out.
Table Instruction
Instruction READ FAST_READ Description Read Data Bytes Read Data Bytes Higher Speed One-byte Instruction Code 0000 0011 0000 1011 Address Bytes Dummy Bytes Data Bytes
P/N: PM1141
REV. 1.1, MAY. 2005
MX23L12854
Figure Read Data Bytes (READ) Instruction Sequence Data-Out Sequence
Instruction 24-Bit Address
High Impedance
Data Data
Read Data Bytes (READ) device first selected driving Chip Select (S#) Low. instruction code Read Data Bytes (READ) instruction followed 3-byte address (A23-A0), each being latched-in during rising edge Serial Clock (C). Then memory contents, that address, shifted Serial Data Output (Q), each being shifted out, maximum frequency during falling edge Serial Clock (C). instruction sequence shown Figure first byte addressed location. address automatically incremented next higher address after each byte data shifted out. whole memory can, therefore, read with single Read Data Bytes (READ) instruction.When highest address reached, address counter rolls over 000000h, allowing read sequence continued indefinitely. Read Data Bytes (READ) instruction terminated driving Chip Select (S#) High. Chip Select (S#) driven High time during data output.
P/N: PM1141
REV. 1.1, MAY. 2005
MX23L12854
Figure Read Data Bytes Higher Speed (FAST_READ) Instruction Sequence Data-Out Sequence
Instruction ADDRESS
High Impedance
Dummy Byte
DATA DATA
Read Data Bytes Higher Speed (FAST_READ) device first selected driving Chip Select (S#) Low. instruction code Read Data Bytes Higher Speed (FAST_READ) instruction followed 3byte address (A23-A0) dummy byte, each being latched-in during rising edge Serial Clock (C). Then memory contents, that address, shifted Serial Data Output (Q), each being shifted out, maximum frequency during falling edge Serial Clock (C). instruction sequence shown Figure first byte addressed location. address
automatically incremented next higher address after each byte data shifted out. whole memory can, therefore, read with single Read Data Bytes Higher Speed (FAST_READ) instruction. When highest address reached, address counter rolls over 000000h, allowing read sequence continued indefinitely. Read Data Bytes Higher Speed (FAST_READ) instruction terminated driving Chip Select (S#) High. Chip Select (S#) driven High time during data output.
P/N: PM1141
REV. 1.1, MAY. 2005
MX23L12854
POWER-UP POWER-DOWN
Power-up Power-down, device must selected (that Chip Select (S#) must follow voltage applied until reaches correct value: VCC(min) Power-up, then further delay tVSL Power-down Usually simple pull-up resistor Chip Select (S#) used insure safe proper Power-up Powerdown. avoid data corruption inadvertent write operations during power Power Reset (POR) circuit included. logic inside device held reset while less than threshold value, operations disabled, device does respond instruction. These values specified Table delay, tVSL, elapsed, after risen above (min), device selected READ instructions even tPUW delay fully elapsed. Power-up, device following state: device Standby mode. Normal precautions must taken supply rail decoupling, stablise feed. Each device system should have rail decoupled suitable capacitor close package pins. (Generally, this capacitor order 0.1uF). Power-down, when drops from operating voltage, below threshold value, operations disabled device does respond instruction.
Figure Power-up Timing
VCC(max) Chip Selection Allowed VCC(min) Reset State Device tPUW tVSL Read Access allowed Device fully accessible
time
P/N: PM1141
REV. 1.1, MAY. 2005
MX23L12854
Table Power-Up Timing
Symbol tVSL1 VCC(min) Parameter Min. Max. Unit
Note: These parameters characterized only.
MAXIMUM RATING
Stressing device above rating listed the"Absolute Maximum Ratings" table cause permanent damage device. These stress ratings only operation device these other conditions above those indicated Operating sections this specification implied. Exposure Absolute Maximum Rating conditions extended periods affect device reliability.
Table Absolute Maximum Ratings
Symbol TSTG TLEAD VESD Storage Temperature Lead Temperature during Soldering Input Output Voltage (with respect Ground) Supply Voltage Electrostatic Discharge Voltage (Human Body model) 2000 Parameter Min. Max. 2000 Unit
Note: Compliant with ECOPACK 7191395 specifiication lead-free soldering processes exceeding 250°C more than seconds, peaking 260°C JEDEC JESD22-A114A (C1=100 R1=1500 R2=500
P/N: PM1141
REV. 1.1, MAY. 2005
MX23L12854
PARAMETERS
This section summarizes operating mea-surement conditions, characteristics device. parameters Characteristic tables that follow derived from tests performed under Measurement Conditions summarized relevant tables. Designers should check that operating conditions their circuit match measurement conditions when relying quoted parameters.
Table Operating Conditions
Symbol Supply Voltage Ambient Operating Temperature Parameter Min. Max. Unit
Table Measurement Conditions
Symbol Load Capacitance Input Rise Fall Times Input Pulse Voltages Input Timing Reference Voltages Output Timing Reference Voltages
Note: Output Hi-Z defined point where data longer driven.
Parameter
Min.
Max.
Unit
0.2VCC 0.8VCC 0.3VCC 0.7VCC
Figure Measurement Waveform
Input Levels 0.8VCC Input Output Timing Reference Levels 0.7VCC 0.5VCC 0.3VCC
0.2VCC
Table Capacitance
Symbol COUT Parameter Output Capacitance Input Capacitance (other pins) Test Condition VOUT Min. Max. Unit
Note: Sampled only, 100% tested, TA=25°C frequency MHz.
P/N: PM1141
REV. 1.1, MAY. 2005
MX23L12854
Table Characteristics
Symbol ICC1 Parameter Input Leakage Current Output Leakage Current Standby Current VCC, 0.1VCC 0.9.VCC 50MHz, open ICC2 Operating Current (READ) 0.1VCC 0.9.VCC 20MHz, open Input Voltage Input High Voltage Output Voltage Output High Voltage 1.6mA -100 VCC- 0.7VCC 0.3VCC VCC+0.4 Test Condition addition those Table Min. Max. Unit
P/N: PM1141
REV. 1.1, MAY. 2005
MX23L12854
Table Characteristics
Test conditions specified Table Table Symbol tCLCH tCHCL tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tSHSL tSHQZ tCLQV tCLQX tHLCH tCHHH tHHCH tCHHL tHHQX tHLQZ tCSH tDIS tDSU tCSS tCLH tCLL Alt. Parameter Clock Frequency following instructions: FAST_READ Clock Frequency READ instructions Clock High Time Clock Time Clock Rise Time3 (peak peak) Clock Fall Time3 (peak peak) Active Setup Time (relative Active Hold Time (relative Data Setup Time Data Hold Time Active Hold Time (relative Active Setup Time (relative Deselect Time Output Disable Time Clock Output Valid Output Hold Time HOLD# Setup Time (relative HOLD# Hold Time (relative HOLD Setup Time (relative HOLD Hold Time (relative HOLD Output Low-Z HOLD# Output High-Z Min. D.C. D.C. Typ. Max. Unit V/ns V/ns
Note: must greater than equal Value guaranteed characterization, 100% tested production. Expressed slew-rate.
P/N: PM1141
REV. 1.1, MAY. 2005
MX23L12854
Figure Serial Input Timing
tSHSL tCHSL tDVCH tCHDX tCLCH tCHCL tSLCH tCHSH tSHCH
High Impedance
Figure Hold Timing
tHLCH tCHHL tCHHH tHLQZ tHHQX tHHCH
HOLD#
P/N: PM1141
REV. 1.1, MAY. 2005
MX23L12854
Figure Output Timing
tCLQV tCLQX tQLQH tQHQL
ADDR.LSB
tCLQV tCLQX
tSHQZ
P/N: PM1141
REV. 1.1, MAY. 2005
MX23L12854
PACKAGE INFORMATION
P/N: PM1141
REV. 1.1, MAY. 2005
MX23L12854
REVISION HISTORY
Revision Description Added "Order Information" Changed from "2.7V 3.6V" "3.0V 3.6V" Page P1,11 Date APR/06/2005 MAY/04/2005
P/N: PM1141
REV. 1.1, MAY. 2005
MX23L12854
MACRONIX INTERNATIONAL CO., LTD.
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128M-BIT Voltage, Serial Mask Memory with 50MHz Interface 128Mbit

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