128M-BIT NAND INTERFACE XtraROMWord organization (16,777,216 1,048,576
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MX23J12840
128M-BIT NAND INTERFACE XtraROMWord organization (16,777,216 1,048,576Note) bits Page size (512 16Note) bits Block size (16,384 512Note) bits Note Underlined parts redundancy fixed FFH. Operation mode READ mode (1), READ mode (2), READ mode (3), RESET Operating supply voltage 2.7~3.6V Access Time Memory cell array starting address (MAX.) Read cycle time (MAX.) access time (MAX.) Operating supply current During read (MAX.) cycle operation) During standby (CMOS) (MAX.) Package Type 48-pin TSOP(I) (12mmx20mm) XtraROM: factory pre-programmed with Macronix NBittechnology, supporting short Process 0.15um
CONFIGURATIONS TSOP
I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
DESCRIPTION
SYMBOL I/O0~I/O7 NAME Address Input/Command Inputs/ Data Outputs Command Latch Enable Address Latch Enable Write Enable Read Enable Chip Enable READY, /BUSY Supply Voltage Connection Ground
MX23J12840 (Normal Type)
ORDER INFORMATION
Part MX23J12840TC-50G MX23J12840TC-50 MX23J12840TI-50G Package TSOP (Pb-free, RoHS) TSOP TSOP (Pb-free, RoHS) Grade Commercial Commercial Industrial
P/N:PM1097
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MX23J12840
BLOCK DIAGRAM
Data Register Circuit
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
Input/Output Buffer
Sense Amplifier Address Register Y-Selector Command Register
Control Logic
X-Decoder
Memory Cell Matrix
READ Contorol Circuit
READY/BUSY Control Circuit
(Open-drain)
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MX23J12840
MEMORY
Page=528 Bytes Block Pages 32,765 32,766 32,767 Bytes (Main memory)
1,024 Blocks =32,768 Pages
Bytes (Redundancy)
start address (SA) during read operation specified divided into three areas using three types read commands. read mode (1), start address (SA) area (A). read mode (2), start address (SA) area (B). read mode (3), start address (SA) area (C).
page consists total bytes broken down into bytes (main memory) bytes (redundancy). block consists pages.
Caution data area redundancy, which programmable fixed FFH.
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Operation Modes
Command input, address input, serial read performed from pins, respective statuses controlled CLE, ALE, signals.
Command input cycle Address input cycle Serial read cycle
I/O0~ I/O7
Busy
Operation mode
Mode Command input cycle Address input cycle Serial read cycle
Operation mode during serial read
Mode Data output Output Hi-Z Standby Remark
P/N:PM1097 REV. 1.2, OCT. 2005
I/O0 I/O7 Data output Hi-Z Hi-Z
MX23J12840
Operation Commands
following operation settings possible inputting commands from pins. Command Read mode(1) Read mode(2) Read mode(3) Reset
Note2 Note1
I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Command receivable during Busy
Notes: data output read mode FFH. only command that executed when device Busy reset command. other commands while device Busy.
Correspondence Table during Address Input Cycle (Address Setting)
When command [Read mode (1), Read mode (2)] Command address cycle address cycle address cycle I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
When command [Read mode (3)] Command address cycle address cycle address cycle I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
Remarks internal addresses. Internal address internally with command 01H. When command [read mode (3)], I/O4, I/O5, I/O6, I/O7 inputs address cycle VIL.
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MX23J12840
Electrical Specifications
Absolute Maximum Ratings Parameter Supply voltage Input voltage Input Output voltage Operating ambient temperature Storage temperature Symbol VI/O Tstg Condition Rating -0.5 +4.6 -0.3 VCC+0.3 -0.3 VCC+0.3 4.6) +150 Unit
Caution Exposing device stress above those listed Absolute Maximum Ratings could cause permanent damage. device meant operated under conditions outside limits described operational section this specification. Exposure Absolute Maximum Rating conditions extended periods affect device reliability.
Capacitance
Parameter Input capacitance Output capacitance Symbol Test condition MIN. TYP. MAX. Unit
Characteristics 2.7~3.6V)
Parameter High level input voltage level input voltage High level output voltage level output voltage Input leakage current Output leakage current Power supply current read Standby current (CMOS) output current Symbol ICCO1 ICCS2 IOL(RB) =-400uA VIL, IOUT tCYCLE VCC-0.2 Test conditions MIN. -0.3 TYP. MAX. VCC+0.3 +0.8 Unit
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MX23J12840
Characteristics 2.7~3.6V)
Parameter setup time hold time setup time hold time Write pulse width setup time hold time Data setup time Data hold time Write cycle time high hold time Ready falling edge Read pulse width Read cycle time access time (serial data access) high hold time last address serial read cycle high output Hi-Z high output Hi-Z high hold time Output Hi-Z falling edge high Memory cell array starting address high Busy (read cycle) last clock rising edge Busy sequential read) high Ready (when interrupted read mode) Device reset time Symbol tCLS tCLH tALS tALH tREA tCEH tRHZ tCHZ tREH tWHR tAR2 tCRY tRST
Note
MIN.
TYP.
MAX.
Unit
Note :tCRY (time from Ready) depends pull-up resister pin.
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MX23J12840
Test Conditions
Input Waveform (Rise/Fall Time 5ns)
1.5V
Test points
1.5V
Output Waveform
1.5V
Test points
1.5V
Input Pulse Levels 2.4V Output Load 100pF
P/N:PM1097
REV. 1.2, OCT. 2005
MX23J12840
READ CYCLE TIMING CHART
case read mode (1))
tCLS tCLH
tCEH
tCRY tALH tALS tALH tAR2 tCHZ
tREH tRHZ tRHZ
DOUT DOUT
A0-A7 A9-A16 A17-A24
I/O0~ I/O7
DOUT
tREA
Access page
Output Page Data
Remarks: Start address (SA) specification when read performed with command 00H. time (tCRY) from high level until Busy cancelled depends pull-up register output pin.
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REV. 1.2, OCT. 2005
MX23J12840
READ CYCLE TIMING CHART
case read mode (2))
tCLS tCLH
tCEH
tCRY tALH tALS tALH tAR2 tCHZ
tREH tRHZ tRHZ
DOUT DOUT
A0-A7 A9-A16 A17-A24
I/O0~ I/O7
DOUT
256+N tREA
256+N+1
Access page
Output Page Data
Remarks Start address (SA) specification when read performed with command 01H. time (tCRY) from high level until Busy cancelled depends pull-up register output pin.
P/N:PM1097
REV. 1.2, OCT. 2005
MX23J12840
READ CYCLE TIMING CHART
case read mode (3))
tCLS tCLH
tCEH
tCRY tALH tALS tALH tAR2 tCHZ
tREH tRHZ tRHZ
DOUT DOUT
A0-A3 A9-A16 A17-A24
I/O0~ I/O7
DOUT
512+N tREA
512+N+1
Access page
Output Page Data
Remarks Start address (SA) specification when read performed with command 50H. start address area (redundancy data) specified with during address cycle. this time, Don't Care. time (tCRY) from high level until Busy cancelled depends pull-up register output pin.
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MX23J12840
Sequential Read
read modes (1), (2), (3), when command (00H, 01H, 50H) input address specified, block that includes address that specified first, address automatically incremented read operation continuously performed until last address same block, inputting clock. this time, Busy period (tR) occurs after last address accessed page.
Note
Command Address input input
Page data output
Page data output
Output last page block
Command input
Note
Address input
Data output
tCRY
Busy
Busy
Busy
Busy
Busy
Busy
same block (Maximum pages)
Note perform read again after reading 527th byte data last page block, stop read operation once, then restart read operation inputting again read command address.
Relationship Between Command Start Address (SA) during Sequential Read
1block pages
Sequential read mode (When "00H" command input)
Sequential read mode (When "01H" command input)
Note Sequential read mode (When "50H" command input)
Note When "50H" command set, only area (redundancy data part) continuously read.
When "00H" command set, start address (SA) area (A). When "01H" command set, start address (SA) area (B). When "50H" command set, start address (SA) area (C).
P/N:PM1097 REV. 1.2, OCT. 2005
MX23J12840
SEQUENTIAL READ CYCLE TIMING CHART(1)
case read mode (1))
tCLS tCLH
tALH tALS tALH tAR2
tREH tRHZ
DOUT DOUT
A0-A7 A9-A16 A17-A24
I/O0~ I/O7
DOUT
DOUT
DOUT
tREA
Access page
Output Page Data
Access page
Output page data
Remarks 1.Start address (SA) specification when read performed with command 00H. 255.
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REV. 1.2, OCT. 2005
MX23J12840
SEQUENTIAL READ CYCLE TIMING CHART(2)
case read mode (2))
tCLS tCLH
tALH tALS tALH tAR2
tREH tRHZ
DOUT DOUT
A0-A7 A9-A16 A17-A24
I/O0~ I/O7
DOUT
DOUT
DOUT
256+N tREA
256+N+1
Access page
Output Page Data
Access page
Output page data
Remarks 1.Start address (SA) specification when read performed with command 01H. 255.
P/N:PM1097
REV. 1.2, OCT. 2005
MX23J12840
SEQUENTIAL READ CYCLE TIMING CHART(3)
case read mode (3))
tCLS tCLH
tALH tALS tALH tAR2
tREH tRHZ
DOUT DOUT
A0-A3 A9-A16 A17-A24
I/O0~ I/O7
DOUT
DOUT
DOUT
512+N tREA
512+N+1
Access page
Output Page Data
Access page
Output page data
Remarks 1.Start address (SA) specification when read performed with command 50H.
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REV. 1.2, OCT. 2005
MX23J12840
Reset Cycle Timing Chart
tCLS tCLH
tRST tALS tALH
I/O0~ I/O7
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MX23J12840
[Usage Cautions] Rated operation Operation using timing other than shown timing charts guaranteed. Commands that input only commands that input 00H, 01H, 50H, FFH. input other commands. other commands input, subsequent operation guaranteed. Command limitations during Busy period input commands other than reset command (FFH) during Busy period. command input during Busy period, subsequent operation guaranteed. Cautions regarding clock Following last clock, input clock until changes from Busy Ready. input clock other than during data output. Cautions upon power application Since state device undetermined upon power input high level execute reset command following power Cautions during read mode Perform address input immediately following command input. address input done without performing command input first, correct data cannot output because operation mode undetermined. execute read mode after read mode been stopped with reset command (FFH) input again command address. Busy output following access last address page read mode After access last address page, delay (tRHCH) from less, Ready status maintained Busy output keeping high level period (tCEH).
tCEH
tRHCH
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MX23J12840
PACKAGE INFORMATION
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REV. 1.2, OCT. 2005
MX23J12840
REVISION HISTORY
Revision Description Page Changed standby current from 100uA 40uA P1,6 Removed "Advanced Information" Added "Order Information" Removed tWHC Modified "Read cycle timing chart" "Sequential read cycle timing P9~11 chart" P13~15 Date AUG/16/2005 SEP/06/2005 OCT/28/2005
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MX23J12840
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http //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves right change product specifications without notice.
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