M11L416256SA PAGE MODE FEATURES organization (Extended

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M11L416256SA PAGE MODE FEATURES organization (Extended

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EliteMT
M11L416256SA
PAGE MODE
FEATURES
organization (Extended Data-Output) access mode Byte/Word Read/Write operation Single 3.3V 10%) power supply LVTTL-compatible inputs outputs 512-cycle refresh Refresh modes only, BEFORE (CBR) HIDDEN capabilities Self-refresh capability JEDEC standard pinout Parameter tRAC tCAC
ORDERING INFORMATION PACKAGE
40-pin 400mil 40-pin 400mil TSOP (Type
PRODUCT
PACKING TYPE
COMMENTS
M11L416256SASOJ/TSOPII M11L416256SA35
Pb-free
GENERAL DESCRIPTION
M11L416256 series randomly accessed solid state memory, organized 262,144 bits device. offers Extended Data-Output 3.3V( 10%) single power supply. Access time (-35) self-refresh package type (SOJ, TSOP optional features this family. these family have before -only refresh Hidden refresh capabilities. access modes supported this device: Byte access Word access. only leave other staying high will result BYTE access. WORD access happens when CASL CASH used.
CASL transiting during READ WRITE cycle will output input data into lower byte (IO0~IO7), CASH transiting will output input data into upper byte (IO8~15).
ASSIGNMENT
View
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
TSOP (TypeII) View
I/O1 I/O1 I/O1 I/O1 I/O1 I/O1 I/O9 I/O8 CASL CASH
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
I/O1 I/O1 I/O1 I/O1 I/O1 I/O1 CASL CASH
Elite Memory Technology
Publication Date: Aug. 2005 Revision 1/16
EliteMT
FUNCTIONAL BLOCK DIAGRAM
M11L416256SA
CASL CASH CONTROL LOGIC
DATA-IN BUFFER IO15
CLOCK GENERATOR
DATA-OUT BUFFER COLUMN DECODER
COLUMN ADDRESS BUFFER
REFRESH CONTROLER
SENSE AMPLIFIERS GATING
ROW. ADDRESS BUFFERS(9) DECODER MEMORY ARRAY REFRESH COUNTER
GENERATOR
DESCRIPTIONS
16~19,22~26 NAME A0~A8
CASH CASL
TYPE Input Input Input Input
DESCRIPTION Address Input Address A0~A8 Column Address A0~A8 Address Strobe Column Address Strobe Upper Byte Control Column Address Strobe Lower Byte Control
Input Input Input Output Supply Ground
Write Enable Output Enable Data Input Output Power, 3.3V Ground Connect
2~5,7~10,31~34,36~39 1,6,20 21,35,40 11,12,15,30
I/O0 I/O15
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Publication Date: Aug. 2005 Revision 2/16
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ABSOLUTE MAXIMUM RATINGS
Voltage Relative .-0.5V +4.6V Operating Temperature, (ambient) Storage Temperature (plastic) .-55 +150 Power Dissipation .0.8W Short Circuit Output Current .50mA
M11L416256SA
Permanent device damage occur "Absolute Maximum Ratings" exceeded. This stress rating only, functional operation device above those conditions indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
ELECTRICAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS 3.3V unless otherwise noted)
PARAMETER CONDITIONS SYMBOL UNITS NOTES
Supply Voltage Supply Voltage Input High Voltage Input Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Voltage Note 1.All Voltages referenced VIH(max) VOUT Output(s) disable
-0.3
+0.3
PARAMETER
CONDITIONS
cycling =min
SYMBOL
UNITS NOTES
Operating Current
ICC1
Standby Current
interface DOUT =High-Z CMOS interface, VCC-0.2V
ICC2
only refresh Current
=VIH,
ICC3 ICC4 ICC5 ICC6
Page Mode Current Standby Current
Before Refresh Current
0.2V, DOUT High-Z, CMOS interface VIL,
Battery Backup Current (S-ver. only) Self Refresh Current (S-ver. only)
ICC7
A0~A8 -0.2 0.2V DQ0~DQ15 -0.2, 0.2V open
ICC8
Note specified output open condition. Address changed twice less while =VIL Address changed once less while =VIH
Elite Memory Technology
Publication Date: Aug. 2005 Revision 3/16
EliteMT
CAPACITANCE 3.3V 10%)
PARAMETER SYMBOL
M11L416256SA
UNIT
Input Capacitance (address) Input Capacitance CASH CASL Output capacitance (I/O0~I/O15)
ELECTRICAL CHARACTERISTICS =3.3V 10%, (note
Test Conditions Input timing reference levels 0.8V, 2.0V Output reference level VOL= 0.8V, VOH=2.0V Output Load 2TTL gate (50pF) Assumed
PARAMETER
Read Write Cycle Time Read Write Cycle Time EDO-Page-Mode Read Write Cycle Time EDO-Page-Mode Read-Write Cycle Time Access Time From Access Time From Access Time From Access Time From Column Address Access Time From Precharge
SYMBOL
UNIT
NOTES
tRWC tPCM tRAC tCAC tOAC tACP tRAS tRASC tRSH tCAS tCSH tRCD tCRP tASR tRAH tRAD tASC tCAH tRAL tRCS
100K
15,18
5,20 13,20
Pulse Width Pulse Width (EDO Page Mode) Hold Time Precharge Time Pulse Width Hold Time Precharge Time Delay Time Precharge Time
Address Setup Time Address Hold Time
6,23 7,18
Column Address Delay Time
Column Address Setup Time Column Address Hold Time Column Address Hold Time (Reference Column Address Lead Time Read Command Setup Time
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Publication Date: Aug. 2005 Revision 4/16
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(Continued)
PARAMETER Read Command Hold Time Reference Read Command Hold Time Reference SYMBOL
M11L416256SA
9,15,19 10,17,20 17,26 11,15,18 15,25 15,19 12,20 12,20
UNIT
NOTES
tRCH tRRH tCLZ tOFF1 tOFF2 tWCS tWCH tWCR tRWL tCWL tDHR tRWD tAWD tCWD tREF tRPC tCSR tCHR tOEH tOES tOEHC tOEP tORD tCLCH tCOH tWHZ tRASS tRPS tCHS
Output Low-Z
Output Buffer Turn-off Delay From
Output Buffer Turn-off Write Command Setup Time Write Command Hold Time Write Command Hold Time(Reference Write Command Pulse Width Write Command Lead Time Write Command Lead Time Data-in Setup Time Data-in Hold Time Data-in Hold Time (Reference
Delay Time
Column Address Delay Time
11,18
Delay Time
Transition Time (rise fall) Refresh Period (512 cycles)
Precharge Time Setup Time(CBR REFRESH) Hold Time(CBR REFRESH) Hold Time From During Read-Mode-Write Cycle High Setup Time High Hold Time From High Precharge Time Setup Prior During Hidden Refresh Cycle
Last Going First Returning High Data Output Hold After Returning Output Disable Delay From Self Refresh Pulse width Self Refresh High Precharge Time Self Refresh Hold Time
1,18 1,19
27,28 27,28 27,28
Elite Memory Technology
Publication Date: Aug. 2005 Revision 5/16
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Notes
M11L416256SA
Enables on-chip refresh address counters. VIH(min) VIL(max) reference levels measuring timing input signals. Transition times measured between VIL. addition meet transition rate specification, input signals must transit between monotonic manner. Assume that tRCD tRCD(max). tRCD greater than maximum recommended value shown this table, tRAC will increase amount that tRCD exceeds value shown. Assume that tRCD tRCD (max) falling edge data-out will maintained from previous cycle. initiate cycle clear data-out buffer, must pulsed high. Operation within tRCD limit ensures that tRCD (max) met, tRCD (max) specified reference point only tRCD greater than specified tRCD (max) limit, access time controlled tCAC. Operation within tRAD limit ensures that tRAD(max) met. tRAD(max) specified reference point only tRAD greater than specified tRAD (max) limit, access time controlled tAA. Either tRCH tRRH must satisfied READ cycle. tOFF1(max) defines time which output achieves open circuit condition reference VOL. tWCS, tRWD, tAWD tCWD restrictive operating parameters LATE WRITE READ-MODIFY-WRITE cycle only. tWCS tWCS(min) cycle EARLY WRITE cycle data output will remain open circuit throughout entire cycle. tRWD tRWD(min) tAWD tAWD(min) tCWD tCWD(min) cycle READ-WRITE data output will contain data read from selected cell. neither above conditions met, state access time until back indeterminate. held high taken after goes result LATE WRITE -controlled) cycle.
Those parameters referenced leading edge EARLY WRITE cycles leading edge LATE WRITE READ-MODIFY- WRITE cycles. During READ cycle, then taken HIGH before goes high, goes open, tied permanently low, LATE WRITE READ-MODIFY-WRITE operation possible. initial pause required after power-up followed eight refresh cycles only CBR) before proper device operation assured. eight cycle wake-ups should repeated time tREF refresh requirement exceeded. WRITE command defined going low. LATE WRITE READ-MODIFY-WRITE cycles must have both tOFF2 tOEH high during WRITE cycle) order ensure that output buffers will open during WRITE cycles. I/Os open during READ cycles once tOFF1 tOFF2 occur. Referenced earlier falling edge. Referenced latter rising edge. Output parameter (I/O) referenced corresponding input, IO0~7 CASL IO8~15 CASH Last falling edge first rising edge. Last rising edge next cycle's last rising edge. Last rising edge first falling edge. Each must meet minimum pulse width. Referenced latter falling edge. controlled regardless CASL CASH Self refresh mode initiated performing refresh cycle holding specified tRASS. Self refresh mode terminated rising high minimum time tRPS. refresh mode expect distributed refresh mode, rows must refreshed within refresh rate before after self refresh.
Elite Memory Technology
Publication Date: Aug. 2005 Revision 6/16
EliteMT
TRUTH TABLE
ADDRESSES
M11L416256SA
FUNCTION
CASL CASH
High-Z Data-Out Lower Byte, Data-Out Upper Byte, Data-Out Data-In Lower Byte, Data-In Upper Byte, High-Z Lower Byte, High-Z Upper Byte, Data-In Data-Out, Data-In Data-Out Data-Out Data-Out
NOTES
Standby Read Word Read Lower Byte Read Upper Byte Write Word (Early Write) Write Lower Byte (Early)
Write Upper Byte (Early) Read-Write Cycle EDO-Page-Mode Cycle Read Cycle EDO-Page-Mode Cycle Write Cycle EDO-Page-Mode Cycle Read-Write Cycle Hidden Refresh
-Only Refresh
Data-In Data-In Data-Out, Data-In Data-Out, Data-In Data-Out High-Z
Refresh Self-Refresh
High-Z High-Z
*Note These WRITE cycles also BYTE WRITE cycles (either CASL CASH active). These READ cycles also BYTE READ cycles (either CASL CASH active). Only must active CASL CASH
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Publication Date: Aug. 2005 Revision 7/16
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READ CYCLE
tRAS
M11L416256SA
tCSH
tCRP
tRCD
tRSH tCAS
tRRH tCLCH
tASR
ADDR
tRAD tRAH
tASC
tRAL tCAH
COLUMN
tRCS
tRCH
tRAC tCAC tCLZ
OPEN
tOFF1
DATA
tOFF2
EARLY WRITE CYCLE
tRAS
tCRP
CASL
tRCD
tCSH tRSH tCAS
tCLCH
tASR
ADDR
tRAD tRAH
tASC
COLUMN
tRAL tCAH
tWCS
tCWL tRWL tWCR tWCH
tDHR
DATA
DON'T CARE UNDEFINED
Note: tOFF1 referenced from rising edge whichever occurs last.
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Publication Date: Aug. 2005 Revision 8/16
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READ WRITE CYCLE (LATE WRITE READ-MODIFY-WRITE CYCLES)
tRWC
M11L416256SA
tCRP
CASL,CASH
tRCD
tCSH tCAS,tCLCH
tASR
ADDR
tRAD tRAH
tASC
COLUMN
tRCS
tRWD tCWD tAWD
tCWL tRWL
tRAC tCAC tCLZ
VI/O VI/O OPEN
VALI
tOFF
tOEH
EDO-PAGE-MODE READ CYCLE
tRASC
tCRP
CASL
tCSH tRCD
tCAS tCLCH
(NOTE2)
tCAS,tCLCH
tRSH tCAS, CLCH
tASR tRAH
ADDR
tRAL tASC tCAH tASC tASC tCAH
COLUMN
COLUMN
COLUMN
tRCS
tRCH
tRRH
tRAC tCAC tCLZ
OPEN
tCAC tCOH
VALID DATA
tACP tCAC tCLZ tOEHC tOFF tOES tOEP
tOFF
OPEN
tOES
tOFF
DON'T CARE
UNDEFINED
*NOTE tOFF1 referenced from rising edge whichever occurs last. measured from falling edge falling edge from rising edge rising edge Both measurements must meet specification.
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Publication Date: Aug. 2005 Revision 9/16
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EDO-PAGE-MODE EARLY-WRITE CYCLE
tRASC
M11L416256SA
tCSH tCRP
CASL ,CASH
tRCD
tCAS,tCLCH
(NOTE1) tCAS, tCLCH
tRSH tCAS,tCLCH
tRAD tASR
ADDR
tRAH
tASC
tCAH
tASC
tCAH
tASC
tRAL tCAH
COLUMN
COLUMN
COLUMN
tCWL tWCS tWCH tWCS
tCWL tWCH
tWCS
tCWL tWCH
tWCR tDHR
tRWL
DATA
DATA
DATA
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE READ-MODIFY-WRITE CYCLES)
tRASC
tCSH tCRP
CASL ,CASH
tRCD
tCAS,tCLCH
tPCM tCAS, tCLCH
tRSH tCAS,tCLCH
tRAD tASR
ADDR
tRAH
tASC
tCAH
tASC tCAH
COLUMN
tASC
tRAL tCAH
COLUMN
COLUMN
tRWD tRCS tCWL tCWL tAWD tCWD tAWD tCWD
tRWL tCWL
tAWD tCWD
tRAC tCAC tCLZ
VI/O VI/O
VALI VALI DOUT
tACP tCAC tCLZ
VALI VALI DOUT
tACP tCAC tCLZ
VALID VALI DOUT
tOFF2
tOFF
tOFF2 tOEH
DON'T CARE
UNDEFINED
Note measured from falling edge falling edge from rising edge rising edge Both measurements must meet specification.
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Publication Date: Aug. 2005 Revision 10/16
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EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY-WRITE)
tRASC
M11L416256SA
tCSH tCRP
CASL
tRCD
tCAS
tCAS
tRSH tCAS
tRAD tASR tRAH
ADDR
tRAL tCAH tCAH tASC tCAH
tASC
COLUMN(A)
COLUMN(B)
COLUMN(N)
tRCS
tRCH
tWCS
tWCH
tRAC tCAC tACP
tWHZ tCAC tCOH
DATA(
VALID DATA(B
VI/OH VI/OL
OPEN
VALID DATA
ONLY REFRESH CYCLE (ADDR A0~A8 DON'T CARE)
tRAS
tCRP
CASL,CASH
tRPC
tASR
ADDR
tRAH
DON'T CARE UNDEFINED
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Publication Date: Aug. 2005 Revision 11/16
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REFRESH CYCLE (A0~A8 DON'T CARE)
M11L416256SA
tRAS
tRAS
tRPC
CASL
tCSR
tCHR
tRPC
tCSR
tCHR
OPEN
tRCH
HIDDEN REFRESH CYCLE HIGH LOW)
(READ)
(REF RESH)
tRAS
tRAS
tCRP
CASL
tRCD
tRSH
tCHR
tRAD tASR
ADDR
tRAH
tASC
tRAL tCAH
COLUMN
tRAC tCAC tCLZ
OPEN VALID DATA
tOFF1
OPEN
tORD
tOFF2
DON'T CARE
UNDEFINED
Note tOFF1 reference from rising edge whichever occurs last.
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Publication Date: Aug. 2005 Revision 12/16
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SELF REFRESH CYCLE DON'T CARE)
M11L416256SA
tRASS
tRPS
tRPC
CASL ,CASH
tCSR
tRPC tCHS
tCRP
tASR
ADDR
OPEN
tRCH
DON'T CARE
UNDEFINED
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Publication Date: Aug. 2005 Revision 13/16
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PACKING 40-LEAD SECTION
M11L416256SA
DIMENSIONS SOJ(400mil)
0.050" Max.
Detail
Seating Plain Detail 0.024" Min.
SECTION
0.050" Max.
Detail
Seating Plain Detail 0.024" Min.
Symbol
Dimension Norm 3.250 3.510 3.760 2.080 2.790 0.380 0.460 0.560 0.635 0.180 0.250 0.360 1.270
Dimension inch Symbol Dimension Norm Norm 0.128 0.138 0.148 10.920 11.176 11.430 0.082 10.030 10.160 10.290 0.110 9.40 0.015 0.018 0.022 0.760 0.890 1.020 0.025 0.007 0.010 0.014 0.050 25.91 26.040 26.290
Dimension inch Norm 0.430 0.440 0.450 0.395 0.400 0.405 0.370 0.030 0.035 0.040
1.02 1.025
1.035
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Publication Date: Aug. 2005 Revision 14/16
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PACKING 44-LEAD DIMENSIONS TSOP(II) DRAM(400mil)
M11L416256SA
Symbol
Dimension 0.05 0.95 0.30 0.30 0.12 0.10 18.28 11.56 10.03 0.40 18.41 0.805 11.96 10.29 0.69 11.76 10.16 0.59 0.80 0.80 0.35 1.00 Norm 1.20 0.15 1.05 0.45 0.40 0.21 0.16 18.54
Dimension inch 0.002 0.037 0.012 0.012 0.005 0.004 0.720 0.455 0.395 0.016 0.725 0.0317 0.463 0.400 0.023 0.031 0.0315 0.471 0.027 0.014 0.039 Norm 0.047 0.006 0.042 0.018 0.016 0.008 0.006 0.730
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Publication Date: Aug. 2005 Revision 15/16
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Important Notice rights reserved.
M11L416256SA
part this document reproduced duplicated form means without prior permission EliteMT. contents contained this document believed accurate time publication. EliteMT assumes responsibility error this document, reserves right change products specification this document without notice. information contained herein presented only guide examples application products. responsibility assumed EliteMT infringement patents, copyrights, other intellectual property rights third parties which result from use. license, either express implied otherwise, granted under patents, copyrights other intellectual property rights EliteMT others. semiconductor devices have inherently certain rate failure. minimize risks associated with customer's application, adequate design operating safeguards against injury, damage, loss from such failure, should provided customer when making application designs. EliteMT's products authorized critical applications such limited life support devices system, where failure abnormal operation directly affect human lives cause physical injury property damage. products described here used such kinds application, purchaser must quality assurance testing appropriate such applications.
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Publication Date: Aug. 2005 Revision 16/16

M11L416256SA PAGE MODE FEATURES organization (Extended

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