Provides Bridge Between Extended Bus; 25-33 Extended Bus; 7.5-8.33 Sys
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INTEL 430MX PCISET 82371MX MOBILE XCELERATOR (MPIIX)
Provides Bridge Between Extended Bus; 25-33 Extended Bus; 7.5-8.33 System Power Management (Intel Support) Programmable System Management Interrupt (SMI)-Hardware/Software Events, EXTSMI# Programmable Clock Control (STPCLK#) with Auto Clock Throttle Peripheral Device Power Management (Local Standby) Suspend State Support (Suspend-toDRAM Suspend-to-Disk) Enhanced Functions 8237 Controllers Fast Type Compatible Transfers PC/PCI Expansion Docking Support Fast Interface Mode Transfers 2x16-Bit Posted Write Buffer 1x32-Bit Read Prefetch Buffer Plug-n-Play Port Motherboard Devices Steerable Channels Steerable Interrupt Line (Plus Steerable Interrupts) Programmable Chip Select Functionality 82C54 Timer
System Timer Refresh Request Speaker Tone Output
Functionality 82C59 Interrupt Controllers Interrupts Supported Independently Programmable Edge/Level Sensitivity X-Bus Peripheral Support
Chip Select Decode Controls Lower X-Bus Data Byte
Transceiver Non-Maskable Interrupts (NMI) System Error Reporting NAND Tree Board-Level Testing 176-Pin TQFP
82371MX Xcelerator (MPIIX) provides bridge between ISA-like Extended expansion bus. addition, 82371MX interface that supports devices providing interface hard disks ROMs. MPIIX integrates many common functions found based systems-a seven-channel controller, 82C59 interrupt controllers, 8254 timer/counter, Intel power management support, control logic generation. Chip select decoding provided BIOS, real time clock, keyboard controller. Edge/Level interrupts interrupt steering supported plug play compatibility. MPIIX also provides Extended direct connection Super devices providing complete PC-compatible solution. MPIIX also provides support "Mobile PC/PCI" Expansion protocol that enables implementation Docking Stations with full capability without running full across docking connector. motherboard Plug-n-Play compatibility, 82371MX also provides three steerable channels, three steerable interrupt lines, programmable chip select. interrupt lines routed available interrupts. MPIIX's power management function supports SMI# interrupt sources, extensive clock control (including Auto Clock Throttling), peripheral power idle detection with access traps, system Suspend-to-DRAM Suspend-to-Disk.
*Other brands names property their respective owners. Information this document provided connection with Intel products. Intel assumes liability whatsoever, including infringement patent copyright, sale Intel products except provided Intel's Terms Conditions Sale such products. Intel retains right make changes those specifications time, without notice. Microcomputer Products have minor variations this specification known errata.
COPYRIGHT INTEL CORPORATION, 1996
April 1996
Order Number: 290525-001
82371MX (MPIIX)
SMI# STPCLK# EXTSMI# SRBTN# ATLO RST# UT[3:0]
System Power Mgmt
E#/SM OUT5
DIOR# Interface DIOW# IORDY [15:8]/S [15:8]/S [15:8] [7:0]/S [7:0] [2:0]/S [2:0] S1#/SA S3#/SA
EXTEVNT# PAD# AD[31:0] C/BE[3:0]# FRAME# TRDY# IRDY# STOP# DEVSEL# SERR# IDSEL PHOLD PHOLDA# [A,B]# ,B]# xtended terface otherb oard terface
SA16 ZERO MEMW ALTA20M
Interface
RTCALE/SM
IRQ8# IRQ12/M Interrupt INTR IRQ(15,14,11:9,7:3,1) PIRQ System Clocks Reset
PWROK CPURST PCIRST# RSTDRV INIT CLK0
MDRQ0 2#/PA 2/EX TEVN
TESTIN#
Test
Timers/ Counters
SPKR
MPIX_BLK
82371MX MPIIX Block Diagram
82371MX (MPIIX)
CONTENTS
1.0. ARCHITECTURE OVERVIEW. SIGNAL DESCRIPTION 2.1. Interface Signals. 2.2. Interface Signals. 2.3. Extended Signals 2.4. Motherboard Device Interface Signals 2.5. Signals 2.6. Interrupt Controller Signals 2.7. System Power Management SMM) Signals 2.8. System Clock Reset Signals 2.9. Test Signals 3.0. REGISTER DESCRIPTION 3.1. Register Access 3.2. Configuration Registers 3.2.1. VID-VENDOR IDENTIFICATION REGISTER 3.2.2. DID-DEVICE IDENTIFICATION REGISTER 3.2.3. COM-COMMAND REGISTER 3.2.4. DS-DEVICE STATUS REGISTER 3.2.5. RID-REVISION IDENTIFICATION REGISTER 3.2.6. CLASSC-CLASS CODE REGISTER 3.2.7. HEDT-HEADER TYPE REGISTER 3.2.8. SPPE-SERIAL PARALLEL PORT ENABLE REGISTER 3.2.9. ECRT- EXTENDED CONTROLLER RECOVERY TIMER REGISTER 3.2.10. BIOSE BIOS ENABLE REGISTER 3.2.11. FDCE-FDC ENABLE REGISTER 3.2.12. PIRQRC [A,B]-PIRQX ROUTE CONTROL REGISTERS 3.2.13. MSTAT-MISCELLANEOUS STATUS REGISTER 3.2.14. IDETIM-IDE TIMING REGISTER 3.2.15. MIRQRC-MOTHERBOARD DEVICE ROUTE CONTROL REGISTER 3.2.16. MDMARC[2:0]MOTHERBOARD DEVICE ROUTE CONTROL REGISTERS 3.2.17. AUDIOE-AUDIO ENABLE REGISTER 3.2.18. DMADS-DMA CH[7:5] DATA SIZE REGISTER 3.2.19. PCIDMAE-PCI ENABLE REGISTER 3.2.20. PCIDMA[A,B]PCI EXPANSION REGISTER 3.2.21. PMAC[1:0]-PROGRAMMABLE MEMORY ADDRESS CONTROL REGISTERS 3.2.22. PMAM[1:0]-PROGRAMMABLE MEMORY ADDRESS MASK REGISTERS 3.2.23. PARE-PROGRAMMABLE ADDRESS RANGE ENABLE REGISTER 3.2.24. PCSC-PROGRAMMABLE CHIP SELECT CONTROL REGISTER
82371MX (MPIIX)
3.2.25. PAC[5:1]-PROGRAMMABLE ADDRESS CONTROL REGISTER 3.2.26. PAMA-PROGRAMMABLE ADDRESS MASK REGISTER 3.2.27. PAMB-PROGRAMMABLE ADDRESS MASK REGISTER 3.2.28. IOCA-I/O CONFIGURATION ADDRESS REGISTER 3.2.29. PAMC-PROGRAMMABLE ADDRESS MASK REGISTER 3.2.30. PADE[2:0]-PERIPHERAL ACCESS DETECT ENABLE REGISTERS 3.2.31. LTADEV3-Local Trap Address Device Register 3.2.32. LTMDEV3-Local Trap Mask Device Register 3.2.33. LTSMIE-Local Trap Enable Register 3.2.34. LTSMIS-Local Trap Status Register 3.2.35. LSBSMIE-Local Standby Enable Register 3.2.36. LSBTRE-Local Standby Timer Reload Enable Register 3.2.37. LSBSMIS-Local Standby Status Register 3.2.38. LSTBTIDE-Local Standby Timer Register 3.2.39. LSBTAUD-Local Standby Audio Timer Register 3.2.40. LSBTCOM-Local Standby Timer Register 3.2.41. LSBTDEV1-Local Standby Device Timer Register 3.2.42. LSBTDEV2-Local Standby Device Timer Register 3.2.43. LSBTDEV3-Local Standby Device Timer Register 3.2.44. SESMIT-Software/EXTSMI# Delay Timer Register 3.2.45. SUSSMIT-Suspend Delay Timer Register 3.2.46. GSBTMR-Global Standby Timer Register 3.2.47. CLKTHSBYT Clock Throttle Standby Timer Register 3.2.48. SYSMGNTC-System Management Control Register 3.2.49. SYSSMIE-System Enable Register 3.2.50. MISCSMIE-Misc Enable Register 3.2.51. GSMIE-Global Enable Register 3.2.52. SYSSMIS-System STATUS Register 3.2.53. MISCSMIS-Miscellaneous STATUS Register 3.2.54. GSMIS Global STATUS Register 3.2.55. SUSRSMC1-Suspend/Resume Control Register 3.2.56. SUSRSMC2-Suspend/Resume Control Register 3.2.57. SMOUTC-SMOUT Control Register 3.2.58. SYSEVNTE0-System EVENT Enable Register 3.2.59. SYSEVNTE1-System EVENT Enable Register 3.2.60. SYSEVNTE2-System EVENT Enable Register 3.2.61. BSTCLKT Burst Count Timer Register 3.2.62. CLKC-Clock Control Register 3.2.63. STPCLKLT-STPCLK# Timer Register 3.2.64. STPCLKHT-STPCLK# High Timer Count 3.2.65. STPBRKE0-Stop Break Event Enable Register 3.2.66. STPBRKE1-Stop Break Event Enable Register
82371MX (MPIIX)
3.2.67. STPBRKE2-Stop Break Event Enable Register 3.2.68. SHDW-Shadow Register Access Port 3.2.69. BSTCLKEE[6:0]-Burst Clock Event Enable Registers 3.2.70. CLKTHLBRKEE[6:0]-Clock Throttle Break Event Enable Registers 3.3. Compatible Registers 3.3.1. REGISTERS. 3.3.1.1. DCOM-DMA Command Register 3.3.1.2. DCM-DMA Channel Mode Register 3.3.1.3. DR-DMA Request Register 3.3.1.4. Mask Register-Write Single Mask 3.3.1.5. Mask Register-Write Mask Bits 3.3.1.6. DS-DMA Status Register 3.3.1.7. Base Current Address Registers (8237 Compatible Segment) 3.3.1.8. Base Current Byte/Word Count Registers (Compatible Segment) 3.3.1.9. Memory Page Registers 3.3.1.10. Clear Byte Pointer Register 3.3.1.11. DMC-DMA Master Clear Register 3.3.1.12. DCLM-DMA Clear Mask Register 3.3.2. TIMER/COUNTER REGISTERS 3.3.2.1. TCW-Timer Control Word Register 3.3.2.2. Interval Timer Status Byte Format Register 3.3.2.3. Counter Access Ports Register 3.3.3. INTERRUPT CONTROLLER REGISTERS 3.3.3.1. ICW1-Initialization Command Word Register 3.3.3.2. ICW2-Initialization Command Word Register 3.3.3.3. ICW3-Initialization Command Word Register 3.3.3.4. ICW3-Initialization Command Word Register 3.3.3.5. ICW4-Initialization Command Word Register 3.3.3.6. OCW1-Operational Control Word Register 3.3.3.7. OCW2-Operational Control Word Register 3.3.3.8. OCW3-Operational Control Word Register 3.3.3.9. ELCR1-Edge/Level Triggered Register 3.3.3.10. ELCR2-Edge/Level Triggered Register 3.3.4. RESET EXTENDED I/O-BUS IRQ12 IRQ1 REGISTER 3.3.5. REGISTERS 3.3.5.1. NMISC-NMI Status Control Register 3.3.5.2. Enable Real-Time Clock Address Register 3.3.5.3. Coprocessor Error Register 3.3.5.4. RC-Reset Control Register 3.3.5.5. Port Register 3.4. Advanced Power Management Registers 3.4.1. APMC-ADVANCED POWER MANAGEMENT CONTROL PORT
82371MX (MPIIX)
3.4.2. APMS-ADVANCED POWER MANAGEMENT STATUS PORT 4.0. FUNCTIONAL DESCRIPTION 4.1. Memory Address 4.1.1. ACCESSES.84 4.1.2. BIOS MEMORY ACCESS 4.1.3. PERIPHERAL CHIP SELECTS 4.2. Interface.86 4.2.1. TRANSACTION TERMINATION 4.2.2. PARITY SUPPORT 4.2.3. ARBITRATION 4.2.4. CLOCK CONTROL (CLKRUN#) 4.3. Extended 4.3.1. EXTENDED CYCLES MPIIX MASTER (PCI MASTER INITIATED) 4.3.2. EXTENDED (8-BIT 16-BIT TRANSFERS) 4.4. Controller.90 4.4.1. TYPE TIMING 4.4.2. buffer type transfers 4.4.3. EXTENDED ARBITRATION 4.4.4. DMA.91 4.4.4.1. Expansion Protocol 4.4.4.2. Expansion Cycles 4.4.4.3. Normal Cycle 4.4.4.4. Normal Cycle with Terminal Count 4.4.4.5. Verify Cycle 4.4.4.6. Verify Cycle with Terminal Count 4.5. Interface.98 4.5.1. REGISTER BLOCK DECODE 4.5.2. ENHANCED TIMING MODES 4.5.2.1. IORDY masking 4.5.2.2. data port mode 4.6. Interval Timer 4.7. Interrupts. 4.7.1. PROGRAMMING INTERRUPT CONTROLLER 4.7.1.1. Edge Level Triggered Mode 4.7.2. INTERRUPT STEERING 4.7.3. MOUSE FUNCTION 4.7.4. COPROCESSOR ERROR FUNCTION 4.7.5. SUPPORT 4.8. Power Management Support 4.8.1. GENERATION. 4.8.1.1. Enables
82371MX (MPIIX)
4.8.1.2. Request Status.106 4.8.1.3. SMI# Signal Generation .108 4.8.1.4. SOURCES .108 4.8.2. POWER MANAGEMENT (CPU, DRAM, CACHE, DATAPATH) 4.8.2.1. Stop Clock. 4.8.2.2. Software Control STPCLK# 4.8.2.3. Emulating Clock Division (Clock Throttling) .112 4.8.2.4. STPCLK Control State Machine 4.8.2.5. Auto Clock Throttle (ACT) Feature .114 4.8.3. LOCAL STANDBY (PERIPHERAL MANAGEMENT) .117 4.8.3.1. Local Standby Sequence .117 4.8.3.2. Access Ranges .118 4.8.3.3. Idle Timers 4.8.3.4. Access Traps 4.8.3.5. SMOUT Programmable Outputs 4.8.4. SUSPEND .119 4.8.4.1. Suspend mode selects .120 4.8.4.2. Suspend SMI# Requests (SRBTN# BATLOW#) 4.8.4.3. Suspend Status (SUSTAT#) Signal Register 4.8.4.4. POWER PLANE CONTROL .122 4.8.4.5. SHADOW REGISTERS .123 4.8.5. SUMMARY TIMER RANGES 4.9. Reset Support .124 5.0. PINOUT PACKAGE INFORMATION .125 5.1. Pinout Information.125 5.2. Package Information. 6.0. TESTABILITY. .130
82371MX (MPIIX)
82371MX (MPIIX)
1.0. ARCHITECTURE OVERVIEW
This section provides brief overview MPIIX. More detailed descriptions provided Signal Description, Register Description, Functional Description sections. Power Management. Flexible power management capabilites MPIIX permit operating system system software efficiently manage system resources. Various power states supported while providing best performance user. MPIIX uses several mechanisms help power management software initiate manage transitions between power managed states. These include, System Event Monitors such Idle Timers identify peripheral system-wide idle wake-up conditions, Intel's System Management Interrupt (SMI) support, Advanced Power Management (APM) interface, Pentium® Processor STPCLK# Clock Control, Power Suspend/Resume hardware. Docking Support. MPIIX provides mechanisms necessary implement docking solution that supports both docking station. information sent across according PC/PCI expansion protocol. IRQx lines provided. cycles intended MPIIX positively decoded that bridge docking station subtractive decode agent. Fast Interface. MPIIX supports connector motherboard devices) transfers Mbytes/sec. interface 2-word write poster read prefetcher optimal transfers. Plug-n-Play Interface. MPIIX provides Plug-n-Play interface motherboard devices consisting steerable channels, steerable interrupt line, programmable chip select. Each steerable channel supports TYPE transfers 4-byte buffer. Interface. MPIIX provides both master slave interface bus. master, MPIIX runs cycles behalf DMA. slave, MPIIX accepts cycles initiated masters targeted MPIIX's internal register Extended bus. MPIIX directly supports running either MHz. Extended Bus. MPIIX incorporates 8-bit ISA-like interface motherboard devices such MultiFunction I/O, Keyboard Controller, Audio Chip, Flash memory, Real Time Clock. MPIIX also includes 16-bit interface. cycles this interface positively decoded. programmable Chip Select range, PCS#, additional programmable ranges provided other devices Extended bus. DMA. controller incorporates functionality 82C37 controllers with seven independently programmable channels. Channels [3:0] hardwired 8-bit, count bytes transfers, channels [7:5] programmed either 16-bit, count words transfers, 8-bit transfers. seven channels support fast type timings using steerable channels. Timer. timer block contains three counters that equivalent function those found 82C54 programmable interval timer. These counters provide system timer function speaker tone. 14.31818 oscillator input provides clock source counters. Interrupt Controller. MPIIX provides compatible interrupt controller that incorporates functionality 82C59 interrupt controllers. interrupt controllers cascaded that external internal interrupts possible.
82371MX (MPIIX)
Pentium Processor Control ddress Data Second Level Cache ache MTSC Control Address/Data [7:0] Cntl Main Memory (DRAM)
Data
Cntl PLIN (Data)
Fast MPIIX raphics
Audio
Plug-n-Play Port
Extended
052501
Figure Intel 430MX PCIset PCIset System
82371MX (MPIIX)
SIGNAL DESCRIPTION
This section provides detailed description each signal. signals arranged functional groups according their associated interface. symbol signal name indicates that active, asserted state occurs when signal voltage level. When present after signal name, signal asserted when high voltage level. terms assertion negation used extensively. This done avoid confusion when working with mixture 'active-low' 'active-high' signals. term assert, assertion indicates that signal active, independent whether that level represented high voltage. term negate, negation indicates that signal inactive. Certain signals used drive other signals with different functions through external buffers transceivers. Both functions have been noted descriptions below, with signal whose function being described bold font. actual name given signal driven MTSC. "PCIRST#" column indicates state signals during reset. following notations used describe signal type. s/t/s Input standard input-only signal. Totem pole output standard active driver. Open drain. Tri-State bi-directional, tri-state input/output pin. Sustained tri-state active tri-state signal owned driven only agent time. agent that drives s/t/s must drive high least clock before letting float. agent start driving s/t/s signal sooner than clock after previous owner tri-states external pull-up required sustain inactive state until another agent drives must provided central resource. Indicates standard 3.3V voltage interface. Indicates that this signal normally will powered voltage VDDR "resume well" power supply during suspend state normal volts. Internal Pull-Up Internal Pull-Down Internal Keeper
3.3V 5/3V
2.1. Interface Signals
Signal Name AD[31:0] Type PCIRST# Tri-state Description ADDRESS/DATA: standard address data lines. address driven with FRAME# assertion data driven received following clocks. COMMAND BYTE ENABLES: command driven with FRAME# assertion. Byte enables corresponding supplied requested data driven following clocks.
C/BE[3:0]#
Tri-state
82371MX (MPIIX)
Signal Name FRAME# Type (s/t/s) (s/t/s) (s/t/s) (s/t/s) (s/t/s) Tri-state PCIRST# Tri-state Description FRAME: Assertion indicates address phase transfer. Negation indicates that more data transfer desired cycle initiator. This signal requires pullup resistor. TARGET READY: Asserted when target ready data transfer. This signal requires pullup resistor. INITIATOR READY: Asserted when initiator ready data transfer. This signal requires pullup resistor. STOP: Asserted target request master stop current transaction. This signal requires pullup resistor. INITIALIZATION DEVICE SELECT: IDSEL used chip select during configuration read write transactions. DEVICE SELECT: MPIIX asserts DEVSEL# claim transaction through positive decoding. This signal requires pullup resistor. CALCULATED PARITY SIGNAL: "even" parity calculated bits-AD[31:0] plus C/BE[3:0]#. SYSTEM ERROR: SERR# pulsed active device that detects system error condition. Upon sampling SERR# active, MPIIX programmed generate non-maskable interrupt (NMI) CPU. This signal requires pullup resistor. Tri-state HOLD: MPIIX asserts this signal request Bus. HOLD ACKNOWLEDGE: MTSC asserts this signal grant MPIIX. REQUEST PC/PCI requests dedicated channel PC/PCI expansion. These signals should used standard Masters. Tri-state GRANT grants dedicated channel PC/PCI expansion. These signals should used standard Masters. CLOCK RUN: CLKRUN# asynchronous request start clock. This signal also indicates clock status. RESET: System Clock Reset Signal section.
TRDY#
Tri-state
IRDY#
Tri-state
STOP#
Tri-state
IDSEL DEVSEL#
SERR#
Tri-state
PHOLD# PHLDA# REQ[A,B]#
GNT[A,B]#
CLKRUN# PCIRST#
Tri-state
82371MX (MPIIX)
2.2. Interface Signals
Signal Name DD[15:8]/ SA[15:8]/ SD[15:8] Type pu8K Undefined PCIRST# Undefined Description DISK DATA: These signals directly drive corresponding signals connector. addition, these signals externally buffered produce SA[15:8] signals (see separate descriptions). DISK DATA: These signals directly drive corresponding signals connector. addition, these signals externally buffered produce SD[7:0] signals (see separate descriptions). DISK READ: This signal directly drives corresponding signal connector.
DD[7:0]/ SD[7:0]
Tri-state
DIOR#
High
DIOW#
High
DISK WRITE: This signal directly drives corresponding signal connector.
IORDY
CHANNEL READY: This input signal directly driven corresponding signal connector. DISK ADDRESS: These address signals directly drive DA[2:0] signals connector used indicate which byte command block control block being addressed. These pins multiplexed with SA[2:0]. DISK CHIP SELECTS: DCS1# controls command register block corresponds CS1FX# connector. DCS3# controls control register block corresponds CS3FX# connector. These pins multiplexed with SA[7,6]. DISK OUTPUT ENABLE: This signal controls isolation buffers. SMOUT5 configured enable this function SMOUT Control Register.
DA[2:0]/ SA[2:0]
DCS1#, DCS3# SA7,SA6
Undefined
DOE# SMOUT5
High
82371MX (MPIIX)
2.3. Extended Signals
Signal Name SYSCLK Type PCIRST# Active Description SYSTEM CLOCK: SYSCLK reference clock Extended drives directly. SYSCLK generated dividing PCICLK SYSCLK frequencies supported 6.25 MHz, 8.33 MHz. SYSCLK divided down version PCICLK. Hardware strapping option SYSCLK tri-stated when PWROK negated. value SYSCLK sampled assertion PWROK: sampled low, clock divisor (for PCI). Otherwise, divisor (for PCI). default value (divideby-4) determined internal pull-up resistor This pullup disabled after reset. IOCHRDY pu8K CHANNEL READY: Resources Extended negate IOCHRDY indicate that additional time (wait-states) required complete cycle. This signal normally high. IOCHRDY input when MPIIX owns Extended agent accessing Extended slave during transfers. High READ: IOR# command Extended slave device that slave drive data Extended data (SD[15:0]). WRITE: IOW# command Extended slave device that slave latch data from Extended data (SD[15:0]). SYSTEM ADDRESS BUS: These address output signals define selection with granularity byte. accesses, only SA[15:0] used. SA[17:0] outputs during memory cycles Extended BIOS range. SA[17:0] unknown state during PCIRST#. SA[15:0] driven durintg cycles Extended Bus. SA[17:16] driven following PCIRST# during cycles Extended Bus.
IOR#
IOW#
High
SA[7:0], DCS1#, DCS3#, DA[2:0] SA[15:8]/ DD[15:8]/ SD[15:8] SA[17,16], PCS#, RTCCS# SD[15:8]/ DD[15:8]/ SA[15:8] MEMR#
Undefined
Undefined
Undefined
Undefined
SYSTEM DATA BUS: SD[15:8] provide higher byte data path devices residing Extended Bus. SD[15:8] available memory devices Extended Bus. MEMORY READ: MEMR# command BIOS memory that drive data onto Extended data bus.
High
82371MX (MPIIX)
Signal Name MEMW# Type pu8K pu8K Tri-state PCIRST# High Description MEMORY WRITE: MEMW# command BIOS memory that latch data from Extended data bus. ZERO WAIT STATES: Extended slave asserts ZEROWS# after address command signals have been decoded indicate that current cycle shortened. 8-bit memory cycle reduced three SYSCLKs. SYSTEM DATA: SD[7:0] provide 8-bit data path devices residing Extended Bus. MPIIX tristates these signals during PCIRST#.
ZEROWS#
SD[7:0]/ DD[7:0]
SDIR
SYSTEM ADDRESS TRANSCEIVER DIRECTION: This signal controls direction '245 transceivers that interface DD[15:0] signals SA[15:8] SD[7:0] signals. Default condition high (transmit).
2.4. Motherboard Device Interface Signals
Signal Name SA17/ PCS# Type PCIRST# Undefined Description PROGRAMMABLE CHIP SELECT. PCS# asserted Extended cycles that generated masters, access address range programmed into PCSC Register. Extended buffer signals enabled when chip select asserted (i.e., assumed that peripheral that selected this resides Extended Bus). PCS# used control isolation buffer Plug-n-Play port isolation buffer. BIOS CHIP SELECT: BIOSCS# asserted during read write accesses BIOS. BIOSCS# driven combinatorially from Extended addresses SA[17:0], except during DMA. During cycles, BIOSCS# generated. KEYBOARD CONTROLLER CHIP SELECT: KBCS# asserted during read write accesses locations 60h, 62h, 64h, 66h. cycles, KBCS# never asserted. REAL TIME CLOCK CHIP SELECT: RTCCS# asserted during read write accesses location 71h, 73h, 75h, 77h. RTCCS# tied pair external gates generate real time clock read write command signals.
BIOSCS#
Undefined
KBCS#
Undefined
SA16/ RTCCS#
Undefined
82371MX (MPIIX)
Signal Name RTCALE/ SMOUT4 Type PCIRST# High Description REAL TIME CLOCK ADDRESS LATCH: RTCALE used latch appropriate memory address into RTC. write port 70h, 72h, 74h, with appropriate memory address that will written read from, causes RTCALE asserted. RTCALE asserted based IOW# falling remains asserted SYSCLKs. SPEAKER DRIVE: SPKR signal output counter
SPKR
3.3V pu50K
OSCILLATOR: 14.31818 clock signal. used internal 8254 Timer. NUMERIC COPROCESSOR ERROR: This signal tied coprocessor error signal CPU. IGNNE# only used MPIIX coprocessor error reporting function enabled Enable Register. FERR# asserted, MPIIX generates internal IRQ13 interrupt controller unit. MPIIX then asserts INTR output CPU. FERR# also used gate IGNNE# signal ensure that IGNNE# asserted unless FERR# active. FERR# weak internal pull-up used ensure high level when coprocessor error function disabled. High IGNORE ERROR: This signal connected ignore error CPU. IGNNE# only used MPIIX coprocessor error reporting function enabled Enable Register. FERR# asserted, indicating coprocessor error, write Coprocessor Error Register (F0h) causes IGNNE# asserted. IGNNE# remains asserted until FERR# negated. FERR# asserted when Coprocessor Error Register written, IGNNE# signal asserted. Alternative MASK: This MPIIX output externally OR'd with A20gate from generate A20M# CPU. A20M# used emulate Mbyte wraparound.
FERR#
IGNNE#
3.3V
ALTA20M
82371MX (MPIIX)
2.5. Signals
Signal Name MDRQ[2:0]/ EXTEVNT# Type pd50K High PCIRST# Description MOTHERBOARD DEVICE REQUEST: These signals connected internally DREQ[3:0,7:5]. Each pair request/acknowledge signals controlled separate register. MOTHERBOARD DEVICE ACKNOWLEDGE: These signals connected internally DACK[3:0,7:5]. Each pair request/acknowledge signals controlled separate register. MDAK1 MDAK2 both enabled re-load Local Standby Timer audio device. REQUEST DREQ2 used floppy disk controller request service from MPIIX's controller. inactive active edges assumed asynchronous. request must remain active until appropriate DACK2# signal asserted. High ACKNOWLEDGE DACK2# indicates that request service been granted MPIIX. This line should used decode slave device with IOR# IOW# line indicate selection. TERMINAL COUNT: MPIIX asserts slaves terminal count indicator. MPIIX asserts after address been output, byte count expires with that transfer. When channels use, negated (low).
MDAK[2:0]#/ PAD#
DREQ2
pu50K
DACK2#
Tri-state
2.6. Interrupt Controller Signals
Signal Name IRQ[15,14, 11:9,7:3,1] Type pu8K PCIRST# Description INTERRUPT REQUEST: signals provide both system board components docking station Extended devices with mechanism asynchronously interrupting CPU. assertion mode these inputs depends programming ELCR Registers. IRQ1 well IRQ[8#,2,0] internal IRQ13) programmable through ELCR Registers. These IRQs always active high edge triggered. internal flip-flop latches low-to-high transition IRQ1. MPIIX continues generate internal IRQ1 8259 core until PCIRST# read access port 60h. active input must remain asserted until after interrupt acknowledged. negated before this time, DEFAULT IRQ7 occurs when acknowledges interrupt.
82371MX (MPIIX)
Signal Name IRQ8# Type 5/3V pu8K CMOS PCIRST# Description INTERRUPT REQUEST EIGHT SIGNAL: IRQ8# always active edge triggered interrupt input (i.e. this interrupt modified software). This signal monitored power `Resume Well' circuitry during suspend. IRQ8# must remain asserted until after interrupt acknowledged. input goes inactive before this time, DEFAULT IRQ7 will occur when acknowledges interrupt. IRQ12/M pu8K INTERRUPT REQUEST MOUSE INTERRUPT: addition providing standard interrupt function (see IRQ[15,14,11:9,7:3,1] signal description), this programmed (via Enable Register) provide mouse interrupt function. When mouse interrupt function selected, low-to-high transition this signal latched MPIIX INTR generated IRQ12. internal IRQ12 interrupt continues generated until PCIRST# read access address 60h. After PCIRST#, this signal provides standard IRQ12 function. MIRQ MOTHERBOARD DEVICE INTERRUPT REQUEST: MIRQ signal internally connected interrupts IRQ[15,14,12:9,7:3]. MIRQ line PIRQx# steered same interrupt, device connected MIRQx should produce active high, level interrupts. MIRQ line steered given input internal 8259, corresponding masked, unless Route Control register programmed allow interrupts shared. This should only done device connected MIRQ line device connected line both produce active high, level interrupts. PIRQ[A,B]# pu8K 3.3V 3.3V PROGRAMMABLE INTERRUPT REQUEST: PIRQx# signals shared with interrupts IRQ[15,14,12:9,7:3] described Interrupt Steering section. Each PIRQx# line separate Route Control Register. INTERRUPT: INTR driven MPIIX signal that interrupt request pending needs serviced. interrupt controller must programmed following PCIRST# ensure that INTR known state. NON-MASKABLE INTERRUPT: used force nonmaskable interrupt CPU. MPIIX generates when SERR# asserted, depending Status Control Register programmed.
INTR
82371MX (MPIIX)
2.7. System Power Management (SMM) Signals
Signal Name SMI# Type 3.3V 3.3V 5/3V CMOS pu50K PCIRST# High Description SYSTEM MANAGEMENT INTERRUPT: SMI# active synchronous output that asserted MPIIX response many enabled hardware software events. During Reset (INIT CPURST), this signal negated. STOP CLOCK: STPCLK# active synchronous output that asserted MPIIX response many hardware software events. STPCLK# connects directly synchronous PCICLK. SUSPEND STATUS: This output signal used switch power non-critical devices during suspend. Activation this signal typically last step code. SYSTEM ACTIVITY: This input signal used system devices such bridge chips indicate system activity that visible MPIIX power management logic. This signal, enabled through setup software, used MPIIX prevent system from entering idle state. SUSPEND RESUME BUTTON: This signal enabled generates SMI# request. SRBTN# monitored power "Resume Well" circuitry during suspend. This signal must always driven valid logic level. BATTERY LOW: BATLOW# Indicates that battery power low. Assertion this signal triggers SMI, enabled. This signal monitored power "Resume Well" circuitry during suspend. MPIIX programmed prevent resume operation when BATLOW# signal active. This signal must always driven valid logic level. Once asserted, this signal must remain asserted until SMI# generated. RESUME RESET: This signal acts reset power "Resume Well" circuitry. This signal must always driven valid logic level. High SYSTEM MANAGEMENT OUTPUT ENABLES: These programmable outputs connected control power circuits various devices system. SMOUT5 configured generate DISK Output Enable. SMOUT4 configured generate RTCALE. RING INDICATE: modem connected port will asserts this signal wake suspended system. This signal monitored power "Resume Well" circuitry during suspend.
STPCLK#
High
SUSTAT#
High
SYSACT#
SRBTN#
5/3V CMOS
BATLOW#
5/3V CMOS
RSMRST#
5/3V CMOS
SMOUT[5:0]/ DOE#, RTCALE
COMRI#
5/3V pu50K CMOS
82371MX (MPIIX)
Signal Name EXTSMI# Type 5/3V pu8K CMOS PCIRST# Description EXTERNAL SYSTEM MANAGEMENT INTERRUPT: EXTSMI# falling edge triggered input MPIIX indicating that external device requesting system enter mode. When enabled, level EXTSMI# will result assertion SMI# signal. EXTSMI# asynchronous input should asserted minimum µsec. EXTERNAL EVENT (EXTEVNT#): EXTEVNT# signal allows events detected external logic used BSTCLK Events CLKTHL Break Events. MDRQ[2] multiplexed with EXTEVNT# signal. confguration selects which signal enabled pin. power default MDRQ[2] signal. High Peripheral Access Decode: PAD# signal asserted MPIIX when memory address decoded same address range defined Peripheral Access Detect Tables enabled Peripheral Access Decode Enable register. MPIIX does have target cycle PAD# signal asserted. MDAK2# multiplexed with PAD# signal. configuration selects which signal enabled pin. power default MDAK2# signal.
EXTEVNT#/ MDRQ2
pd50K
PAD# MDAK2#
2.8. System Clock Reset Signals
Signal Name HCLK Type PCIRST# Description HOST CLOCK: Main system clock used create clocks PCI, MTSC, MTDP, external cache. CLOCK: PCICLK provides timing transactions Bus. other signals sampled rising edge PCICLK, timing parameters defined with respect this edge. frequencies 25-33 supported. Active HOST CLOCK OUT: Must buffered provide CPU, MTSC, TDP, external cache clocks.
PCICLK
HCLKO
3.3V 5/3V CMOS
PCICLKO
Active
CLOCK OUTPUT: Synchronous divide-by-2 HCLK. Must buffered provide fully loadable clock. REAL TIME CLOCK INPUT.
RTCCLK
82371MX (MPIIX)
Signal Name RTCCLKO Type 5/3V CMOS 5/3V CMOS PCIRST# Active Description REAL TIME CLOCK OUTPUT: Gated RTCCLK MTSC suspend refresh operation.
SYSCLK PWROK
SYSTEM CLOCK: Extended Interface Section. POWER When asserted, PWROK indication MPIIX that power PCICLK have been stable least PWROK driven asynchronously. When PWROK negated, MPIIX asserts CPURST, PCIRST# RSTDRV. When PWROK asserted, MPIIX negates CPURST, PCIRST#, RSTDRV. High RESET: MPIIX asserts CPURST reset CPU. MPIIX asserts CPURST during power-up when hard reset sequence initiated through Register. CPURST driven synchronously rising edge PCICLK. hard reset initiated through register, MPIIX resets it's internal registers default state. RESET: MPIIX asserts PCIRST# reset devices that reside Bus. MPIIX asserts PCIRST# during power-up when hard reset sequence initiated through Register. PCIRST# driven inactive minimum after PWROK driven active. PCIRST# driven active minimum when initiated through Register. PCIRST# driven asynchronously relative PCICLK. INITIALIZATION: MPIIX asserts INIT detects shut down special cycle soft reset initiated Register (0CF9h). RESET DRIVE: MPIIX asserts this signal during hard reset during power-up reset Extended devices. RSTDRV also asserted minimum hard reset been programmed Register.
CPURST
3.3V
PCIRST#
INIT
3.3V
High
RSTDRV
High
2.9. Test Signals
Signal Name TESTIN# Type 3.3V PCIRST# Description TEST INPUT: Test signal used tri-state MPIIX outputs.This input sampled assertion PWROK.
82371MX (MPIIX)
3.0. REGISTER DESCRIPTION
There groups MPIIX internal registersPCI Configuration Registers Compatible Registers. These registers discussed this section. Some MPIIX registers contain reserved bits. Software must deal correctly with fields that reserved. reads, software must appropriate masks extract defined bits rely reserved bits being particular value. writes, software must ensure that values reserved positions preserved. That values reserved positions must first read, merged with values other positions then written back. addition reserved bits within register, MPIIX contains address locations configuration space that marked "Reserved" (Table 3.1). MPIIX responds accesses these address locations completing Host cycle. Software should write reserved MPIIX configuration locations devicespecific region (above address offset 3Fh). During hard reset MPIIX sets internal registers predetermined default states. default values indicated individual register descriptions. following notation used describe register access attributes: R/WC Read Only. register read only, writes have effect. Write Only. register write only, reads have effect. Read/Write. register with this attribute read written. Note that individual bits some read/write registers read only. Read/Write Clear. register with this attribute read written. However, write clears (sets corresponding write effect.
3.1. Register Access
Table Table show assignments Configuration Registers Compatible Registers, respectively. masters have access MPIIX internal registers. MPIIX single-function device Bus. MPIIX configuration registers accessed through mechanism defined single-function devies compliance with Local Specification, Revision 2.0. configuration registers only accessed masters. configuration cycles, DEVSEL# function IDSEL AD[1:0]. DEVSEL# selected during configuration cycle only IDSEL active both AD[1:0]=00. IDSEL must connected AD12 (device #1). Configuration cycles that target functions through (AD[10:8]=001b through 111b) ignored (DEVSEL# asserted). Compatible Registers (e.g., registers, timer/counter registers, interrupt registers, X-Bus registers, registers) accessed through space normal fashion. master accesses Compatible Registers bits. MPIIX will only respond least significant byte (see section Functional Description section 16-bit register response). writes other bytes will loaded reads other bytes have invalid data. There power management registers located normal space. These registers accessed masters) with 8-bit accesses. other power management registers located configuration space. general, accesses from masters internal MPIIX registers broadcast Extended bus. Exceptions this general rule read write accesses locations 60h, 70-76h, F0h, write accesses ports 80h, 84-86h, 88h, 8C-8Eh. These accesses broadcast Extended Bus.
82371MX (MPIIX)
Table Configuration Registers Configuration Offset 00-01h 02-03h 04-05h 06-07h 09-0Bh 0C-0Dh 0F-48h 4A-4Bh 50-5Fh 60-61h 62-69h 6A-6Bh 6C-6Dh 6E-6Fh 71-75h 76-78h 79-7Dh 81-87h 8A-8Dh 8E-8Fh 92-93h 94-95h 96-97h 98-99h Mnemonic CLASSC HEDT SPPE ECRT BIOSE FDCE PIRQRC[A,B] MSTAT IDETIM MIRQRC MDMARC AUDIOE DMADS PCIDMAE PCIDMAA PCIDMAB PMAC[1:0] PMAM[1:0] PARE PCSC PAC1 PAC2 PAC3 PAMA PAMB Register Vendor Identification Device Identification Command Device Status Revision Identification Class Code Reserved Header Type Reserved Serial Parallel Port Enable Reserved Extended Controller Recovery Timer Reserved BIOS Enable Enable Reserved PIRQ[A,B]# Route Control Reserved Miscellaneous Status Timing Modes Reserved Motherboard Route Control Reserved Motherboard Route Control Reserved Audio Enable CH[7:5] Address Size Enable Reserved Expansion Expansion Programmable Memory Address Control Programmable Memory Address Mask Programmable Address Range Enable Reserved Programmable Chip Select Control Programmable Address Control Programmable Address Control Programmable Address Control Programmable Address Mask Programmable Address Mask Register Access R/WC
82371MX (MPIIX)
Configuration Offset 9C-9Dh 9E-9Fh A0h-A1h A2h-A3h A5-A7h A8h-A9h AC-ADh C4-C5h C9-CBh Mnemonic IOCA PAC4 PAC5 PAMC PADE[2:0] LTADEV3 LTMDEV3 LTSMIE LTSMIS LSBSMIE LSBTRE LSBSMIS LSBTIDE LSBTAUD LSBTCOM LSBTDEV1 LSBTDEV2 LSBTDEV3 SESMIT SUSSMIT GSBTMR CLKTSBYT SYSMGNTC SYSSMIE MISCSMIE GSMIE SYSSMIS MISCSMIS GSMIS SUSRSMC1 SUSRSMC2 SMOUTC Register Configuration Address Reserved Programmable Address Control Programmable Address Control Programmable Address Mask Peripheral Access Detect Enable Local Trap Address Device Local Trap Mask Device Local Trap Enable Reserved Local Trap Status Reserved Local Standby Enable Local Standby Timer Reload Enable Local Standby Status Reserved Local Standby Timer Idle Local Standby Timer Audio Idle Local Standby Timer Idle Reserved Local Standby Timer Device Idle Local Standby Timer Device Idle Local Standby Timer Device Idle Reserved Software/EXTSMI# Delay Timer Suspend Delay Timer Global Standby Timer Clock Throttle Standby Timer System Mangement Control System Enable Miscellaneous Enable Global Enable Reserved System Status Miscellaneous Status Global Status Reserved Suspend/Resume Control Suspend/Resume Control SMOUT Control Reserved Register Access
82371MX (MPIIX)
Configuration Offset DB-DFh E1-E3h E4-EAh EC-F2h F3-FFh Mnemonic SYSEVNTE0 SYSEVNTE1 SYSEVNTE2 BSTCLKT CLKC STPCLKLT STPCLKHT STPBRKE0 STPBRKE1 STPBRKE2 SHDW BSTCLKEE[6:0] CLKTHLBRKEE[6:0] Register System Event Enable System Event Enable System Event Enable Burst Count Timer Clock Control Reserved STPCLK# Timer STPCLK# High Timer Stop Break Event Enable Stop Break Event Enable Stop Break Event Enable Reserved Shadow Register Reserved Burst Clock Event Enable Reserved Clock Throttle Break Event Enable Reserved Register Access description
Table ISA-Compatible Registers
Address FEDC 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0020h 0021h 0040h 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Address BA98 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 7654 000x 000x 000x 000x 000x 000x 000x 000x 000x 000x 000x 000x 000x 000x 000x 000x 001x 001x 010x 3210 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 xx00 xx01 0000 DMA1 Base Current Address DMA1 Base Current Count DMA1 Base Current Address DMA1 Base Current Count DMA1 Base Current Address DMA1 Base Current Count DMA1 Base Current Address DMA1 Base Current Count DMA1 Status(r) Command(w) register DMA1 Write Request register DMA1 Write Single Mask DMA1 Write Mode register DMA1 Clear Byte Pointer DMA1 Master Clear DMA1 Clear Mask register DMA1 Read/Write Mask Register Bits Control register Mask register Timer Counter Counter Count Type Name
82371MX (MPIIX)
Address FEDC 0041h 0042h 0043h 0060h1 0061h 0070h1 0080h2 0081h 0082h 0083h 0084h2 0085h2 0086h2 0087h 0088h2 0089h 008Ah 008Bh 008Ch2 008Dh2 008Eh2 008Fh 0092h 00A0h 00A1h 00B2h 00B3h 00C0h 00C2h 00C4h 00C6h 00C8h 00CAh 00CCh 00CEh 00D0h 00D2h 00D4h 00D6h 00D8h 00DAh 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Address BA98 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 7654 010x 010x 010x 0110 0110 0111 100x 100x 1000 100x 100x 100x 100x 100x 100x 100x 100x 100x 100x 100x 100x 100x 1001 101x 101x 1011 1011 1100 1100 1100 1100 1100 1100 1100 1100 1101 1101 1101 1101 1101 1101 3210 0001 0010 0011 0001 0xx0 0000 0001 0010 0011 0100 0101 0110 0111 0100 1001 1010 1011 1100 1101 1110 1111 0010 xx00 xx01 0010 0011 000x 001x 010x 011x 100x 101x 110x 111x 000x 001x 010x 011x 100x 101x
Type
Name
Timer Counter Counter Count Timer Counter Counter Count Timer Counter Command Mode register Reset XBus IRQ12/M IRQ1 Status Control CMOS Address Mask reg. Page Register (Reserved) Channel Page register Channel Page register Channel Page register Page Register (Reserved) Page Register (Reserved) Page Register (Reserved) Channel Page register Page Register (Reserved) Channel Page register Channel Page register Channel Page register Page Register (Reserved) Page Register (Reserved) Page Register (Reserved) page Register Refresh System Control Port Control register Mask register Advanced Power Management Control Port Advanced Power Management Status Port DMA2 Base Current Address DMA2 Base Current Count DMA2 Base Current Address DMA2 Base Current Count DMA2 Base Current Address DMA2 Base Current Count DMA2 Base Current Address DMA2 Base Current Count DMA2 Status(r) Command(w) register DMA2 Write Request register DMA2 Write Single Mask DMA2 Write Mode register DMA2 Clear Byte Pointer DMA2 Master Clear
82371MX (MPIIX)
Address FEDC 00DCh 00DEh 00F0h1 04D0h 04D1h 0CF9h 0000 0000 0000 0000 0000 0000
Address BA98 0000 0000 0000 0100 0100 1100 7654 1101 1101 1111 1101 1101 1111 3210 110x 111x 0000 0000 0001 1001
Type
Name
DMA2 Clear Mask register DMA2 Read/Write Mask Register Bits Coprocessor Error INT-1 edge/level control register INT-2 edge/level control register Control Register
Note: Accesses these locations always broadcast Extended Bus. Writes these locations always broadcast Extended Bus.
3.2. Configuration Registers
3.2.1. VID-VENDOR IDENTIFICATION REGISTER 01-00h 8086h Read Only
Address Offset: Default Value: Attribute:
Register contains vendor identification number. This register, along with Device Identification Register, uniquely identifies device. Writes this register have effect. 15:0 Description Vendor Identification Number. This 16-bit value assigned Intel.
3.2.2.
DID-DEVICE IDENTIFICATION REGISTER 03-02h 1234h Read Only
Address Offset: Default Value: Attribute:
Register contains device identification number. This register, along with Register, define MPIIX. Writes this register have effect. 15:0 Description Device Identification Number. This 16-bit value assigned MPIIX.
82371MX (MPIIX)
3.2.3. COM-COMMAND REGISTER 05-04h 0007h Read/Write
Address Offset: Default Value: Attribute:
This 16-bit register provides basic control over MPIIX's ability respond cycles. 15:10 Reserved. Read Fast Back-to-Back Enable (FBE). Reserved, read SERR# Enable. Reserved, read Reserved. Read Postable Memory Write Enable (PMWE). This will always read Special Cycle Enable (SCE). 1=Enable (MPIIX recognizes special cyclesshutdown stop grant); 0=Disable (MPIIX ignores special cycles). Master Enable (BME). MPIIX does support disabling master capability. This always reads Memory Space Enable (MSE). MPIIX does support disabling access main memory. This read Space Enable (IOSE). MPIIX does support disabling response cycles. This read Description
3.2.4.
DS-DEVICE STATUS REGISTER 06-07h 0280h Read/Write Clear
Address Offset: Default Value: Attribute:
16-bit status register that reports occurrence master-abort MPIIX targetabort when MPIIX master. register also indicates MPIIX DEVSEL# signal timing. Description Parity Error (Not Implemented). Read SERR# Status (Not Implemented). Read Master-Abort Status (MA): When MPIIX, master, generates master-abort, Software sets writing this location. Received Target-Abort Status (RTA): When MPIIX master receives target-abort, this Software resets writing this location. Signaled Target-Abort Status (STA): This when MPIIX Extended bridge function targeted with transaction that MPIIX terminates with target abort. Software resets writing this location.
82371MX (MPIIX)
10:9 Description DEVSEL# Timing Status (DEVT): DEVT=01. MPIIX always generates DEVSEL# with medium timing Extended functions. This DEVSEL# timing does include configuration cycles. PERR# Response (Not Implemented). Read Fast Back BackRO. This read indicating Master that MPIIX, target, capable accepting fast back-to-back transactions. Reserved. Read
3.2.5.
RID-REVISION IDENTIFICATION REGISTER Refer stepping information Read Only
Address Offset: Default Value: Attribute:
This 8-bit register contains device stepping information. Writes this register have effect. Description Revision Byte: register hardwired default value.
3.2.6.
CLASSC-CLASS CODE REGISTER 09-0Bh 068000h Read Only
Address Offset: Default Value: Attribute:
This register contains device programming interface information related Sub-Class Code Base Class Code definition MPIIX. This register also identifies Base Class Code function sub-class relation Base Class Code. 23:16 15:8 Description Base Class Code (BASEC). 06h=PCI Bridge device. Sub-Class Code (SCC). 01h=Other bridge device (ISA-like Extended Bus). Programming Interface (PI). 00h=No programming interface defined.
82371MX (MPIIX)
3.2.7. HEDT-HEADER TYPE REGISTER Read Only
Address Offset: Default Value: Attribute:
HEDT Register identifies MPIIX single-function device. Description Device Type (DEVICET): 00h=single-function device.
3.2.8.
SPPE-SERIAL PARALLEL PORT ENABLE REGISTER Read/Write
Address Offset: Default Value: Attribute:
This register enables/disables accesses Serial Ports Parallel Ports Extended Bus. Reserved. LPT3 Enable 1=Enable (forward accesses 0278-027Fh 0678-067Bh Extended Bus). 0=Disable (confine PCI). LPT2 Enable. 1=Enable (forward accesses 0378-037Fh 0778-077Bh Extended Bus). 0=Disable (confine PCI). LPT1 Enable. 1=Enable (forward accesses 03BC-03BFh 07BC-07BFh Extended Bus). 0=Disable (confine PCI). COM4 Enable. 1=Enable (forward accesses 02E8h-02EFh Extended Bus). 0=Disable (confine PCI). COM3 Enable. 1=Enable (forward accesses 03E8h-03EFh Extended Bus). 0=Disable (confine PCI). COM2 Enable. 1=Enable (forward accesses 02F8h-02FFh Extended Bus). 0=Disable (confine PCI). COM1 Enable. 1=Enable (forward accesses 03F8h-03FFh Extended Bus). 0=Disable (confine PCI). Description
82371MX (MPIIX)
3.2.9. ECRT- EXTENDED CONTROLLER RECOVERY TIMER REGISTER Read/Write
Address Offset: Default Value: Attribute:
recovery mechanism MPIIX used additional recovery delay between Master originated 8-bit cycles Extended Bus. MPIIX automatically forces minimum delay SYSCLKs between back-to-back 8-bit cycles Extended bus. This delay measured from rising edge command (IOR# IOW#) falling edge next command delay greater than SYSCLKs required, Extended Recovery Time Register programmed increase delay increments SYSCLKs. additional delay inserted back-toback "sub cycles" generated result byte assembly disassembly. This register defaults 8bit recovery enabled with SYSCLK clock added standard recovery. Reserved. 8-Bit Recovery Enable. 1=Enable recovery time programmed bits [5:3]. 0=Disable recovery times bits [5:3] recovery timing SYSCLKs inserted. 8-Bit Recovery times. When 6=1, this 3-bit field defines recovery time 8-bit I/O. [5:3] SYSCLK (default) [5:3] SYSCLK Description
16-Bit Recovery Enable. Reserved. Read 16-Bit Recovery Times. Reserved. Read
3.2.10. BIOSE BIOS ENABLE REGISTER Address Offset: Default Value: Attribute: Read/Write
This register enables/disables BIOS accesses different segments. This register also controls generation BIOSCS# signal. Description Extended BIOS Enable. When (enabled), master accesses locations FFFC0000h-FFFDFFFFh forwarded Extended BIOSCS# generated. When 7=0, MPIIX does claim cycle generate BIOSCS#. Lower BIOS Enable When (enabled), master accesses locations 0E4000h- 000EFFFFh (and alias forwarded Extended BIOSCS# generated. When 6=0, MPIIX does claim cycle generate BIOSCS#. Lower BIOS Decode Enable When (enabled), master accesses locations 0E0000h-000E3FFFh (and alias forwarded Extended Bus. This region also used Kanji BIOS. When 5=0, MPIIX does claim cycle.
82371MX (MPIIX)
Description Lower BIOS Enable When bit=1 (enabled), master accesses locations 0E0000h- 000E3FFFh (and alias generate BIOSCS#. This region also used Kanji BIOS. When 4=0, MPIIX does generate BIOSCS#. F-SEGMENT BIOS ENABLE: 1=Enable (default). 0=Disable. This enables MPIIX claim cycles F-Segment BIOS. When disabled, MPIIX does claim these cycles. MPIIX should programmed claim cycles F-Segment BIOS after DRAM controller claim cycles shadowed F-Segment. BIOSCS# Write Protect. When (enabled), BIOSCS# asserted BIOS memory read write cycles decoded BIOS region. When 2=0, BIOSCS# only asserted BIOS read cycles (MPIIX does claim write cycle). Reserved.
3.2.11. FDCE-FDC ENABLE REGISTER Address Offset: Default Value: Attribute: Read/Write
This register enables/disables accesses Floppy Disk Extended Bus. This register also enable/disables coprocessor Error Function, IRQ12/Mouse Function, DOE# Disk Output Enable signal (multiplexed with SMOUT5 signal), RTCALE enable signal (multiplexed with SMOUT4 signal). Description Coprocessor Error function Enable. 1=Enable. FERR# input, when asserted, triggers IRQ13 (internal). FERR# also used gate IGNNE# output. IRQ12/M Mouse Function Enable. 1=Mouse function. 0=Standard IRQ12 interrupt function. System Management Output 5/Disk Output Enable. 1=DOE# function SMOUT5/DOE# signal. 0=SMOUT5 function SMOUT5/DOE# (signal reflects logic level SMOUT5 SMOUTC Register). System Management Output 4/RTCALE Enable. 1=RTCALE function SMOUT4/RTCALE signal. 0=SMOUT4 function SMOUT4/RTCALE (signal reflects logic level SMOUT4 SMOUTC Register). Motherboard Disable: 1=PAD# function enabled MDAK2#/PAD# EXTEVNT# function enabled MDRQ2/EXTEVNT# pin. (default)=MDAK2# function enabled MDAK2#/PAD# MDRQ2 function enabled MDRQ2/EXTEVNT# pin. Reserved. Floppy Secondary Address Enable. When (Enable), accesses 0370-0375h 0377h forwarded Extended Bus. When 1=0, MPIIX does claim these cycles. Floppy Primary Address Enable. When (Enable), accesses 03F0-03F5h 03F7h forwarded Extended Bus. When 0=0, MPIIX does claim these cycles.
82371MX (MPIIX)
3.2.12. PIRQRC [A,B]-PIRQX ROUTE CONTROL REGISTERS Address Offset Default Value: Attribute: (PIRQRCA) (PIRQRCB) Read/Write
These registers control routing PIRQ[A,B] inputs interrupt controller. Each PIRQx# independently routed interrupts. Both PIRQx# lines routed same IRQx input. Note, that selected through bits [3:0] must level sensitive mode corresponding ELCR Register. When PIRQ# line routed given input internal 8259, corresponding masked Description Interrupt Routing Enable. 0=enable. 1=disable. Reserved. Read Interrupt Routing: When 7=0, this field selects routing PIRQx interrupt controller interrupt inputs. Bits [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 Routing Reserved Reserved Reserved IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Bits [3:0] 1000 1001 1010 1011 1100 1101 1110 1111 Routing Reserved IRQ9 IRQ10 IRQ11 IRQ12 Reserved IRQ14 IRQ15
3.2.13. MSTAT-MISCELLANEOUS STATUS REGISTER Address Offset: Default Value: Attribute: 6Bh-6Ah xxxx xxxx xxxx x00S (S=Strapping option) Read Only
This register reports hardware strapping options selected Extended clock divisor. 15:3 Description Reserved. Software should rely particular value this field. Reserved. Read Clock Divisor Status: This reports strapping option SYSCLK signal. 1=clock divisor (PCICLK=25 MHz). (default)=Clock divisor (PCICLK=33 MHz). Note that, PCICLK=30 MHz, clock divisor must selected produces SYSCLK MHz.
82371MX (MPIIX)
3.2.14. IDETIM-IDE TIMING REGISTER Address Offset: Default Value: Attribute: 6D-6Ch: Primary/Secondary Channel 0000h Read/Write
This register controls MPIIX's interface selects timing characteristics Local cycle. Description Decode Enable (IDE): When 15=1 (Enable), accesses register blocks (command block control block) forwarded interface. When 15=0, MPIIX does claim cycle. Primary Secondary Address Decode. 0=Primary. 1=Secondary. must decode cycles PCI. IORDY Sample Point (ISP). This field determines number clocks between DIOx# assertion first IORDY# sample point. Bits [13:12] 11:10 Reserved. Recovery Time (RCT). This field determines minimum number clocks between last IORDY# sample point DIOx# strobe next cycle. Bits [9:8] Reserved. Prefetch Posting Enable (PPE1). When this set, prefetch posting data port enabled drive IORDY Sample Point Enable Drive Select (IE1). When IE1=0, IORDY sampling disabled Drive internal IORDY signal forced asserted guaranteeing that IORDY sampled asserted first sample point specified field this register. When IE1=1 currently selected drive (via copy 1x6h) Drive accesses enabled address range sample IORDY. IORDY sample point specified field this register. Number Clocks Number Clocks
13:12
82371MX (MPIIX)
Description Fast Timing Bank Drive Select (TIME1). When TIME1=0, accesses data port enabled address range 16-bit compatible timing local path. When TIME1=1 currently selected drive (via copy 1x6h) Drive then accesses data port enabled address range fast timing bank local path. Accesses data port fast timing only this register (DTE1) Accesses non-data ports enabled address range 8-bit compatible timing local path. Reserved. Prefetch Posting Enable (PPE0). 1=Enable prefetch posting data port drive 0=Disable. IORDY Sample Point Enable Drive Select (IE0). When IE0=0, IORDY sampling disabled Drive internal IORDY signal forced asserted guaranteeing that IORDY sampled asserted first sample point specified field this register. When IE0=1 currently selected drive (via copy 1x6h) Drive accesses enabled address range sample IORDY. IORDY sample point specified field this register. Fast Timing Bank Drive Select (TIME0). When TIME0=0, accesses data port enabled address range 16-bit compatible timing local path. When TIME0=1 currently selected drive (via copy 1x6h) Drive then accesses data port enabled address range fast timing bank local path. Accesses data port fast timing only this register (DTE0) Accesses non-data ports enabled address range 8-bit compatible timing local path.
3.2.15. MIRQRC-MOTHERBOARD DEVICE ROUTE CONTROL REGISTER Address Offset Default Value: Attribute:
This register controls routing MIRQ inputs. MIRQ# routed interrupts. When MIRQ line PIRQ# line steered same interrupt, device connected MIRQ line must active high, level interrupts. this case, corresponding interrupt masked. that motherboard device Route Control Register must programmed Description Interrupt Routing Enable: 0=Enable routing, 1=Disable routing. MIRQ/IRQx Sharing Enable: 0=Disable sharing, 1=Enable sharing. When sharing disabled this register interrupt specified bits [3:0] masked. Interrupt sharing should only enabled when device connected MIRQ line device connected line both produce active high, level interrupts. Reserved. Read 0's.
82371MX (MPIIX)
Description Interrupt Routing: When 7=0, this field selects routing MIRQ interrupt controller interrupt inputs. Bits [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 Routing Reserved Reserved Reserved IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Bits [3:0] 1000 1001 1010 1011 1100 1101 1110 1111 Routing Reserved IRQ9 IRQ10 IRQ11 IRQ12 Reserved IRQ14 IRQ15
3.2.16. MDMARC[2:0]MOTHERBOARD DEVICE ROUTE CONTROL REGISTERS Address Offset Default Value: Attribute: (MDMARC0), (MDMARC1), (MDMARC2),
These registers control routing MDRQ[2:0] MDAK[2:0]# signals DREQ DACK# signals 8237 controllers. When MDRQ/MDAK# pair programmed channel then DREQ2/DACK2# pins masked. more than three Motherboard DMAs used, Motherboard DMAs should programmed different compatible channels. Programming more than Motherboard same compatible channel will result unpredictable device operation. Description Type Buffer Enable (FAST): 1=Enable this channel. 0=Disable. Reserved. Read 0's. Channel select (CHNL): This field selects channel connected MDRQ/MDAK# pair. Bits[2:0] channel Bits[2:0] channel default (disabled)
82371MX (MPIIX)
3.2.17. AUDIOE-AUDIO ENABLE REGISTER Address Offset: Default Value: Attribute: Read/Write
This register enables/disables audio channel and, when enabled, selects address. Description Audio Enable. 1=Enable (forwards accesses address range with base address selected bits [3:2] this register (2x0-2xFh) Extended Bus. 0=Disable. Reserved. Audio Address. These bits select address audio device, when enabled this register Bits [3:2] Address Reserved. 0220h 0230h 0240h 0250h
3.2.18. DMADS-DMA CH[7:5] DATA SIZE REGISTER Address Offset: Default Value: Attribute: Read/Write
This register selects between 8-bit 16-bit device data size channels [7:5]. Description Channel 16/8-Bit Count Words (CH7DS). 1=16-bit, count word. 0=8-bit, count byte. Channel 16/8-Bit Count Words (CH6DS). 1=16-bit, count word. 0=8-bit, count byte. Channel 16/8-Bit Count Words (CH5DS). 1=16-bit, count word. 0=8-bit, count byte. Reserved. Read
82371MX (MPIIX)
3.2.19. PCIDMAE-PCI ENABLE REGISTER Address Offset: Default Value: Attribute: Read/Write
This register selects, channel channel basis, whether device using channel Extended (including proliferation bus). Description PCI/Extended (PCICH7). 1=PCI Bus. 0=Extended Bus. PCI/Extended (PCICH6). 1=PCI Bus. 0=Extended Bus. PCI/Extended (PCICH5). 1=PCI Bus. 0=Extended Bus. Reserved. PCI/Extended (PCICH3). 1=PCI Bus. 0=Extended Bus. PCI/Extended (PCICH2). 1=PCI Bus. 0=Extended Bus. PCI/Extended (PCICH1). 1=PCI Bus. 0=Extended Bus. PCI/Extended (PCICH0). 1=PCI Bus. 0=Extended Bus.
3.2.20. PCIDMA[A,B]PCI EXPANSION REGISTER Address Offset: Default Value: Attribute: (REQA#/GNTA#), (REQB#/GNTB#) (both) Read/Write
Expansion request lines (REQ[A,B]#/GNT[A,B]#) provide expansion support. default value registers selects request/grant signal control expansion device using channel Reserved. Expansion. This provides ability control multiple channels through single request/grant field. When expansion expansion agent required pass channel number arbiter when requesting service using expansion channel passing protocol, thus making channel field "don't care". expansion hardware will then route agent's REQ#/GNT# pair appropriate internal DREQ/DACK# pair, depending value channel number passed Description
82371MX (MPIIX)
Description Channel. This field indicates what Channel signal pair controls. This allows request/grant pair software routable channel. Valid values Channel field are: Bits[3:1] Channel Channel Channel Channel Channel Bits[3:1] Channel Reserved Channel Channel Channel
Note that MPIIX does support PC/PCI REQ#/GNT# pair Masters. program channel field reserved value 100.
3.2.21. PMAC[1:0]-PROGRAMMABLE MEMORY ADDRESS CONTROL REGISTERS Address Offset: Default Value: Attribute: 8A-8Bh (PMAC0), 8C-8Dh (PMAC1) 0000h Read/Write
This register provides memory addresses used Burst Event, Clock Throttle Break Event, Peripheral Access Detect. memory address programmable range between Kbytes Gbyte. memory range programmable between Kbytes Mbytes using Programmable Memory Address Mask (PMAM) registers. Note: memory address must aligned size memory range programmed through PMAM registers. Thus, range Kbytes, memory address range start 16-Kbyte address boundary), memory range Mbytes, memory address range start Mbytes address boundary. Description Memory Address Control (MAC). This field compared against addresses AD[29:14] during memory cycles. upper addresses (AD[31:30]) must zero address decoded.
15:0
82371MX (MPIIX)
3.2.22. PMAM[1:0]-PROGRAMMABLE MEMORY ADDRESS MASK REGISTERS Address Offset: Default Value: Attribute: (PMAM0) (PMAM1) Read/Write
This register defines size memory address range which will decoded MPIIX used signal Burst Event, Clock Throttle Break Event Peripheral Access Detect. starting address determined PMAC register programming. Description Memory Address Mask (MAM). This field provides mask bits that used determine AD[21:14] part decode ignored. Bits [7:0] correspond AD[21:14], respectively. corresponding address used during decode. Split ranges precluded.
3.2.23. PARE-PROGRAMMABLE ADDRESS RANGE ENABLE REGISTER Address Offset: Default Value: Attribute: Read/Write
This register enables/disables address range defined Programmable Address Control Registers (bits[5:1]) PCSC Register (bit When enabled, MPIIX forwards accesses address range specified corresponding PACx/PCSC Registers Extended Bus. When disabled, MPIIX does claim these accesses. This register also enables PCS# assertion accesses enabled PAC1 PAC2 ranges. Description PCS# Enable Programmable Address Range 1=Enable 2=1). 0=Disable. PCS# Enable Programmable Address Range 1=Enable 1=1). 0=Disable. Programmable Address Range Enable. 1=Enable. 0=Disable Programmable Address Range Enable. 1=Enable. 0=Disable Programmable Address Range Enable. 1=Enable. 0=Disable Programmable Address Range Enable. 1=Enable. 0=Disable Programmable Address Range Enable. 1=Enable. 0=Disable PCS# Address Range Enable. 1=Enable. 0=Disable
82371MX (MPIIX)
3.2.24. PCSC-PROGRAMMABLE CHIP SELECT CONTROL REGISTER Address Offset: Default Value: Attribute: 92-93h 0000h Read/Write
This register defines 16-bit address range forwarded Extended and, enabled (via PARE register), generation PCS# signal. Note that PAMA Register selects address range bytes (split range precluded). 15:0 Description Address (PCSADDR). addresses AD[15:0] compared against bits [15:2]. AD[31:16] must address decoded.
3.2.25. PAC[5:1]-PROGRAMMABLE ADDRESS CONTROL REGISTER Address Offset: 94-95hPAC1 A0-A1hPAC4 96-97hPAC2 A2-A3hPAC5 98-99hPAC3 0000h Read/Write
Default Value: Attribute:
This register provides 16-bit address range forwarded Extended Bus, enabled PARE Register. Note that PAM[A,B,C] Register selects address range bytes (split range precluded). 15:0 Description Programmable Address Control (PADDRC). addresses AD[15:0] compared against bits [15:2]. AD[31:16] must address decoded.
3.2.26. PAMA-PROGRAMMABLE ADDRESS MASK REGISTER Address Offset: Default Value: Attribute: Read/Write
This register selects address range bytes (split range precluded) Programmable Address Control Register (PAC1) PCSC Register. bits this register used mask address bits AD[3:0], respectively during decode. Description Programmable Address Control Mask (PAC1MASK). 1=corresponding address used address decode. 0=Corresponding address used address decode. example, mask field=0011 selects 4-byte range. Programmable Chip Select Mask (PCSMASK). 1=corresponding address used address decode. 0=Corresponding address used address decode. example, mask field=0011 selects 4-byte range.
82371MX (MPIIX)
3.2.27. PAMB-PROGRAMMABLE ADDRESS MASK REGISTER Address Offset: Default Value: Attribute: Read/Write
This register selects address range bytes (split range precluded) Programmable Address Control Registers (PAC[3,2]). Description Programmable Address Control Mask (PAC3MASK). 1=corresponding address used address decode. 0=Corresponding address used address decode. example, mask field=0011 selects 4-byte range. Programmable Address Control Mask (PAC2MASK). 1=corresponding address used address decode. 0=Corresponding address used address decode. example, mask field=0011 selects 4-byte range.
3.2.28. IOCA-I/O CONFIGURATION ADDRESS REGISTER Address Offset: Default Value: Attribute: 9C-9Dh Read/Write
This register provides address range forwarded Extended accesses configuration space integrated device. address bits AD[9:1] compared bits [9:1] this register. address bits AD[31:10] must zero decode hit. 15:10 Reserved. Configuration Address (IOCA). This field defines 2-byte address space between Kbyte Kbyte that will forwarded Extended Bus, enabled IOCAE bit. Configuration Address Enable (IOCAE). 1=Enable bits [9:1] this register. 0=Disable (MPIIX does claim these cycles). Description
82371MX (MPIIX)
3.2.29. PAMC-PROGRAMMABLE ADDRESS MASK REGISTER Address Offset: Default Value: Attribute: Read/Write
This register selects address range bytes (split range precluded) Programmable Address Control Registers (PAC[5,4]). Description Programmable Address Control Mask (PAC5MASK). 1=corresponding address used address decode. 0=Corresponding address used address decode. example, mask field=0011 selects 4-byte range. Programmable Address Control Mask (PAC4MASK). 1=corresponding address used address decode. 0=Corresponding address used address decode. example, mask field=0011 selects 4-byte range.
3.2.30. PADE[2:0]-PERIPHERAL ACCESS DETECT ENABLE REGISTERS Address Offset: Default Value: Attribute: A5hPADE0, A6hPADE1, A7hPADE2 Read/Write
This register enables addresses used assert PAD# signal. Setting bits enables corresponding memory address part peripheral activity detection range. address detected enabled peripheral activity range, MPIIX asserts Peripheral Access Detect (PAD#) signal. Setting disables this function. Tables (Section 4.8) provide address range where associated function determined. Bits Audio-E. Audio-D. Audio-C. Audio-B. Audio-A. Parallel Port Parallel Port Parallel Port PADE2 COM4. COM3. COM2. COM1. FDC, Secondary Drive. FDC, Primary Drive. IDE, Secondary Drive. IDE, Primary Drive. PADE1 PMAC1. PMAC0. PAC5. PAC4. PAC3. PAC2. PAC1. PCSC. PADE0
82371MX (MPIIX)
3.2.31. LTADEV3-Local Trap Address Device Register Address Offset: Default Value: Attribute: A8h-A9h Read/Write
This register contains 16-bit trap address device address range this trap address selected LTMDEV3 Register. 15:0 Description LTRP_ADDR_DEV3. Bits [15:0] correspond address bits AD[15:0]. Note that AD[31:16] must match.
3.2.32. LTMDEV3-Local Trap Mask Device Register Address Offset: Default Value: Attribute: Read/Write
This register selects port access that will trapped. register also selects trap address range bytes Device (split range precluded). Description LTRP_COM_SEL. These bits select port accesses that will trapped. When written access corresponding Local Trap Address will cause synchronous SMI#. Bits COM4 COM3 COM2 COM1 Port Address 02E8h-02EFh 03E8h-03EFh 02F8h-02FFh 03F8h-03FFh
LTRP_MASK_DEV3. This field selects address trap range Device 1=corresponding address used address decode. 0=Corresponding address used address decode. example, mask field=0011 selects 4-byte range.
3.2.33. LTSMIE-Local Trap Enable Register Address Offset: Default Value: Attribute: Read/Write
This register enables local address trap cause synchronous accesses corresponding enabled trap address range. address range each defined Section 4.8.3.2, Access Ranges. Reserved. LTRP_SMI_EN_IDE. 1=Enable. 0=Disable. Description
82371MX (MPIIX)
Description LTRP_SMI_EN_AUD. 1=Enable. 0=Disable. LTRP_SMI_EN_COM. 1=Enable. 0=Disable. (The address range defined LTMDEV3 Register.) LTRP_SMI_EN_DEV3. 1=Enable. 0=Disable. (The address range defined LTADEV3 LTMDEV3 Registers.) LTRP_SMI_EN_DEV2. 1=Enable. 0=Disable. (The address range defined PAC1 PAMA Registers.) LTRP_SMI_EN_DEV1. 1=Enable. 0=Disable. (The address range defined PCSC PAMA Registers.)
3.2.34. LTSMIS-Local Trap Status Register Address Offset: Default Value: Attribute: Read/Write
This register indicates that access corresponding enabled local trap caused SMI# request. traps enabled LTSMIE Register. MPIIX sets request status bits Software clears writing MPIIX setting same time that software setting address range each defined Section 4.8.3.2, Access Ranges. Reserved. LTRP_STAT_IDE. LTRP_STAT_AUD. LTRP_STAT_COM. address range defined LTMDEV3 Register. LTRP_STAT_DEV3. address range defined LTADEV3 LTMDEV3 Registers. LTRP_STAT_DEV2. address range defined PAC1 PAMA Registers. LTRP_STAT_DEV1. address range PCSC PAMA Registers. Description
3.2.35. LSBSMIE-Local Standby Enable Register Address Offset: Default Value: Attribute: Read/Write
When this register corresponding Local Standby timer reloaded with initial count begins count down. access corresponding local trap address reloads timer. When timer expires, SMI# generated, enabled GSMIE Register. When corresponding timer does count down. address range each defined Section 4.8.3.2, Access Ranges. Description
82371MX (MPIIX)
Reserved. LSTBY_SMI_EN_IDE. LSTBY_SMI_EN_AUD. LSTBY_SMI_EN_COM. address range defined LTMDEV3 Register. LSTBY_SMI_EN_DEV3. address range defined LTADEV3 LTMDEV3 Registers. LSTBY_SMI_EN_DEV2. address range defined PAC1 PAMA Registers. LSTBY_SMI_EN_DEV1. address range PCSC PAMA Registers. Description
3.2.36. LSBTRE-Local Standby Timer Reload Enable Register Address Offset: Default Value: Attribute: Read/Write
This register enables/disables local standby timer reloading. When access made enabled address ranges selected bits [7:2] (i.e., IDE, Audio, port, Device [3:1]), local standby timers reloaded with their initial count value. This register also enables/disables motherboard activity MDAK[2,1] reload Audio Local Standby Timer. Description LSTBY_RLD_IDE Enable. 1=Enable. 0=Disable. LSTBY_RLD_AUD Enable. 1=Enable. 0=Disable. LSTBY_RLD_COM Enable. 1=Enable. 0=Disable. LSTBY_RLD_DEV3 Enable. 1=Enable. 0=Disable. LSTBY_RLD_DEV2 Enable. 1=Enable. 0=Disable. LSTBY_RLD_DEV1 Enable. 1=Enable. 0=Disable. MDAK2 Enable. 1=Enable. 0=Disable. MDAK1 Enable. 1=Enable. 0=Disable.
82371MX (MPIIX)
3.2.37. LSBSMIS-Local Standby Status Register Address Offset: Default Value: Attribute: Read/Write
bits this register indicate that corresponding Local Standby Timer expired caused SMI. generation timers globally enabled GSMIE Register individually enabled LSBMIE Register. MPIIX sets request bits Software clears writing MPIIX setting same time that software setting Reserved. LSTBY_STAT_IDE. 1=IDE Local Standby Timer generated SMI#. LSTBY_STAT_AUD. 1=Audio Local Standby Timer generated SMI#. LSTBY_STAT_COM. 1=COM Port Local Standby Timer generated SMI#. LSTBY_STAT_DEV3. 1=Device Local Standby Timer generated SMI#. LSTBY_STAT_DEV2. 1=Device Local Standby Timer generated SMI#. LSTBY_STAT_DEV1. 1=Device Local Standby Timer generated SMI#. Description
3.2.38. LSBTIDE-Local Standby Timer Register Address Offset: Default Value: Attribute: Read/Write
This register provides idle time interval generating SMI#. eight second internal clock provides idle timeout range sec. minutes. timer frozen SYSMGNTC Register. timer reloaded with count value programmed into this register when there access enabled device address, individual enable LSBSMIE Register, access device enabled LSBTRE register. Description LSTBY_TMR_IDE. This field contains 8-bit value Local Standby Timer. illegal programmed value.
82371MX (MPIIX)
3.2.39. LSBTAUD-Local Standby Audio Timer Register Address Offset: Default Value: Attribute: Read/Write
This register provides idle time interval generating SMI#. eight second internal clock provides idle timeout range sec. minutes. timer individually enabled LSBSMIE Register. timer frozen SYSMGNTC Register. timer reloaded with count value programmed into this register when there access enabled device address, individual enable LSBSMIE Register, access device enabled LSBTRE register. Description LSTBY_TMR_AUD. This field contains 8-bit count value AUDIO Local Standby Timer. illegal programmed value.
3.2.40. LSBTCOM-Local Standby Timer Register Address Offset: Default Value: Attribute: Read/Write
This register provides idle time interval generating SMI#. eight second internal clock provides idle timeout range sec. minutes. timer individually enabled LSBSMIE Register. timer frozen SYSMGNTC Register. timer reloaded with count value programmed into this register when there access enabled device address, individual enable LSBSMIE Register, access device enabled LSBTRE register. Description LSTBY_TMR_COM. This field contains 8-bit count value port Local Standby Timer. illegal programmed value.
3.2.41. LSBTDEV1-Local Standby Device Timer Register Address Offset: Default Value: Attribute: Read/Write
This register provides idle time interval generating SMI#. eight second internal clock provides idle timeout range sec. minutes. timer individually enabled LSBSMIE Register. timer frozen SYSMGNTC Register. timer reloaded with count value programmed into this register when there access enabled device address, individual enable LSBSMIE Register, access device enabled LSBTRE register. Description LSTBY_TMR_DEV1. This field contains 8-bit count value DEVICE (PCS#) Local Standby Timer. (Programmable Chip Select, PCS#). illegal programmed value.
82371MX (MPIIX)
3.2.42. LSBTDEV2-Local Standby Device Timer Register Address Offset: Default Value: Attribute: Read/Write
This register provides idle time interval generating SMI#. eight second internal clock provides idle timeout range sec. minutes. timer individually enabled LSBSMIE Register. timer frozen SYSMGNTC Register. timer reloaded with count value programmed into this register when there access enabled device address, individual enable LSBSMIE Register, access device enabled LSBTRE register. Description LSTBY_TMR_DEV2. This field contains 8-bit count value Device Local Standby Timer. (Programmable Address Range illegal programmed value.
3.2.43. LSBTDEV3-Local Standby Device Timer Register Address Offset: Default Value: Attribute: Read/Write
This register provides idle time interval generating SMI#. eight second internal clock provides idle timeout range sec. minutes. timer individually enabled LSBSMIE Register. timer frozen SYSMGNTC Register. timer reloaded with count value programmed into this register when there access enabled device address, individual enable LSBSMIE Register, access device enabled LSBTRE register. Description LSTBY_TMR_DEV3. This field contains 8-bit count value Device Local Standby Timer. (LTADEV3 Register). illegal programmed value.
3.2.44. SESMIT-Software/EXTSMI# Delay Timer Register Address Offset: Default Value: Attribute: Read/Write
This timer enabled GSMIE Register. When enabled, timer provides delay between software generated SMI# (setting SWEXT_SMI_EN_SW GSMIE Register) generation EXTSMI# enabled SYSSMIE Register), generation SMI# CPU. msec internal clock provides time delay range msec msec. timer reloaded when enabled system event occurs (see SYSEVNTE[2:0] Registers). When this timer generates SMI, global status this timer (GSMIS Register) individual status bit(s) source that caused set. Description SWEXT_SMI_DLY_TMR. This field contains 8-bit count value Software EXTSMI# Delay Timer. illegal programming count.
82371MX (MPIIX)
3.2.45. SUSSMIT-Suspend Delay Timer Register Address Offset: Default Value: Attribute: Read/Write
This timer generates delay between hardware generation suspend resume (asserting SRBTN# signal) battery indication (asserting BATLOW# signal) corresponding generation. msec internal clock provides time delay range msec sec. SRBTN# BATLOW# signals activate this delay timer, there individual enable bits must MISCSMIE Register. Note that generation BATLOW# bypass this delay timer immediately generate programming this feature SUSRSMC1 Register. Description SUSP_SMI_DLY_TMR. This field contains 8-bit count value Suspend/Resume Button SRBTN# Battery BATLOW# Delay Timer. illegal programming count.
3.2.46. GSBTMR-Global Standby Timer Register Address Offset: Default Value: Attribute: Read/Write
This register provides global standby timer interval generating SMI#. eight second internal clock provides standby timeout range minutes. This timer enabled GSMIE Register. timer reloaded when enable set, timer expires, local standby timer reloaded, enabled system event specfied SYSEVNTE[2:0] Registers. status GSMIS Register indicates that this timer generated SMI. Description GSTBY_TMR. This field contains 8-bit count value Global Standby Timer. illegal programmed value.
3.2.47. CLKTHSBYT Clock Throttle Standby Timer Register Address Offset: Default Value: Attribute: Read/Write
This register provides count STPCLK# negation CLKTHL Break Event detected). MPIIX starts throttle clock when timer expires. timer programmed Clock Control Register (offset D4h) with granularity This provides timer range sec, sec, respectively. timer reloaded everytime enabled CLKTHL Break Event detected. Description CLKTHL_STBY_TMR: This field contains count value STPCLK# deassertion CLKTHL Break Event detected). illegal programmed count.
82371MX (MPIIX)
3.2.48. SYSMGNTC-System Management Control Register Address Offset: Default Value: Attribute: Read/Write
This register freezes power management timers, enables/disables power management functions, enables/disables SMI# signal. Reserved. SM_FREEZE. 1=Freeze power management timers (timers stop counting retain present count). SM_EN. 0=Disable power management functions. SMI_GATE. 1=Enable SMI. 0=Disable SMI. When enabled, system management interrupt condition asserts SMI# signal. When disabled, SMI# signal masked negated. This only affects SMI# signal does affect detection/recording SMI. Thus, pending when this SMI# signal asserted. Description
3.2.49. SYSSMIE-System Enable Register Address Offset: Default Value: Attribute: Read/Write
This register enables generation enabled SYSMGNTC Register) associated hardware events (bits [5:0]), software events (bit Reserved. APMC_SMI_EN. 1=Enable write APMC Register generates SMI#). 0=Disable SWEXT_SMI_EN_EXTSMI. 1=Enable (The occurrence EXTSMI# reloads Software /EXTSMI# Delay Timer generated after this timer expires.). 0=Disable SYS_SMI_EN_IRQ12. 1=Enable. 0=Disable. SYS_SMI_EN_IRQ8. 1=Enable. 0=Disable. SYS_SMI_EN_IRQ4. 1=Enable. 0=Disable. SYS_SMI_EN_IRQ3. 1=Enable. 0=Disable. SYS_SMI_EN_IRQ1. 1=Enable. 0=Disable. Description
82371MX (MPIIX)
3.2.50. MISCSMIE-Misc Enable Register Address Offset: Default Value: Attribute: Read/Write
This register enables interrupt write APCM Register, enables SRBTN# BATLOW# signals generate SMI. Reserved. APM_CALLBACK_EN. When (and APMC enabled SYSSMIE Register), write APMC Register generates interrupt (PIRQA). PIRQA steered available interrupt interrupt controller. SUSP_SMI_EN_SRBTN. 1=Enable (SRBTN# assertion causes SMI, enabled GSMIE Register). 0=Disable. SUSP_SMI_EN_BATLOW. 1=Enable (BATLOW# assertion causes SMI, enabled GSMIE Register). 0=Disable. Reserved. Description
3.2.51. GSMIE-Global Enable Register Address Offset: Default Value: Attribute: Read/Write
This register provides master enable system events, software SMI# EXTSMI#, local traps, local standby timers, global standby timer, SRBTN# BATLOW# suspend signals. register also enables Software/EXTSMI Delay Timer. Description SYS_SMI_EN. 1=Enable (master enable system events SYSEVNT[2:0] Registers). 0=Disable these system events from generating SMI. SWEXT_SMI_EN. 1=Enable software SMI# generated this register. This (bit also enables EXTSMI# signal cause SMI, enabled SYSSMIE Register. 0=Disable these SMIs from generating SMI. Reserved. LTRP_SMI_EN. 1=Enable (master enable local traps). 0=Disable (local traps will cause SMI). LSTBY_SMI_EN. 1=Enable (master enable standby timers). 0=Disable (standby timers will cause SMI). GSTBY_SMI_EN. 1=Enable (global standby timer loaded with intial value, begins counting, generates when counter expires). 0=Disable global standby timer. SUSP_SMI_EN. 1=Enable (SRBTN# BATLOW# generate SMI, individual enable MISCSMIE Register). 0=Disable SRBTN# BATLOW# from generating SMI.
82371MX (MPIIX)
Description SWEXT_SMI_EN_SW. This permits software generate SMI. 1=Enable (Software/EXTSMI Delay Timer reloaded, starts counting, generates when timer expires).
3.2.52. SYSSMIS-System STATUS Register Address Offset: Default Value: Attribute: Read/Write
This register indicates whether IRQ[12,8,4,3,1], EXTSMI#, software (via GSMIE Register) generated SMI. MPIIX sets these bits software sets these bits writing individual bit(s). MPIIX setting same time that software setting Reserved. SWEXT_STAT_SW. 1=Software caused SMI# (setting GSMIE Register). SWEXT_STAT_EXTSMI. 1=EXTSMI# signal caused SMI#. SYS_STAT_IRQ12. 1=IRQ12 caused SMI#. SYS_STAT_IRQ8. 1=IRQ8# caused SMI#. SYS_STAT_IRQ4. 1=IRQ4 caused SMI#. SYS_STAT_IRQ3. 1=IRQ3 caused SMI#. SYS_STAT_IRQ1. 1=IRQ1 caused SMI#. Description
3.2.53. MISCSMIS-Miscellaneous STATUS Register Address Offset: Default Value: Attribute: Read/Write
This register indicates whether SRBTN# BATLOW caused SMI. register also permits power management software provide status whether system global standby. Note that MPIIX sets bits [2,1] software sets these bits writing individual bit(s). MPIIX setting bits [2,1] same time that software setting Reserved. SYSTEM_IN_GSTBY. This reset software indicate whether system Global Standby. SUSP_STAT_SRBTN. 1=SRBTN# signal caused SMI#. SUSP_STAT_BATLOW. 1=BATLOW# signal caused SMI#. Description
82371MX (MPIIX)
Reserved. Description
3.2.54. GSMIS Global STATUS Register Address Offset: Default Value: Attribute: Read/Write
This register indicates whether system event, EXTSMI#, software (via GSMIE Register) generated SMI. register also indicates whether write APMC Register, local traps, local standby timers, global standby timer, suspend hardware events caused SMI. MPIIX sets these bits software sets these bits writing individual bit(s). MPIIX setting same time that software setting Description SYS_STAT. 1=One system events SYSEVNT[2:0] Registers caused SMI#. SWEXT_STAT. 1=Software (programming GSMIE Register) EXTSMI# caused SMI. APM_STAT. 1=Write APMC Register caused SMI. LTRP_STAT. 1=Access Local Traps caused SMI. LSTBY_STAT. 1=One Local Standby Timers expired caused SMI. GSTBY_STAT. 1=Global Standby Timer expired caused SMI. SUSP_STAT. 1=SRBTN# BATLOW# caused SMI. Reserved.
3.2.55. SUSRSMC1-Suspend/Resume Control Register Address Offset: Default Value: Attribute: Read/Write
software programmable bits this register control various suspend/resume functions. This register also enables BATLOW# signal bypass Suspend Delay Timer immediately generate SMI. Description BATLOW_BYPASS_EN. When (and MISCSMIE Register), BATLOW# input bypasses Suspend Delay Timer cause SMI# directly. When this BATLOW# waits timer expire. RSM_MSK_IRQ8. 1=IRQ8# will cause resume. RSM_MSK_COMRI. 1=COMRI# will cause resume. RSM_MSK_BATLOW. 1=BATLOW# will PREVENT resume.
82371MX (MPIIX)
Description SUS_REF. This power management software suspend routine. SUS_STAT automatically MPIIX when SUS_REF software. This shadowed MTSC initiate suspend refresh. SUS_STAT. This power management software suspend routine. addition, this MPIIX when SUS_REF This power managment resume routine. SUS_MODE. This field sets suspend mode. Bits[1:0] Function Suspend Disabled Reserved (illegal) Suspend-to-DRAM Suspend-to-Disk
3.2.56. SUSRSMC2-Suspend/Resume Control Register Address Offset: Default Value: Attribute: Read/Write
This register prevents EXTSMI# from causing resume event. Reserved. RSM_MSK_EXTSMI. 1=EXTSMI# will cause resume event. Description
3.2.57. SMOUTC-SMOUT Control Register Address Offset: Default Value: Attribute: Read/Write
This register controls SMOUT[5:0] signals. Reserved. SMOUT[5:0]. Writing these bits causes that logical level driven corresponding SMOUTx signal. When dual function SMOUT5/DOE# signal configured Disk Output Enable (DOE#), writing SMOUT5 effect. When dual function SMOUT4/RTCALE signal configured RTCALE, writing SMOUT4 effect. Description
82371MX (MPIIX)
3.2.58. SYSEVNTE0-System EVENT Enable Register Address Offset: Default Value: Attribute: Read/Write
This register enables hardware events system events power management control. Description SYS_EVNT_EN_IRQ_7. 1=Enable IRQ7 System Event. SYS_EVNT_EN_IRQ_6. 1=Enable IRQ6 System Event. SYS_EVNT_EN_IRQ_5. 1=Enable IRQ5 System Event. SYS_EVNT_EN_IRQ_4. 1=Enable IRQ4 System Event. SYS_EVNT_EN_IRQ_3. 1=Enable IRQ3 System Event. Reserved. SYS_EVNT_EN_IRQ_1. 1=Enable IRQ1 System Event. SYS_EVNT_EN_IRQ_0. 1=Enable IRQ0 System Event.
3.2.59. SYSEVNTE1-System EVENT Enable Register Address Offset: Default Value: Attribute: Read/Write
This register enables hardware events system events power management control. Description SYS_EVNT_EN_IRQ_15. 1=Enable IRQ15 System Event. SYS_EVNT_EN_IRQ_14. 1=Enable IRQ14 System Event. Reserved. SYS_EVNT_EN_IRQ_12. 1=Enable IRQ12 System Event. SYS_EVNT_EN_IRQ_11. 1=Enable IRQ11 System Event. SYS_EVNT_EN_IRQ_10. 1=Enable IRQ10 System Event. SYS_EVNT_EN_IRQ_9. 1=Enable IRQ9 System Event. SYS_EVNT_EN_IRQ_8. 1=Enable IRQ8# System Event.
82371MX (MPIIX)
3.2.60. SYSEVNTE2-System EVENT Enable Register Address Offset: Default Value: Attribute: Read/Write
This register enables hardware events system events power management control. This register also contains master enable system events. Description SYS_EVNT_EN_HWSUS. 1=Enable BATLOW# SRBTN# System Event. corresponding BATLOW# SRBTN# enable bits must MISCSMIE Register these signals recognized system events. SYS_EVNT_EN_EXTSMI. 1=Enable EXTSMI# System Event. EXTSMI# must SYSSMIE Register this signal recognized system event. SYS_EVNT_EN_SMI. 1=Enable SMI# System Event. SYS_EVNT_EN_NMI. 1=Enables System Event. SYS_EVNT_EN_INTR. 1=Enable INTR System Event. Reserved. SYS_EVNT_EN_COMRI. 1=Enable COMRI# System Event. SYS_EVNT_EN. 1=Enable System Events (each System Event individually enabled SYSEVNT[2:0]). 0=Disable System Events. enabled system event causes Global Standby Timer Delay timers reloaded.
3.2.61. BSTCLKT Burst Count Timer Register Address Offset: Default Value: Attribute: Read/Write
This register provides 8-bit initial count Burst Count Timer that controls STPCLK# negation period after Burst Clock Event mode. timer runs with granularity giving timer range timer reloaded from this register every time enabled Burst Clock Event detected. STPCLK# asserted when timer expires. Description STPCLK_LO_TMR. This field contains Burst Count Timer count value.
82371MX (MPIIX)
3.2.62. CLKC-Clock Control Register Address Offset: Default Value: Attribute: Read/Write
This register enables PCICLK stopped enables clock throttling. register also permits software control STPCLK#. Description Clock Throttle Standby Timer Frequency (CLKTHSBYT) Timer: This selescts resolution (granularity) 8-bit CLKTHSBYT. Reserved. Auto Clock Throttle (ACT_MODE_EN): 1=Enable. 0=Disable. STPCLK_MODE. When either read from APMC Register causes STPCLK# asserted. When bits [3:2]=00, reads from APMC Register have effect STPCLK# function. Bits[3:2] Function Disable STPCLK# function Enable Stop Grant Mode Enable Stop Clock Mode Reserved
CLK_THROTTLE_EN. 1=Enable clock throttling. 0=Disable clock throttling. PCI_CLK_CTRL_EN. 1=Enable (PCI clock stopped). 0=Disable.
3.2.63. STPCLKLT-STPCLK# Timer Register Address Offset: Default Value: Attribute: Read/Write
value this register defines duration STPCLK# asserted period when CLKC Register value this register loaded into STPCLK# Timer when STPCLK# asserted. STPCLK# timer counts using 32-us clock with range Description STPCLK_LO_TMR. Bits [7:0] define duration STPCLK# asserted period during clock throttling. illegal programmed count.
82371MX (MPIIX)
3.2.64. STPCLKHT-STPCLK# High Timer Count Address Offset: Default Value: Attribute: Read/Write
value this register defines duration STPCLK# negated period when CLKC Register value this register loaded into STPCLK# Timer when STPCLK# negated. STPCLK# timer counts using 32-us clock with range Description STPCLK_HI_TMR. Bits [7:0] define duration STPCLK# negated period during clock throttling. illegal programmed count.
3.2.65. STPBRKE0-Stop Break Event Enable Register Address Offset: Default Value: Attribute: Read/Write
This register enables/disables hardware events break events restore system clocks. When break event enabled, corresponding hardware event activity restores clock negating STPCLK# reloading STPCLKHT Register with intial count. Description STPBRK_EN_IRQ7. 1=Enable IRQ7 break event. STPBRK_EN_IRQ6. 1=Enable IRQ6 break event. STPBRK_EN_IRQ5. 1=Enable IRQ5 break event. STPBRK_EN_IRQ4. 1=Enable IRQ4 break event. STPBRK_EN_IRQ3. 1=Enable IRQ3 break event. Reserved. STPBRK_EN_IRQ1. 1=Enable IRQ1 break event. STPBRK_EN_IRQ0. 1=Enable IRQ0 break event.
82371MX (MPIIX)
3.2.66. STPBRKE1-Stop Break Event Enable Register Address Offset: Default Value: Attribute: Read/Write
This register enables/disables hardware events break events restore system clocks. When break event enabled, corresponding hardware event activity restores clock negating STPCLK# reloading STPCLKHT Register with intial count. Description STPBRK_EN_IRQ15. 1=Enable IRQ15 break event. STPBRK_EN_IRQ14. 1=Enable IRQ14 break event. Reserved. STPBRK_EN_IRQ12. 1=Enable IRQ12 break event. STPBRK_EN_IRQ11. 1=Enable IRQ11 break event. STPBRK_EN_IRQ10. 1=Enable IRQ10 break event. STPBRK_EN_IRQ9. 1=Enable IRQ9 break event. STPBRK_EN_IRQ8. 1=Enable IRQ8# break event.
3.2.67. STPBRKE2-Stop Break Event Enable Register Address Offset: Default Value: Attribute: Read/Write
This register enables/disables hardware events break events restore system clocks. When break event enabled, corresponding hardware event activity restores clock negating STPCLK# reloading STPCLKHT Register with intial count. This register also disables break events. Description STPBRK_EN_HWSUS. 1=Enable SRBTN# BATLOW# break events. these signals recognized break events, corresponding SMIs musts enabled MISCSMIE Register. STPBRK_EN_EXTSMI. 1=Enable EXTSMI# break event. this signal recognized break event, SMIs must enable EXTSMI# SYSSMIE Register. STPBRK_EN_SMI. 1=Enable SMI# break event. STPBRK_EN_NMI. 1=Enable break event. STPBRK_EN_INTR. 1=Enable INTR break event. Reserved. STPBRK_EN_COMRI. 1=Enable COMRI# break event. STPBRK_EN. 0=Disable break events. 1=Break events enabled their respective enables.
82371MX (MPIIX)
3.2.68. SHDW-Shadow Register Access Port Register Location: Default Value: Attribute: undefined Read/Write.
MPIIX includes shadow registers standard write-only registers. transition Suspend mode, content these registers saved system state restored, when resumed. shadowed registers read through configuration register. When written, SHDW register initializes counter that points shadow register. When SHDW Register read, returns data from shadow register pointed counter. counter increments count every time software reads register. Tables 3.3-3.5 define MPIIX shadow registers with register counter. Register Counter address Table Registers Description Master Channel Base Address Register (low byte). Channel Base Address Register (high byte). Channel Base Word Count Register (low byte). Channel Base Word Count Register (high byte). Channel Base Address Register (low byte). Channel Base Address Register (high byte). Channel Base Word Count Register (low byte). Channel Base Word Count Register (high byte). Channel Base Address Register (low byte). Channel Base Address Register (high byte). Channel Base Word Count Register (low byte). Channel Base Word Count Register (high byte). Channel Base Address Register (low byte). Channel Base Address Register (high byte). Channel Base Word Count Register (low byte). Channel Base Word Count Register (high byte). DMA1 Command Register. Channel Mode Register. Channel Mode Register. Channel Mode Register. Channel Mode Register. DMA1 Mask Register.
82371MX (MPIIX)
Table Registers Register Counter address Slave Channel Base Address Register (low byte). Channel Base Address Register (high byte). Channel Base Word Count Register (low byte). Channel Base Word Count Register (high byte). Channel Base Address Register (low byte) Channel Base Address Register (high byte). Channel Base Word Count Register (low byte). Channel Base Word Count Register (high byte). Channel Base Address Register (low byte). Channel Base Address Register (high byte). Channel Base Word Count Register (low byte). Channel Base Word Count Register (high byte). DMA2 Command Register. Channel Mode Register. Channel Mode Register. Channel Mode Register. DMA2 Mask Register. Description
NOTE: Base Address Registers, Base Word Counter Registers, Mode Register channel shadowed. However, Mask channel still shadowed. Table Programmable Interrupt Controller Other Registers Register Counter address Interrupt Controller PIC1 ICW1. PIC1 ICW2. PIC1 ICW3. PIC1 ICW4 PIC1 OCW2. PIC2 ICW1. PIC2 ICW2. PIC2 ICW3. Description
82371MX (MPIIX)
Register Counter address PIC2 ICW4. PIC2 OCW2. OTHER. 03FAh 02FAh 03EAh 02EAh mask address. COM1 FIFO Enable Register bits (other bits undefined). COM2 FIFO Enable Register bits (other bits undefined). COM3 FIFO Enable Register bits (other bits undefined). COM4 FIFO Enable Register bits (other bits undefined). TIMER Count Register (low byte). TIMER Count Register (high byte). Master OCW3 Register (bits 0,2,5). Slave OCW3 Register (bits 0,2,5). Total Registers. 3.2.69. BSTCLKEE[6:0]-Burst Clock Event Enable Registers Address Offset: Default Value: Attribute: (BSTCLKEE0) (BSTCLKEE6) Read/Write Description
These registers enable various activities Burst Clock Events. Setting enables corresponding activity Burst Clock Event. When activity detected, STPCLK# negated, necessary, Burst Clock Timer reloaded. Burst Clock Event Enable (bit BSTCLKEE2 register) globally enables these events.
BSTCLK ENVT EN_6 BSTCLK ENVT EN_5 BSTCLK ENVT EN_4 BSTCLK ENVT EN_3 BSTCLK ENVT EN_2 BSTCLK ENVT EN_1 BSTCLK ENVT EN_0
Audio-E Audio-D Audio-C Audio-B Audio-A Parallel-3 Parallel-2 Parallel-1
COM4 COM3 COM2 COM1 FDC-S FDC-P IDE-S IDE-P
PMAC1 PMAC0 PAC5 PAC4 PAC3 PAC2 PAC1 PCSC
Reserved Reserved Reserved Reserved Reserved Reserved EXTEVNT PHLDA#
Reserved EXTSMI# SMI# Reserved Reserved Reserved COMRI# Burst Clock
IRQ15 IRQ14 Reserved IRQ12 IRQ11 IRQ10 IRQ9 IRQ8#
IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 Reserve IRQ1 IRQ0
82371MX (MPIIX)
Event Enable
3.2.70. CLKTHLBRKEE[6:0]-Clock Throttle Break Event Enable Registers Address Offset: Default Value: Attribute: (CLKTHLBRKEE0) (CLKTHLBRKEE6) Read/Write
These registers enable various activities Clock Throttle Break Events. Setting enables corresponding activity Clock Throttle Break Event. When activity detected, STPCLK# negated, necessary, Clock Throttle Standby Timer reloaded. CLKTHLBRKE Enable (bit CLKTHLBRKEE2 register) globally enables these events.
Bits CLKTHL BRKEVNT EN_6 CLKTHL BRKEVNT EN_5 CLKTHL BRKEVNT EN_4 CLKTHL BRKEVNT EN_3 CLKTHL BRKEVNT EN_2 CLKTHL BRKEVNT EN_1 CLKTHL BRKEVNT EN_0
Audio-E Audio-D Audio-C Audio-B Audio Parallel-3 Parallel-2 Parallel-1
Serial-4 Serial-3 Serial-2 Serial-1 FDC-S FDC-P IDE-S IDE-P
PMAC1 PMAC0 PAC5 PAC4 PAC3 PAC2 PAC1 PCSC
Reserved Reserved Reserved Reserved Reserved Reserved EXTEVNT# PHLDA#
BATLOW# /SRBTN# EXTSMI# SMI# INTR Reserved COMRI# CLKTHL BRKEVNT Enable
IRQ15 IRQ14 Reserved IRQ12 IRQ11 IRQ10 IRQ9 IRQ8#
IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 Reserved IRQ1 IRQ0
3.3. Compatible Registers
Compatible registers contain DMA, timer/counter, interrupt registers. This group also contains NMI, reset registers. 3.3.1. REGISTERS
MPIIX contains circuitry that incorporates functionality 82C37 controllers (DMA1 DMA2). registers control operation controllers accessible interface. This section describes registers. Unless otherwise stated, PCIRST sets each register default value.
82371MX (MPIIX)
3.3.1.1. DCOM-DMA Command Register Channels 0-3-08h Channels 4-7-0D0h Write Only
Register Location: Default Value: Attribute:
This 8-bit register controls configuration DMA. Note that disabling channels also disables channels 0-3, since channels cascaded onto channel Description DACK# ACTIVE Level (DACK[3:0,7:5]#). This hardwired DACK[3:0,7:5]# always active low. DREQ Sense Assert Level (DREQ[3:0,7:5]). This hardwired DREQ[3:0,7:5] always active high. Reserved. Must Group Arbitration Priority. 1=Rotating priority. 0=Fixed priority. Reserved. Must Channel Group Enable. 1=Disable. 0=Enable. Reserved. Must
3.3.1.2.
DCM-DMA Channel Mode Register Channels 0-3-0Bh Channels 4-7-0D6h Bits[7:2]=0, Bits[1:0]=undefined Write Only
Register Location: Default Value: Attribute:
Each channel Channel Mode Register. Channel Mode Registers provide control over transfer type, transfer mode, address increment/decrement, autoinitialization. This register default state upon PCIRST Master Clear. Description Transfer Mode: Each channel programmed four different modes. Note that channels programmed block cascade mode channels that used programmed type timing mode. Bits[7:6] Transfer Mode Demand mode Single mode Block mode Cascade mode
Address Increment/Decrement Select: 0=Increment; 1=Decrement. Autoinitialize Enable: 1=Enable; 0=Disable.
82371MX (MPIIX)
Description Transfer Type: When Bits [7:6]=11, transfer type bits irrelevant. Bits[3:2] Transfer Type Verify transfer Write transfer Read transfer Illegal
Channel Select: Bits [1:0] select Channel Mode Register written bits [7:2]. Bits[1:0] Channel Channel Channel Channel Channel
3.3.1.3.
DR-DMA Request Register Channels 0-3-09h Channels 4-7-0D2h Reserved Write Only
Register Location: Default Value: Attribute:
Writes these register address locations claimed MPIIX have effect. Reserved. Must Channel Service Request. Reserved. Channel Select. Reserved. Description
3.3.1.4.
Mask Register-Write Single Mask Channels 0-3-0Ah Channels 4-7-0D4h Bits[1:0]=undefined, 2=1, Bits[7:3]=0 Write Only
Register Location: Default Value: Attribute:
channel's mask automatically when Current Byte/Word Count Register reaches terminal count (unless channel programmed autoinitialization). Setting entire register disables requests until clear mask register instruction allows them occur. This instruction format similar format used with Request Register. Masking channel (DMA controller channel also masks channels [3:0]. fields this register following PCIRST Master Clear. Reserved. Must Channel Mask Select. 1=Disable DREQ selected channel. 0=Enable DREQ selected channel. Description
82371MX (MPIIX)
Description Channel Select. Bits [1:0] select Channel Mode Register program with Bits [1:0] Channel
3.3.1.5.
Mask Register-Write Mask Bits Channels 0-3-0Fh Channels 4-7-0DEh Bit[3:0]=1, Bit[7:4]=0 Read/Write
Register Location: Default Value: Attribute:
channel's mask automatically when Current Byte/Word Count Register reaches terminal count (unless channel programmed autoinitialization). Setting bits [3:0] disables requests until clear mask register instruction enables requests. Note that, masking channel (DMA controller channel masks channels [3:0]. Reserved. Must Channel Mask Bits. 1=Disable corresponding DREQ(s); 0=Enable corresponding DREQ(s). Bits [3:0] upon PCIRST Master Clear. Channel Description
82371MX (MPIIX)
3.3.1.6. DS-DMA Status Register Channels 0-3-08h Channels 4-7-0D0h Read Only
Register Location: Default Value: Attribute:
Each controller read-only Status Register that indicates which channels have reached terminal count which channels have pending request. Description Channel Request Status. When valid request pending channel DREQ signal line), corresponding When request pending particular channel, corresponding Note that channel used cascade controllers together used transfers, response read DMA2 status channel irrelevant. Channel
Channel Terminal Count Status. 1=TC reached; 0=TC reached. Channel
3.3.1.7.
Base Current Address Registers (8237 Compatible Segment) Channel 0-000h Channel 4-0C0h Channel 1-002h Channel 5-0C4h Channel 2-004h Channel 6-0C8h Channel 3-006h Channel 7-0CCh Default Value: Undefined Read/Write
Register Location:
Attribute:
This Register works conjunction with Page Register. After autoinitialization, this register retains original programmed value. Autoinitialize takes place after address register automatically incremented decremented after each transfer. This register read/written successive 8-bit bytes. programmer must issue "Clear Byte Pointer Flip-Flop" command reset internal byte pointer correctly align write prior programming Current Address Register. Autoinitialize takes place only after 15:0 Description Base Current Address [15:0]. These bits represent least significant address bits used during transfers. Together with Page Register, they form ISAcompatible 24-bit address. Upon PCIRST Master Clear, value these bits undefined.
82371MX (MPIIX)
3.3.1.8. Base Current Byte/Word Count Registers (Compatible Segment) Channel 0-001h Channel 1-003h Channel 2-005h Channel 3-007h Default Value: Undefined Read/Write Channel 4-0C2h Channel 5-0C6h Channel 6-0CAh Channel 7-0CEh
Register Location:
Attribute:
This register determines number transfers performed. actual number transfers more than number programmed Current Byte/Word Count Register When value register decremented from zero FFFFh, generated. After autoinitialization, this register retains original programmed value. Autoinitialize only occur when occurs. autoinitialized, this register count FFFFh after transfers to/from 8-bit I/O, Byte/Word count indicates number bytes transferred. This applies channels 0-3. transfers to/from 16-bit I/O, with shifted address, Byte/Word count indicates number 16-bit words transferred. This applies channels 5-7. 15:0 Description Base Current Byte/ Word Count. This field represents 16-byte/word count bits used when counting down transfer. Upon PCIRST Master Clear, value these bits undefined.
3.3.1.9.
Memory Page Registers Channel 0-087h Channel 1-083h Channel 2-081h Channel 3-082h Default Value: Undefined Read/Write Channel 5-08Bh Channel 6-089h Channel 7-08Ah
Register Location:
Access:
Each channel 8-bit Page Register. memory Page Register contains bits 23-16 24-bit address. register works conjunction with controller's Current Address Register define complete (24-bit) address channel. This 8-bit register read written directly. This register static throughout transfer. Following autoinitialization, this register retains original programmed value. Autoinitialize takes place only after Description Page [23:16]. These bits represent address bits [23:16] 24-bit address. Upon PCIRST Master Clear, value these bits undefined.
82371MX (MPIIX)
3.3.1.10. Clear Byte Pointer Register Register Location: Default Value: Attribute: Channels 0-3-00Ch Channels 4-7-0D8h bits undefined Write Only
Writing this register executes Clear Byte Pointer Command. This command executed prior reading/writing address word count DMA. command initializes byte pointer flip-flop known state that subsequent accesses register contents address upper lower bytes correct sequence. Clear Byte Pointer Command CPURST Master Clear Command) clears internal latch used address upper lower byte 16-bit Address Word Count Registers. Description Clear Byte Pointer. specific pattern. Command enabled with write port address.
3.3.1.11. DMC-DMA Master Clear Register Register Location: Default Value: Attribute: Channel 0-3-00Dh Channel 4-7-0DAh bits undefined Write Only
This software instruction same effect hardware Reset. Command, Status, Request, Internal First/Last Flip-Flop registers cleared Mask Register set. controller enters idle cycle. There independent Master Clear Commands; acts channels 0-3, 0DAh acts channels 4-7. Description Master Clear. specific pattern. Command enabled with write port address
3.3.1.12. DCLM-DMA Clear Mask Register Register Location: Default Value: Attribute: Channel 0-3-00Eh Channel 4-7-0DCh bits undefined Write Only
This command clears mask bits four channels. Description Clear Mask Register. specific pattern. Command enabled with write port address.
82371MX (MPIIX)
3.3.2. 3.3.2.1. TIMER/COUNTER REGISTERS TCW-Timer Control Word Register 043h bits undefined Write Only
Register Location: Default Value: Attribute:
Timer Control Word Register specifies counter selection, operating mode, counter byte programming order size count value, whether counter counts down 16-bit binary-coded decimal (BCD) format. After writing control word, count written time. value takes effect according programmed mode. Counter Select. [7:6] Function Counter select Counter select Counter select Read Back Command Description
Read/Write Select. [5:4] Function Counter Latch Command Least Significant Byte (LSB) Most Significant Byte (MSB) then
Counter Mode Selection. Bits [3:1] select possible counter modes. [3:1] Mode Function signal count (=0) Hardware retriggerable one-shot Rate generator (divide counter) Square wave output Software triggered strobe Hardware triggered strobe
Binary/BCD Countdown Select. 0=Binary countdown. largest possible binary count 216. 1=Binary coded decimal (BCD) count used. largest count allowed 104.
Read Back Command Read Back Command used determine count value, programmed mode, current states Null count flag selected counter counters. Read Back Command written Timer Control Word Register which latches current states above mentioned variables. value counter status then read access counter address. Note that Timer Counter Register definitions different during Read Back Command than normal Timer Counter Register write.
82371MX (MPIIX)
Description Read Back Command: When bits[7:6]=11, Read Back Command selected during write Timer Control Word Register. Following Read Back Command, reads from selected counter's addresses produce current latch status, current latched count, both bits both Latch Count Selected Counters: When 5=0, current count value selected counters will latched. When 5=1, count will latched. Latch Status Selected Counters: When 4=0, status selected counters will latched. When 4=1, status will latched. status byte format described Section 4.3.3, Interval Timer Status Byte Format Register. Counter Select: When 3=1, Counter selected latch command selected with bits When 3=0, status and/or count will latched. Counter Select: When 2=1, Counter selected latch command selected with bits When 2=0, status and/or count will latched. Counter Select: When 1=1, Counter selected latch command selected with bits When 1=0, status and/or count will latched. Reserved. Must
Counter Latch Command Counter Latch Command latches current count value time command received. Counter latched once then, some time later, latched again before count read, second Counter Latch Command ignored. count read will count time first Counter Latch Command issued. counter programmed two-byte counts, bytes must read. bytes have read successively (read, write, programming operations other counters inserted between reads). Note that Timer Counter Register definitions different during Counter Latch Command than normal Timer Counter Register write. Note that, counter programmed read/write two-byte counts, program must transfer control between reading first second byte another routine that also reads from that same counter. Otherwise, incorrect count will read. Description Counter Selection. Bits used select counter latching. [7:6] Function latch counter select latch counter select latch counter select Read Back Command select counter latch command)
Counter Latch Command. When bits[5:4]=00, Counter Latch Command selected during write Timer Control Word Register. Following Counter Latch Command, reads from selected counter's addresses produce current latched count. Reserved. Must
82371MX (MPIIX)
3.3.2.2. Interval Timer Status Byte Format Register Counter 0-040h Counter 1-041h Counter 2-042h Bits[6:0]=Undefined, Read Only
Register Location:
Default Value: Attribute:
Each counter's status byte read following Interval Timer Read Back Command. latch status chosen (bit 4=0, Read Back Command) read back option given counter, next read from counter's Counter Access Ports Register returns status byte. Description Counter State: 1=Pin 0=Pin Count Register Status: This indicates when last count written Count Register (CR) been loaded into counting element (CE). 0=Count been transferred from available reading. 1=Count been transferred from available reading. Read/Write Selection Status: B
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