Non-Volatile SRAM MODULE 32Mbit (4,096K 8-Bit), 40Pin-DIP, 3.3V P

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Non-Volatile SRAM MODULE 32Mbit (4,096K 8-Bit), 40Pin-DIP, 3.3V P

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HMN4M8DV(N)
Non-Volatile SRAM MODULE 32Mbit (4,096K 8-Bit), 40Pin-DIP, 3.3V
Part HMN4M8DV(N)
GENERAL DESCRIPTION
HMN4M8DV Nonvolatile SRAM 33,554,432-bit static organized 4,194,304 bytes bits. HMN4M8DV self-contained lithium energy source provide reliable -volatility coupled with unlimited write cycles standard SRAM integral control circuitry which constantly monitors single 3.3V supply out-oftolerance condition. When such condition occurs, lithium energy source automatically switched sustain memory until after returns valid write protection unconditionally enabled prevent garbled data. addition SRAM unconditionally write-protected prevent inadvertent write operation. this time integral energy source switched sustain memory until after returns valid. HMN4M8DV uses extremely standby current CMOS SRAM's, coupled with small lithium coin cells provide volatility without long write-cycle times write-cycle limitations associated with EEPROM.
FEATURES
Access time 70ns High-density design 32Mbit Design Battery internally isolated until power applied Industry-standard 40-pin 4,096K pinout Unlimited write cycles Data retention absence 5-years minimum data retention absence power Automatic write-protection during power-up/power-down cycles Data automatically protected during power loss
ASSIGNMENT
36-pin Encapsulated Package
Package Option HMN4M8DV HMN4M8DVN Package Package
40-pin Encapsulated Package
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HANBit Electronics Co.,Ltd
FUNCTIONAL DESCRIPTION
HMN4M8DV(N)
HMN4M8DV executes read cycle whenever inactive(high) active(low). address specified address inputs(A 0-A19) defines which 4,194,304 bytes data accessed. Valid data will vailable eight data output drivers within (access time) after last address input signal stable. When power valid, HMN4M8DV operates standard CMOS SRAM. During power -down power-up cycles, HMN4M8DV acts nonvolatile memory, automatically protecting preserving memory contents. HMN4M8DV write mode whenever signals active (low) state after address inputs stable. later occurring falling edge will etermine start write cycle. write cycle terminated earlier rising edge /WE. address inputs must kept valid throughout write cycle. must return high state minimum recovery time before another cycle initiated. control signal should kept inactive (high) during write cycles avoid contention. However, output been enabled (/CE active) then will disable outputs from falling edge. HMN4M8DV provides full functional capability greater than write protects 4.37 nominal. Power-down/power-up control circuitry constantly monitors supply power-fail-detect threshold PFD. When falls below threshold, SRAM automatically write -protects data. inputs become "don't care" outputs high impedance. falls below approximately power switching circuit connects lithium energy soure retain ata. During power-up, when rises above approximately volts, power switching circuit connects external disconnects lithium energy source. Normal operation resume after exceeds volts.
BLOCK DIAGRAM
DESCRIPTION
A0-A19 Power A20-A21 Power Fail Control Lithium Cell SRAM Block /CE1 DQ0-DQ7
A0-A21 Address Input Chip Enable Ground DQ0-DQ7 Data Data Write Enable Output Enable VCC: Power (+5V) Connection
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TRUTH TABLE
MODE selected Output disable Read Write
HMN4M8DV(N)
OPERATION High High DOUT
POWER Standby Active Active Active
ABSOLUTE MAXIMUM RATINGS
PARAMETER voltage applied relative Voltage applied excluding relative Operating temperature Storage temperature Temperature under bias Soldering temperature NOTE: SYMBOL RATING -0.5V +0.2V -0.2V 4.6V 70°C 85°C -65°C 150°C -40°C 85°C 260°C second Commercial Industrial CONDITIONS
TOPR TSTG TBIAS TSOLDER
Permanent device damage occur Absolute Maximum Ratings exceeded.
Functional operation should restricted Recommended Operating Conditions detailed this data sheet. Exposure higher than recommended voltage extended periods time could affect device reliability.
RECOMMENDED OPERATING CONDITIONS TOPR
PARAMETER Supply Voltage Ground Input high voltage Input voltage NOTE: SYMBOL 3.0V -0.2
TYPICAL 3.3V
3.6V VCC+0.3V 0.6V
Overshoot: VCC+2.0V case pulse width 20ns. Overshoot undershoot sampled, 100% tested.
Undershoot: -2.0V case pulse width 20ns.
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CAPACITANCE (TA=25 f=1MHz) DESCRIPTION Input Capacitance Input/Output Capacitance CONDITIONS Input voltage Output voltage SYMBOL CI/O
HMN4M8DV(N)
UNIT
NOTE: Capacitance sampled, 100% tested.
OPERATION CHARACTERISTICS (TA= TOPR, VCCmin VCCmax PARAMETER Input Leakage Current Output Leakage Current Output high voltage Output voltage Standby supply current CONDITIONS VIN=VSS /CE=VIH /OE=VIH /WE=VIL IOH=-1.0 IOL= VCC-0.2V Cycle time=Min, 100% duty, II/O=0 /CE<Vcc-0.2V, Average operating current VIN<0.2V VIN>VCC-0.2V Cycle time=1us, 100% duty, II/O=0 /CE=VIL, VIN=VIL Power-fail-detect voltage Supply switch-over voltage VPFD ICC2 ICC1 SYMBOL ISB1 TYP.
CHARACTERISTICS (Test Conditions) PARAMETER Input pulse levels Input rise fall times Input output timing reference levels Output load (including scope jig) Figure VALUE 1.5V unless otherwise specified)
Figure Output Load DOUT 1.9K
DOUT
1.9K
Figure Output Load
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READ CYCLE (TA= TOPR, VCCmin VCCmax
PARAMETER Read Cycle Time Address Access Time Chip enable access time Output enable Output valid Chip enable output Output enable output Chip disable output high Output disable output high Output hold from address change SYMBOL tACC tACE tCLZ tOLZ tCHZ tOHZ Output load Output load Output load Output load Output load Output load Output load Output load CONDITIONS
HMN4M8DV(N)
-120
-150
UNIT
WRITE CYCLE (TA= TOPR, Vccmin Vccmax
PARAMETER Write Cycle Time Chip enable write Address setup time Address valid write Write pulse width Write recovery time (write cycle Write recovery time (write cycle Data valid write Data hold time (write cycle Data hold time (write cycle Write enabled output high Output active from write SYMBOL tWR1 tWR2 tDH1 tDH2 Note Note Note Note Note Note Note Note Note Note CONDITIONS -120 -150
NOTE: write ends earlier transition going high going high. write occurs during overlap allow /WE. write begins later transition going going low. Either tWR2 must met. Either tDH2 must met. goes simultaneously with going after going low, outpu remain highimpedance state.
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DATA RETENTION CHARACTERISTICS (TA= TOPR, VCC=5V)
PARAMETER data retention Data retention current Data retention set-up time Recovery time SYMBOL tSDR tRDR CONDITIONS CEVcc-0.2V Vcc=3.0V, CEVcc data retention
HMN4M8DV(N)
TYP.
UNIT
waveform
POWER-DOWN/POWER-UP CYCLE (TA= TOPR, VCC=3.3V)
PARAMETER VPFD(max) VPFD(min) Fail Time VPFD(max) Fail Time VPFD(max) VPFD(min) Rise Time Write Protect Time SYMBOL Delay after slews down tWPT past VPFD before SRAM Write-protected. Chip Enable Recovery VPFD (min) Rise Time tCER CONDITIONS TYP. UNIT
TIMING WAVEFORM READ CYCLE NO.1 (Address Access)*
Address tACC DOUT Previous Data Valid Data Valid
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READ CYCLE NO.2 (/CE Access)
tACE tCLZ DOUT High-Z
*1,3,4
HMN4M8DV(N)
tCHZ
High-Z
READ CYCLE NO.3 (/OE Access)
*1,5
Address tACC DOUT tOLZ High-Z tOHZ Data Valid High-Z
NOTES: held high read cycle. Device continuously selected: Address valid prior coincident with transition low. Device continuously selected:
WRITE CYCLE NO.1 (/WE-Controlled)
*1,2,3
Address DOUT Data Undefined
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tWR1
tDH1 Data-in Valid High-Z
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HMN4M8DV(N)
WRITE CYCLE NO.2 (/CE-Controlled)
*1,2,3,4,5
Address DOUT Data Undefined High-Z Data-in tDH2 tWR2
NOTE:
must high during address transition. Because active (/OE low) during this period, data input signals osite polarity outputs must applied. high, pins remain state high impedance. Either tWR2 must met. Either tDH2 must met.
POWER-DOWN/POWER-UP TIMING
4.75 VPFD
VPFD 4.25 tWPT tCER
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HANBit Electronics Co.,Ltd
PACKAGE DIMENSION
Dimension 2.070 0.710 0.365 0.015 0.008 0.590 0.017 0.090 0.080 0.120 2.100 0.740 0.375 0.013 0.630 0.023 0.110 0.110 0.150
HMN4M8DV(N)
dimensions inches.
ORDERING INFORMATION
Temperature Option Blank Commercial(0 70°C) Industrial 85°C Speed Option 70ns 85ns 120ns 150ns Package Option Blank Package Package Operation Voltage 3.3V type package Device 4,096K Nonvolatile SRAM HANBit Memory Module
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Non-Volatile SRAM MODULE 32Mbit (4,096K 8-Bit), 40Pin-DIP, 3.3V P

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