Non-Volatile SRAM MODULE 32Mbit (4,096K 8-Bit), 40Pin-DIP, Part HMN4M8

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Non-Volatile SRAM MODULE 32Mbit (4,096K 8-Bit), 40Pin-DIP, Part HMN4M8

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HMN4M8D
Non-Volatile SRAM MODULE 32Mbit (4,096K 8-Bit), 40Pin-DIP, Part HMN4M8D
HMN4M8D Nonvolatile SRAM 33,554,432-bit static organized 4,194,304 bytes bits. HMN4M8D self-contained lithium energy source provide reliable non-volatility coupled with unlimited write cycles standard SRAM integral control circuitry which constantly monitors single supply out-oftolerance condition. When such condition occurs, lithium energy source automatically switched sustain memory until after returns valid write protection unconditionally enabled prevent garbled data. addition SRAM unconditionally write-protected prevent inadvertent write operation. this time integral energy source switched sustain memory until after returns valid. HMN4M8D uses extremely standby current CMOS SRAM's, coupled with small lithium coin cells provide nonvolatility without long write-cycle times write-cycle limitations associated with EEPROM.
FEATURES
Access time 120, High-density design 32Mbit Design Battery internally isolated until power applied Industry-standard 40-pin 4,096K pinout Unlimited write cycles Data retention absence 5-years minimum data retention absence power Automatic write-protection during power-up/power-down cycles Data automatically protected during power loss Industrial temperature operation
ASSIGNMENT
OPTIONS
Timing
MARKING
-100 -150
40-pin Encapsulated Package
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FUNCTIONAL DESCRIPTION
HMN4M8D
HMN4M8D executes read cycle whenever inactive(high) active(low). address specified address inputs(A0-A19) defines which 4,194,304 bytes data accessed. Valid data will available eight data output drivers within tACC (access time) after last address input signal stable. When power valid, HMN4M8D operates standard CMOS SRAM. During power-down power-up cycles, HMN4M8D acts nonvolatile memory, automatically protecting preserving memory contents. HMN4M8D write mode whenever signals active (low) state after address inputs stable. later occurring falling edge will determine start write cycle. write cycle terminated earlier rising edge /WE. address inputs must kept valid throughout write cycle. must return high state minimum recovery time (tWR) before another cycle initiated. control signal should kept inactive (high) during write cycles avoid contention. However, output been enabled (/CE active) then will disable outputs tODW from falling edge. HMN4M8D provides full functional capability greater than write protects 4.37 nominal. Powerdown/power-up control circuitry constantly monitors supply power-fail-detect threshold VPFD. When falls below VPFD threshold, SRAM automatically write-protects data. inputs become "don't care" outputs high impedance. falls below approximately power switching circuit connects lithium energy soure retain data. During power-up, when rises above approximately volts, power switching circuit connects external disconnects lithium energy source. Normal operation resume after exceeds volts.
BLOCK DIAGRAM
1024K SRAM Block
DESCRIPTION
A0-A19 DQ0-DQ7
A0-A21 Address Input Chip Enable Ground
Power
DQ0-DQ7 Data Data Write Enable
Power Fail Control
Output Enable VCC: Power (+5V)
Lithium Cell
Connection
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TRUTH TABLE
MODE selected Output disable Read Write OPERATION High High DOUT
HMN4M8D
POWER Standby Active Active Active
ABSOLUTE MAXIMUM RATINGS
PARAMETER voltage applied relative Voltage applied excluding relative Operating temperature Storage temperature Temperature under bias Soldering temperature SYMBOL TOPR TSTG TBIAS TSOLDER RATING -0.5V 7.0V -0.3V 7.0V 70°C 85°C -55°C 125°C -40°C 85°C 260°C second Commercial Industrial CONDITIONS
NOTE: Permanent device damage occur Absolute Maximum Ratings exceeded. Functional operation should restricted Recommended Operating Conditions detailed this data sheet. Exposure higher than recommended voltage extended periods time could affect device reliability.
RECOMMENDED OPERATING CONDITIONS TOPR
PARAMETER Supply Voltage Ground Input high voltage Input voltage NOTE: SYMBOL 4.5V -0.5
TYPICAL 5.0V
5.5V VCC+0.5V 0.8V
Overshoot: VCC+3.0V case pulse width 30ns. Undershoot: -3.0V case pulse width 30ns.
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CAPACITANCE (TA=25 f=1MHz, VCC=5.0V)
DESCRIPTION Input Capacitance Input/Output Capacitance CONDITIONS Input voltage Output voltage SYMBOL CI/O
HMN4M8D
UNIT
OPERATION CHARACTERISTICS (TA= TOPR, VCCmin VCCmax
PARAMETER Input Leakage Current Output Leakage Current Output high voltage Output voltage Standby supply current Commerci Standby supply current Industrial CONDITIONS VIN=VSS /CE=VIH /OE=VIH /WE=VIL IOH=-1.0Ma IOL= 2.1mA /CE=VIH VCC-0.2V, 0.2V, VCC-0.2V Min.cycle,duty=100%,/CE=VIL, II/O=0 A20<VIL A20>VIH A21<VIL A21>VIH Power-fail-detect voltage Supply switch-over voltage VPFD 4.30 4.37 4.50 SYMBOL ISB1 TYP. UNIT
Operating supply current
CHARACTERISTICS (Test Conditions)
PARAMETER Input pulse levels Input rise fall times Input output timing reference levels Output load (including scope jig) VALUE 2.2V 1.5V unless otherwise specified) Figure
DOUT 1.9K DOUT 1.9K
Figure Output Load
Figure Output Load
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READ CYCLE (TA= TOPR, VCCmin VCCmax
PARAMETER Read Cycle Time Address Access Time Chip enable access time Output enable Output valid Chip enable output Output enable output Chip disable output high Output disable output high Output hold from address change SYMBOL tACC tACE tCLZ tOLZ tCHZ tOHZ Output load Output load Output load Output load Output load Output load Output load Output load CONDITIONS -120
HMN4M8D
-150
UNIT
WRITE CYCLE (TA= TOPR, Vccmin Vccmax
PARAMETER Write Cycle Time Chip enable write Address setup time Address valid write Write pulse width Write recovery time (write cycle Write recovery time (write cycle Data valid write Data hold time (write cycle Data hold time (write cycle Write enabled output high Output active from write SYMBOL tWR1 tWR2 tDH1 tDH2 Note Note Note Note Note Note Note Note Note Note CONDITIONS -120 -150
NOTE: write ends earlier transition going high going high. write occurs during overlap allow /WE. write begins later transition going going low. Either tWR1 tWR2 must met. Either tDH1 tDH2 must met. goes simultaneously with going after going low, outputs remain highimpedance state.
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DATA RETENTION CHARACTERISTICS (TA= TOPR, VCC=5V)
PARAMETER data retention Data retention current Data retention set-up time Recovery time SYMBOL tSDR tRDR CONDITIONS Vcc-0.2V Vcc=3.0V, data retention waveform TYP.
HMN4M8D
UNIT
POWER-DOWN/POWER-UP CYCLE (TA= TOPR, VCC=5V)
PARAMETER slew, 4.75 4.25V slew, 4.75 slew, VPFD (max) SYMBOL Time during which SRAM write-protected after passes VPFD power-up. Delay after slews down past VPFD before SRAM Write-protected. CONDITIONS TYP. UNIT
Chip enable recovery time Data-retention time Absence
tCER
years
Write-protect time
tWPT
TIMING WAVEFORM Read Cycle No.1 (Address Access)*1,2
Address tACC DOUT Previous Data Valid Data Valid
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Read Cycle No.2 (/CE Access)*1,3,4
tACE tCLZ DOUT High-Z
HMN4M8D
tCHZ
High-Z
Read Cycle No.3 (/OE Access)*1,5
Address tACC DOUT tOLZ High-Z tOHZ Data Valid High-Z
NOTES: held high read cycle. Device continuously selected: =VIL. Address valid prior coincident with transition low. VIL. Device continuously selected:
WRITE CYCLE NO.1 (/WE-CONTROLLED)*1,2,3
Address DOUT Data Undefined
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tWR1
tDH1 Data-in Valid High-Z
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WRITE CYCLE NO.2 (/CE-Controlled)*1,2,3,4,5
HMN4M8D
Address DOUT Data
NOTE:
tWR2
tDH2 Data-in
Undefined
High-Z
must high during address transition. Because active (/OE low) during this period, data input signals opposite polarity outputs must applied. high, pins remain state high impedance. Either tWR1 tWR2 must met. Either tDH1 tDH2 must met.
POWER-DOWN/POWER-UP TIMING
4.75 VPFD
VPFD 4.25 tWPT tCER
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PACKAGE DIMENSION
Dimension 2.070 0.710 0.365 0.015 0.008 0.590 0.017 0.090 0.080 0.120 2.100 0.740 0.375 0.013 0.630 0.023 0.110 0.110 0.150
HMN4M8D
dimensions inches.
ODERING INFORMATION
Operating Temperature Industrial Temp. (-40~85 Blank Commercial Temp. (0~70°C) Speed options 85ns 120ns 150ns
type package Device 4,096K (4M) Nonvolatile SRAM
HANBit Memory Module
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Non-Volatile SRAM MODULE 32Mbit (4,096K 8-Bit), 40Pin-DIP, Part HMN4M8

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