Non-Volatile SRAM MODULE 256Kbit (32K 8-Bit),28Pin DIP, Part HMN328D G

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Non-Volatile SRAM MODULE 256Kbit (32K 8-Bit),28Pin DIP, Part HMN328D G

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HMN328D
Non-Volatile SRAM MODULE 256Kbit (32K 8-Bit),28Pin DIP, Part HMN328D GENERAL DESCRIPTION
HMN328D nonvolatile SRAM 262,144-bit static organized 32,768 bytes bits. HMN328D self-contained lithium energy source provide reliable non-volatility coupled with unlimited write cycles standard SRAM integral control circuitry which constantly monitors single supply out-oftolerance condition. When such condition occurs, lithium energy source automatically switched sustain memory until after returns valid write protection unconditionally enabled prevent garbled data. addition SRAM unconditionally write-protected prevent inadvertent write operation. this time integral energy source switched sustain memory until after returns valid. HMN328D uses extremely standby current CMOS SRAM's, coupled with small lithium coin cells provide nonvolatility without long write-cycle times write-cycle limitations associated with EEPROM.
FEATURES
Access time 120, High-density design 256Kbit Design Battery internally isolated until power applied Industry-standard 28-pin pinout Unlimited write cycles Data retention absence 10-years minimum data retention absence power Automatic write-protection during power-up/power-down cycles Data automatically protected during power loss Industrial temperature operation
ASSIGNMENT
OPTIONS
Timing
MARKING
-120 -150
28-pin Encapsulated Package
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FUNCTIONAL DESCRIPTION
HMN328D
HMN328D executes read cycle whenever inactive(high) active(low). address specified address inputs(A0-A14) defines which 32,768 bytes data accessed. Valid data will available eight data output drivers within tACC (access time) after last address input signal stable. When power valid, HMN328D operates standard CMOS SRAM. During power-down power-up cycles, HMN328D acts nonvolatile memory, automatically protecting preserving memory contents. HMN328D write mode whenever signals active (low) state after address inputs stable. later occurring falling edge will determine start write cycle. write cycle terminated earlier rising edge /WE. address inputs must kept valid throughout write cycle. must return high state minimum recovery time (tWR) before another cycle initiated. control signal should kept inactive (high) during write cycles avoid contention. However, output been enabled (/CE active) then will disable outputs tODW from falling edge. HMN328D provides full functional capability greater than write protects 4.37 nominal. Powerdown/power-up control circuitry constantly monitors supply power-fail-detect threshold VPFD. When falls below VPFD threshold, SRAM automatically write-protects data. inputs become "don't care" outputs high impedance. falls below approximately power switching circuit connects lithium energy soure retain data. During power-up, when rises above approximately volts, power switching circuit connects external disconnects lithium energy source. Normal operation resume after exceeds volts.
BLOCK DIAGRAM
SRAM Block Power A0-A14 DQ0-DQ7
DESCRIPTION
A0-A14 Address Input Chip Enable Ground DQ0-DQ7 Data Data Write Enable Output Enable Lithium Cell VCC: Power (+5V) Connection
Power Fail Control
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TRUTH TABLE
MODE selected Output disable Read Write OPERATION High High DOUT
HMN328D
POWER Standby Active Active Active
ABSOLUTE MAXIMUM RATINGS
PARAMETER voltage applied relative Voltage applied excluding relative Operating temperature Storage temperature Temperature under bias Soldering temperature SYMBOL RATING -0.3V 7.0V -0.3V 7.0V 70°C 85°C -55°C 125°C -40°C 85°C 260°C second VCC+0.3 Commercial Industrial CONDITIONS
TOPR TSTG TBIAS TSOLDER
NOTE: Permanent device damage occur Absolute Maximum Ratings exceeded. Functional operation should restricted Recommended Operating Conditions detailed this data sheet. Exposure higher than recommended voltage extended periods time could affect device reliability.
RECOMMENDED OPERATING CONDITIONS TOPR
PARAMETER Supply Voltage Ground Input high voltage Input voltage SYMBOL 4.5V -0.3 TYPICAL 5.0V 5.5V VCC+0.3V 0.8V
NOTE: Typical values indicate operation
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ELECTRICAL CHARACTERISTICS (TA= TOPR, VCCmin VCCmax
PARAMETER Input Leakage Current Output Leakage Current Output high voltage Output voltage Standby supply current Standby supply current CONDITIONS VIN=VSS /CE=VIH /OE=VIH /WE=VIL IOH=-1.0mA IOL= 2.1mA /CE=VIH VCC-0.2V, 0.2V, VCC-0.2V Operating supply current Power-fail-detect voltage Supply switch-over voltage Min.cycle,duty=100%, /CE=VIL, II/O=0 VPFD 4.30 4.37 ISB1 SYMBOL TYP.
HMN328D
UNIT
4.50
CAPACITANCE (TA=25 f=1MHz, VCC=5.0V)
DESCRIPTION Input Capacitance Input/Output Capacitance CONDITIONS Input voltage Output voltage SYMBOL CI/O UNIT
CHARACTERISTICS (Test Conditions)
PARAMETER Input pulse levels Input rise fall times Input output timing reference levels Output load (including scope jig) VALUE 1.5V unless otherwise specified) Figures 1and
DOUT 1.9K DOUT 1.9K
Figure Output Load
Figure Output Load
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READ CYCLE (TA= TOPR, VCCmin VCCmax
PARAMETER Read Cycle Time Address Access Time Chip enable access time Output enable Output valid Chip enable output Output enable output Chip disable output high Output disable output high Output hold from address change SYMBOL tACC tACE tCLZ tOLZ tCHZ tOHZ Output load Output load Output load Output load Output load Output load Output load Output load CONDITIONS -120
HMN328D
-150
UNIT
WRITE CYCLE (TA= TOPR, Vccmin Vccmax
PARAMETER Write Cycle Time Chip enable write Address setup time Address valid write Write pulse width Write recovery time (write cycle Write recovery time (write cycle Data valid write Data hold time (write cycle Data hold time (write cycle Write enabled output high Output active from write SYMBOL tWR1 tWR2 tDH1 tDH2 Note Note Note Note Note Note Note Note Note Note CONDITIONS -120 -150
NOTE: write ends earlier transition going high going high. write occurs during overlap allow /WE. write begins later transition going going low. Either tWR1 tWR2 must met. Either tDH1 tDH2 must met. goes simultaneously with going after going low, outputs remain highimpedance state.
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POWER-DOWN/POWER-UP CYCLE (TA= TOPR, VCC=5V)
PARAMETER slew, 4.75 4.25V slew, 4.75 slew, VPFD (max) Chip enable recovery time Data-retention time Absence Data-retention time Absence Write-protect time SYMBOL Time during which SRAM tCER write-protected after passes VPFD power-up. tDR-N industrial temperature range (-N) only Delay after slews down tWPT past VPFD before SRAM Write-protected. CONDITIONS TYP.
HMN328D
UNIT
years years
TIMING WAVEFORM READ CYCLE NO.1 (Address Access)*1,2
Address tACC DOUT Previous Data Valid Data Valid
READ CYCLE NO.2 (/CE Access)*1,3,4
tACE tCLZ DOUT High-Z
tCHZ
High-Z
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READ CYCLE NO.3 (/OE Access)*1,5
Address tACC DOUT tOLZ High-Z tOHZ Data Valid High-Z
HMN328D
NOTES: held high read cycle. Device continuously selected: =VIL. Address valid prior coincident with transition low. VIL. Device continuously selected:
WRITE CYCLE NO.1 (/WE-Controlled)*1,2,3
Address DOUT Data Undefined Data-in Valid High-Z tDH1 tWR1
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WRITE CYCLE NO.2 (/CE-Controlled)*1,2,3,4,5
Address DOUT Data Undefined
NOTE must high during address transition. Because active (/OE low) during this period, data input signals opposite polarity outputs must applied. high, pins remain state high impedance. Either tWR1 tWR2 must met. Either tDH1 tDH2 must met.
HMN328D
tWR2
tDH2 Data-in Valid
High-Z
POWER-DOWN/POWER-UP TIMING
4.75 VPFD
VPFD 4.25 tWPT
tCER
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PACKAGE DIMENSION
Dimension 1.470 0.710 0.365 0.012 0.008 0.590 0.017 0.090 0.075 0.120 1.500 0.740 0.375 0.013 0.630 0.023 0.110 0.110 0.150
HMN328D
ORDERING INFORMATION
Operating Temp. Blank Commercial Industrial (-40 85°C)
Speed options type package Device Nonvolatile Timekeeping SRAM HANBit Memory Module
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Non-Volatile SRAM MODULE 256Kbit (32K 8-Bit),28Pin DIP, Part HMN328D G

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