Non-Volatile SRAM Module 1Mbit (128K 8-Bit), 32Pin-DIP, 3.3V Part HMN1

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Non-Volatile SRAM Module 1Mbit (128K 8-Bit), 32Pin-DIP, 3.3V Part HMN1

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HMN1288DV
Non-Volatile SRAM Module 1Mbit (128K 8-Bit), 32Pin-DIP, 3.3V Part HMN1288DV
HMN1288DV Nonvolatile SRAM 1,048,576-bit static organized 131,072 bytes bits. HMN1288DV self-contained lithium energy source provide reliable -volatility coupled with unlimited write cycles standard SRAM integral control circuitry, which constantly monitors single 3.3V, supply outof-tolerance condition. When such condition occurs, lithium energy source automatically switched sustain memory until after returns valid write protection unconditionally enabled prevent garbled data. addition SRAM unconditionally write-protected prevent inadvertent write operation. this time integral energy source switched sustain memory until after returns valid. HMN1288DV uses extremely standby current CMOS SRAM coupled with small lithium coin cells provide non-volatility without long write-cycle times write-cycle limitations associated with EEPROM.
FEATURES
Access time 120, High-density design 1Mbit Design Battery internally isolated until power applied Industry-standard 32-pin 128K pinout Unlimited write cycles Data retention absence 10-years minimum data retention absence power Automatic write-protection during power-up/power-down cycles Data automatically protected during power loss Conventional SRAM operation; unlimited write cycles
ASSIGNMENT
OPTIONS
Timing
MARKING
-120 -150
32-pin Encapsulated Package
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HMN1288DV
FUNCTIONAL DESCRIPTION
HMN1288DV executes read cycle whenever inactive(high) active(low). address specified address inputs(A 0-A16) defines which 131,072 bytes data accessed. Valid data will available eight data output drivers within tACC (access time) after last address input signal stable. When power valid, HMN1288DV operates standard CMOS SRAM. During power -down power-up cycles, HMN1288DV acts nonvolatile memory, automatically protectin preserving memory contents. HMN1288DV write mode whenever signals active (low) state after address inputs stable. later occurring falling edge will determine start write cycle. write cycle terminated earlier rising edge /WE. address inputs must kept valid throughout write cycle. must return high state minimum recovery time before another cycle initiated. control signal should kept inactive (high) during write cycles avoid contention. However, output been enabled (/CE active) then will disable outputs from falling edge. HMN1288DV provides full functional capability greater than 3.0V write protects nominal. Powerdown/power-up control circuitry constantly monitors supply power-fail-detect threshold VPFD. When falls below threshold, SRAM automatically write-protects data. inputs become "don't care" outputs high impedance. falls below approximately power switching circuit connects lithium energy soure retain data. During power-up, when rises above approximately volts, power switching circuit connects external disconnects lithium energy source. Normal operation resume after exceeds volts.
BLOCK DIAGRAM
A0-A16 DQ0-DQ7
DESCRIPTION
A0-A16 Address Input Chip Enable Ground
128K SRAM Block
Power
DQ0-DQ7 Data Data
Power Fail Control Lithium Cell
Write Enable Output Enable Power (+3.3V) Connection
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HMN1288DV
TRUTH TABLE
MODE selected Output disable Read Write OPERATION High High DOUT POWER Standby Active Active Active
ABSOLUTE MAXIMUM RATINGS
PARAMETER voltage applied relative Voltage applied excluding relative Operating temperature Storage temperature Soldering temperature SYMBOL TOPR TSTG TSOLDER RATING -0.5V Vcc+0.5 -0.3V 4.6V 70°C -65°C 150°C 260°C second VCC+0.3 CONDITIONS
NOTE: Permanent device damage occur Absolute Maximum Ratings exceeded. Functional operation should restricted Recommended Operating Condit ions detailed this data sheet. Exposure higher than recommended voltage extended periods time could affect device reliability.
RECOMMENDED OPERATING CONDITIONS TOPR
PARAMETER Supply Voltage Ground Input high voltage Input voltage SYMBOL 4.5V -0.3 TYPICAL 5.0V 5.5V Vcc+0.3V 0.8V
NOTE: Typical values indicate operation
CAPACITANCE (TA=25 f=1MHz, VCC=5.0V)
DESCRIPTION Input Capacitance Input/Output Capacitance CONDITIONS Input voltage Output voltage SYMBOL CI/O UNIT
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HMN1288DV
ELECTRICAL CHARACTERISTICS (TA= TOPR, VCCmin VCCmax
PARAMETER Input Leakage Current Output Leakage Current Output high voltage Output voltage CONDITIONS VIN=VSS /CE=VIH /OE=VIH /WE=VIL IOH=-1.0mA IOL= 2.0mA Threshold Power-fail Deselect Voltage Voltage (THS Standby supply current /CE=2.2v VCC-0.2V, Standby supply current 0.2V, VCC-0.2V Operating current Supply switch-over voltage Power supply /CE=VIL, II/O=0 Read ISB1 Select VPFD SYMBOL TYP. UNIT
NOTE: Typical values indicate operation
CHARACTERISTICS (Test Conditions)
PARAMETER Input pulse levels Input rise fall times Input output timing reference levels Output load (including scope jig) VALUE 1.5V unless otherwise specified) Figures 1and
DOUT
Figure Output Load
DOUT 1.9K
1.9K
Figure Output Load
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READ CYCLE (TA= TOPR, VCCmin VCCmax
PARAMETER Read Cycle Time Address Access Time Chip enable access time Output enable Output valid Chip enable output Output enable output Chip disable output high Output disable output high Output hold from address change SYMBOL tACC tACE tCLZ tOLZ tCHZ tOHZ Output load Output load Output load Output load Output load Output load Output load Output load CONDITIONS -120
HMN1288DV
-150
UNIT
WRITE CYCLE (TA= TOPR, Vccmin Vccmax
PARAMETER Write Cycle Time Chip enable write Address setup time Address valid write Write pulse width Write recovery time (write cycle Write recovery time (write cycle Data valid write Data hold time (write cycle Data hold time (write cycle Write enabled output high Output active from write SYMBOL tWR1 tWR2 tDH1 tDH2 Note Note Note Note Note Note Note Note Note Note CONDITIONS -120 -150
NOTE: write ends earlier transition going high going high. write occurs during over allow /WE. write begins later transition going going low. Either tWR2 must met. Either tDH2 must met. goes simultaneously going after going low, outputs remain high impedance state.
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HMN1288DV
POWER-DOWN/POWER-UP CYCLE
PARAMETER VPFD(max) VPFD(min) Fail Time VPFD(max) Fail Time VPFD(max) VPFD(min) Rise Time SYMBOL Delay after slews down Write Protect Time tWPT past VPFD before SRAM Write-protected. Chip Enable Recovery VPFD (min) Rise Time tCER CONDITIONS TYP. UNIT
TIMING WAVEFORM READ CYCLE NO.1 (Address Access)*
Address tACC DOUT Previous Data Valid Data Valid
READ CYCLE NO.2 (/CE Access)*1,3,4
tACE tCLZ DOUT High-Z
tCHZ
High-Z
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*1,5
HMN1288DV
READ CYCLE NO.3 (/OE Access)
Address tACC DOUT tOLZ High-Z tOHZ Data Valid High-Z
NOTES:
held high read cycle. Device continuously sele cted: Address valid prior coincident with transition low. Device continuously selected:
WRITE
CYCLE NO.1 (/WE-CONTROLLED)
*1,2,3
Address DOUT Data Undefined Data-in Valid High-Z tDH1 tWR1
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WRITE CYCLE NO.2 (/CE-Controlled)
*1,2,3,4,5
HMN1288DV
Address DOUT Data Undefined High-Z Data-in tDH2 tWR2
NOTE:
must high during address transition. Because active (/OE low) during this period, data input signals opposite polarity outputs must applied. high, pins remain state high impedance. Either tWR2 must met. Either tDH2 must met.
POWER-DOWN/POWER-UP
TIMING
4.75 VPFD VPFD 4.25 tWPT tCER
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HMN1288DV
PACKAGE DIMENSION
Dimension 1.680 0.720 0.365 0.015 0.008 0.590 0.015 0.090 0.080 0.120 1.680 0.740 0.375 0.025 0.013 0.630 0.021 0.110 0.110 0.160
dimensions inches.
ORDERING INFORMATION
1288
Operating Temp. Blank Commercial Industrial (-40 85°C) Speed options Operating Voltage 3.3V
type package
Device 128K Nonvolatile SRAM HANBit Memory Module
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Non-Volatile SRAM Module 1Mbit (128K 8-Bit), 32Pin-DIP, 3.3V Part HMN1

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