32Mbyte(8Mx36) 72-pin with Parity MODE Ref. SIMM Design Part HMD8M36M2
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HMD8M36M24EG
32Mbyte(8Mx36) 72-pin with Parity MODE Ref. SIMM Design Part HMD8M36M24EG
HMD8M36M24EG 36bit dynamic high density memory module. module consists twenty four CMOS 4bit DRAM 24-pin packages mounted -pin, double-sided, FR-4-printed circuit board. 0.22uF decoupling capacitor mounted printed circuit board each DRAM components. module single In-line Memory Module with edge connections intended mounting -pin edge connector sockets. module components powe from single power supply inputs outputs -compatible.
FEATURES
Part Identification HMD8M36M24E- 2048 Cycles/32ms Ref. Solder HMD8M36M24EG- 2048 Cycles/32ms Ref. Gold Access times 60ns High-density 32MByte design Single ±0.5V power supply JEDEC standard PDpin pinout mode operation compatible inputs outputs FR4-PCB design 60ns SYMBOL DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
ASSIGNMENT
SIMM 90ns 110ns tHPC 26ns 30ns SYMBOL DQ24 DQ25 DQ26 DQ17 DQ35 /CAS0 /CAS2 /CAS3 /CAS1 /RAS0 /RAS1 VIEW SYMBOL DQ27 DQ10 DQ28 DQ11 DQ29 DQ12 DQ30 DQ13 DQ31 DQ32 DQ14 DQ33 DQ15 DQ34 DQ16
OPTIONS
Timing 50ns access 60ns access Packages 72-pin SIMM
MARKING
PRESENCE DETECT PINS
50ns
PERFORMANCE RANGE
Speed tRAC 50ns 60ns tCAC 13ns 15ns
URL:www.hbe.co.kr REV.1.0 (March.2004)
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FUNCTIONAL BLOCK DIAGRAM
/RAS0 /RAS1 DQ[0-3] A[0-11] /CAS0 /RAS DQ[0-3] A[0-11] /CAS /RAS DQ[0-3] A[0-11] /CAS /RAS A[0-11] /CAS /RAS DQ[0-3] A[0-11] /CAS /RAS DQ[0-3] A[0-11] /CAS /RAS A[0-11] /CAS DQ[18-21] A[0-11] /CAS2 /RAS DQ[0-3] A[0-11] /CAS /RAS DQ[0-3] A[0-11] /CAS /RAS A[0-11] /CAS
HMD8M36M24EG
/RAS DQ[0-3] A[0-11] /CAS /RAS DQ[0-3] A[0-11] /CAS /RAS A[0-11] /CAS
DQ[4-7] A[0-11] /CAS0
DQ[22-25] A[0-11] /CAS2
A[0-11] /CAS0
DQ26 A[0-11] /CAS2
DQ[9-12] A[0-11] /CAS1
/RAS DQ[0-3] A[0-11] /CAS /RAS DQ[0-3] A[0-11] /CAS /RAS A[0-11] /CAS
/RAS DQ[0-3] A[0-11] /CAS /RAS DQ[0-3] A[0-11] /CAS /RAS A[0-11] /CAS
DQ[27-30] A[0-11] /CAS3
/RAS DQ[0-3] A[0-11] /CAS /RAS DQ[0-3] A[0-11] /CAS /RAS A[0-11] /CAS
/RAS DQ[0-3] A[0-11] /CAS /RAS DQ[0-3] A[0-11] /CAS /RAS A[0-11] /CAS
DQ[13-16] A[0-11] /CAS1
DQ[31-34] A[0-11] /CAS3
DQ17 A[0-11] /CAS1
DQ35 A[0-11] /CAS3
URL:www.hbe.co.kr REV.1.0 (March.2004)
HANBit Electronics Co.,Ltd.
Absolute Maximum Ratings
PARAMETER Voltage Relative Voltage Supply Relative Power Dissipation Storage Temperature SYMBOL ,OUT TSTG
HMD8M36M24EG
RATING 7.0V 7.0V -55oC 150oC
Short Circuit Output Current 50mA Permanent device damage occur Absolute Maximum Ratings" exceeded. Functional operation should restricted conditions detailed perational sections this data sheet. Exposure absolute maximum rating conditions extended periods affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Voltage reference TA=0 PARAMETER Supply Voltage Ground Input High Voltage Input Voltage SYMBOL -1.0 TYP. Vcc+1 UNIT
OPERATING CHARACTERISTICS
SYMBOL ICC1 SPEED ICC2 ICC3 Don't care ICC4 ICC5 ICC6 Don't care Il(L) IO(L) ICC1 Operating Current (/RAS /CAS Address cycling ICC2 Standby Current /RAS=/CAS=V ICC3 /RAS Only Refresh Current /CAS=V /RAS, Address cycling RC=min ICC4 Mode Current (/RAS=V /CAS, Address cycling PC=min
URL:www.hbe.co.kr REV.1.0 (March.2004)
RC=min.)
UNITS
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ICC5 Standby Current (/RAS=/CAS=Vcc-0.2V ICC6 /CAS-Before-/RAS Refresh Current (/RAS /CAS cycling RC=min Input Leakage Current (Any input 6.5V, other pins under test Output Leakage Current (Data disabled, VOUT 5.5V Output High Voltage Level -5mA Output Voltage Level 4.2mA
HMD8M36M24EG
NOTE: ICC1, ICC3, ICC4 ICC6 dependent output loading cycle rates. Specified values obtained with output open. specified average current. ICC3, address changed maximum once while /RAS=VIL. ICC4, address changed maximum once within page mode cycle.
CAPACITANCE
TA=25 SYMBOL CIN1 CIN3 CIN4 CDQ1
DESCRIPTION Input Capacitance (A0-A11) Input Capacitance (/W) Input Capacitance (/RAS0) Input Capacitance (/CAS0-/CAS3) Input/Output Capacitance (DQ0-31)
UNITS
CHARACTERISTICS
70oC 5V±10%, notes 1,2.)
STANDARD OPERATION Random read write cycle time Access time from /RAS Access time from /CAS Access time from column addr /CAS output Low-Z Output buffer turn-off delay Transition time (rise fall) /RAS precharge time /RAS pulse width /RAS hold time /CAS hold time /CAS pulse width /RAS /CAS delay time /RAS column address delay time /CAS /RAS precharge time address set-up time address hold time Column address set-up time
URL:www.hbe.co.kr REV.1.0 (March.2004)
SYMBOL tRAC tCAC tCLZ tOFF tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC
UNIT
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Column address hold time Column Address /RAS lead time Read command set-up time Read command hold referenced /CAS Read command hold referenced /RAS Write command hold time Write command hold referenced /RAS Write command pulse width Write command /RAS lead time Write command /CAS lead time Data-in set-up time Data-in hold time Refresh period Write command set-up time /CAS setup time (C-B-R refresh) /CAS hold time (C-B-R refresh) /RAS precharge /CAS hold time Access time from /CAS precharge /CAS precharge time (Fast page) /RAS pulse width (Fast page /RAS precharge time (C-B-R refresh) /RAS hold time (C-B-R refresh) NOTES tWRH tCAH tRAL tRCS tRCH tRRH tWCH tWCR tRWL tCWL tREF tWCS tCSR tCHR tRPC tCPA tRASP tWRP 200K
HMD8M36M24EG
200K
1.An initial pause 200ms required after power-up followed /RAS-only /CAS-before-/RAS refresh cycles
before proper device operation achieved.
2.VIH (min) (max) reference levels measuring timing input signals. Transition times measured between
VIH(min) VIL(max) assumed inputs.
3.Measured with load equivalent 1TTL loads 100pF 4.Operation within RCD(max) limit insures that RAC(max) met. RCD(max) specified reference point only.
greater than specified RCD(max) limit, then access time controlled exclusively CAC.
5.Assumes that tRCD(max)
tAR, tWCR, tDHR referenced RAD(max) 7.This parameter defines time which output achieves open circuit conditi referenced VOL. tWCS, tRWD, tCWD tAWD restrictive operating parameter. They included data sheet electrical characteristic only. tWCS(min) cycle early write cycle data will remain high impedance duration cycle. Either tRCH tRRH must satisfied read cycle. These parameters referenced /CAS leading edge early write cycles leading edge read write cycles.
URL:www.hbe.co.kr REV.1.0 (March.2004)
HANBit Electronics Co.,Ltd.
HMD8M36M24EG
Operation within RAD(max) limit insures that RAC(max) met. RAD(max) specified reference point only. greater than specified RAD(max) limit. then access time controlled
TIMING DIAGRAMS TIMING WAVEFORM READ CYCLE
/RAS VIHVILtCRP /CAS VIHVILA VIHVIL/W VIHVIL/OE VIHVILDQ0-DQ7 OHVOLOPEN
tRAS tRCD tRAD tASR tRAH tASC tCAH
COLUMN ADDRESS
tCSH
tRSH tCAS tRAL
tCRP
ADDRESS
tRCS tOEA tCAC tRAC tCLZ
tRRH
tRCH tWEZ tCEZ
tOEZ
tREZ
DATA-OUT
TIMING WAVEFORM WRITE CYCLE (EARLY WRITE) NOTE Dout Open
tRAS tCRP tRCD tRAD tASR tRAH tASC tCAH
COLUMN ADDRESS
/RAS
VIHVILVIHVIL-
tCSH
tRSH tCAS tRAL
tCRP
/CAS
VIHVIL-
ADDRESS
tCWL tRWL tWCS tWCH
VIHVIL/OE VIHVILDQ0-DQ7
VOHVOL-6DATA-IN
URL:www.hbe.co.kr REV.1.0 (March.2004)
HANBit Electronics Co.,Ltd.
PACKAGING INFORMATION
SIMM Design (Front)
HMD8M36M24EG
0.25mm
2.54
1.27
Gold: 1.04±0.10 Solder: 0.914±0.10
(Solder Gold Plating)
Thickness 1.27
0.10
ORDERING INFORMATION
Part Number Density Org. Package Component Number 24EA 24EA Access Time
HMD8M36M24EG-5 HMD8M36M24EG-6
32MByte 32MByte
36bit 36bit
72Pin-SIMM 72Pin-SIMM
50ns 60ns
URL:www.hbe.co.kr REV.1.0 (March.2004)
HANBit Electronics Co.,Ltd.
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