32Mbyte(8Mx36) 72-pin with Parity MODE Ref. SIMM Design Part HMD8M36M1

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32Mbyte(8Mx36) 72-pin with Parity MODE Ref. SIMM Design Part HMD8M36M1

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HMD8M36M18G
32Mbyte(8Mx36) 72-pin with Parity MODE Ref. SIMM Design Part HMD8M36M18, HMD8M36M18G
HMD8M36M18G 36bit dynamic high density memory module. module consists sixteen CMOS 4bit DRAM 24-pin packages CMOS 4bit Quad-CAS DRAM 28pin packages mounted 72-pin, double-sided, FR-4-printed circuit board. 0.22uF decoupling capacitor mounted printed circuit board each DRAM components. module single In-line Memory Module with edge connections intended mounting 72-pin edge connector sockets. module components powered from single power supply inputs outputs TTL-compatible.
ASSIGNMENT FEATURES
Part Identification HMD8M36M18- 2048 Cycles/32ms Ref. Solder Lead HMD8M36M18G- 2048 Cycles/32ms Ref. Gold Lead Access times 60ns High-density 32MByte design Single ±0.5V power supply JEDEC standard PDpin pinout Fast Page with Parity mode operation /CAS-before-/RAS refresh capability w/RAS-only Hidden refresh capability compatible inputs outputs FR4-PCB design SYMBOL DQ18 DQ19 DQ20 DQ21 SYMBOL DQ22 DQ23 DQ24 DQ25 DQ26 SYMBO DQ17 DQ35 /CAS0 /CAS2 /CAS3 /CAS1 /RAS0 /RAS1 DQ27 DQ10 DQ28 DQ11 DQ29 SYMBOL DQ12 DQ30 DQ13 DQ31 DQ32 DQ14 DQ33 DQ15 DQ34 DQ16
OPTIONS
Timing 50ns access 60ns access Packages 72-pin SIMM
MARKING
PRESENCE DETECT PINS(Optional)
50ns 60ns
SIMM VIEW
PERFORMANCE RANGE
Speed tRAC 50ns 60ns tCAC 13ns 15ns 90ns 110ns
Note: used only Ref.
URL:www.hbeoc.kr REV.1.0 (August.2002)
HANBit Electronics Co.,Ltd.
FUNCTIONAL BLOCK DIAGRAM
HMD8M36M18G
/CAS0 /RAS0
/CAS0 /RAS0
A0-A10
DQ0-3
/CAS0 /RAS1 A0-A10
/CAS0 /RAS0
A0-A10
DQ4-7
/CAS0 /RAS1 A0-A10
/CAS1
/CAS1 /RAS0
A0-A10
A0-A10
DQ9-12
/CAS1 /RAS1
/CAS1 /RAS0
A0-A10
DQ13-16
/CAS1 /RAS1 A0-A10
/CAS0 /CAS1 /CAS2 /CAS3 /RAS0
DQ17 DQ26 DQ35
A0-A10
/CAS0 /CAS1 /CAS2 /CAS3 /RAS1 A0-A10
/CAS2
/CAS2 /RAS0 /CAS2 /RAS0
A0-A10 A0-A10 A0-A10 A0-A10
DQ18-21 DQ22-25 DQ27-30 DQ31-34
/CAS2 /RAS1 A0-A10
/CAS2 /RAS1 A0-A10
/CAS3
/CAS3 /RAS0 /CAS3 /RAS0
/CAS3 /RAS1 A0-A10
/CAS3 /RAS1 A0-A10
0.1uF Capacitor each DRAM HANBit Electronics Co.,Ltd. 0.22uF
A0-A10
URL:www.hbeoc.kr REV.1.0 (August.2002)
ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage Relative Voltage Supply Relative Power Dissipation Storage Temperature SYMBOL ,OUT TSTG
HMD8M36M18G
RATING 7.0V 7.0V -55oC 150oC
Short Circuit Output Current 50mA Permanent device damage occur Absolute Maximum Ratings" exceeded. Functional operation should restricted conditions detailed operational sections this data sheet. Exposure absolute maximum rating conditions extended periods affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Voltage reference VSS, TA=0 PARAMETER Supply Voltage Ground Input High Voltage Input Voltage SYMBOL -1.0 TYP. Vcc+1 UNIT
OPERATING CHARACTERISTICS
SYMBOL ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 Il(L) IO(L) ICC1 Operating Current (/RAS /CAS Address cycling RC=min.) ICC2 Standby Current /RAS=/CAS=VIH ICC3 /RAS Only Refresh Current /CAS=VIH, /RAS, Address cycling @tRC=min
URL:www.hbeoc.kr REV.1.0 (August.2002)
SPEED
1008 1008 1008
UNITS
Don't care
Don't care
HANBit Electronics Co.,Ltd.
ICC4 Fast Page Mode Current (/RAS=VIL, /CAS, Address cycling @tPC=min ICC5 Standby Current (/RAS=/CAS=Vcc-0.2V ICC6 /CAS-Before-/RAS Refresh Current (/RAS /CAS cycling RC=min Input Leakage Current (Any input 6.5V, other pins under test Output Leakage Current (Data disabled, VOUT 5.5V Output High Voltage Level (IOH= -5mA Output Voltage Level (IOL 4.2mA
HMD8M36M18G
NOTE: ICC1, ICC3, ICC4 ICC6 dependent output loading cycle rates. Specified values obtained with output open. specified average current. ICC1 ICC3, address changed maximum once while /RAS=VIL. ICC4, address changed maximum once within page mode cycle.
CAPACITANCE
TA=25 DESCRIPTION SYMBOL CIN1 CIN3 CIN4 CDQ1 UNITS
Input Capacitance [A0-A11(A10)] Input Capacitance (/W) Input Capacitance (/RAS0) Input Capacitance (/CAS0-/CAS3) Input/Output Capacitance (DQ0-31)
CHARACTERISTICS
70oC 5V±10%, notes 1,2.) UNIT
HANBit Electronics Co.,Ltd.
STANDARD OPERATION Random read write cycle time Access time from /RAS Access time from /CAS Access time from column address /CAS output Low-Z Output buffer turn-off delay Transition time (rise fall) /RAS precharge time /RAS pulse width /RAS hold time /CAS hold time /CAS pulse width /RAS /CAS delay time /RAS column address delay time /CAS /RAS precharge time address set-up time address hold time
URL:www.hbeoc.kr REV.1.0 (August.2002)
SYMBOL tRAC tCAC tCLZ tOFF tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH
Column address set-up time Column address hold time Column Address /RAS lead time Read command set-up time Read command hold referenced /CAS Read command hold referenced /RAS Write command hold time Write command hold referenced /RAS Write command pulse width Write command /RAS lead time Write command /CAS lead time Data-in set-up time Data-in hold time Refresh period Write command set-up time /CAS setup time (C-B-R refresh) /CAS hold time (C-B-R refresh) /RAS precharge /CAS hold time Access time from /CAS precharge /CAS precharge time (Fast page) /RAS pulse width (Fast page /RAS precharge time (C-B-R refresh) /RAS hold time (C-B-R refresh) tASC tCAH tRAL tRCS tRCH tRRH tWCH tWCR tRWL tCWL tREF tWCS tCSR tCHR tRPC tCPA tRASP tWRP tWRH 200K
HMD8M36M18G
200K
NOTES 1.An initial pause 200µs required after power-up followed /RAS-only /CAS-before-/RAS refresh cycles before proper device operation achieved. 2.VIH (min) (max) reference levels measuring timing input signals. Transition times measured between VIH(min) VIL(max) assumed inputs. 3.Measured with load equivalent 1TTL loads 100pF 4.Operation within tRCD(max) limit insures that tRAC(max) met. tRCD(max) specified reference point only. tRCD greater than specified tRCD(max) limit, then access time controlled exclusively CAC. 5.Assumes that tRCD tRCD(max) tAR, tWCR, tDHR referenced tRAD(max) 7.This parameter defines time which output achieves open circuit condition referenced VOL. tWCS, tRWD, tCWD tAWD restrictive operating parameter. They included data sheet electrical characteristic only. tWCS(min) cycle early write cycle data will remain high impedance duration cycle. Either tRCH tRRH must satisfied read cycle. These parameters referenced /CAS leading edge early write cycles leading edge readwrite cycles. Operation within tRAD(max) limit insures that tRAC(max) met. tRAD(max) specified reference point only. tRAD greater than specified tRAD(max) limit. then access time controlled tAA.
URL:www.hbeoc.kr REV.1.0 (August.2002)
HANBit Electronics Co.,Ltd.
TIMING DIAGRAMS
TIMING WAVEFORM READ CYCLE
HMD8M36M18G
VIH/RAS
tRAS tCRP tRCD tRAD tASR tRAH tASC tCAH
COLUMN ADDRESS
VILtCSH tRSH tCAS tRAL tCRP
/CAS VIH-
VILVIHA
VILVIH-
ADDRESS
tRCS
tRRH tCAC tCLZ
tRCH
VIL-
tOFF
DQ0-DQ7 VOHVOL-
tRAC
OPEN
DATA-OUT
TIMING WAVEFORM WRITE CYCLE (EARLY WRITE) NOTE Dout Open
/RAS VIH-
tRAS tCRP tRCD tRAD tASR tRAH tASC tCAH
COLUMN ADDRESS
VILtCSH tRSH tCAS tRAL tCRP
VIH/CAS
VILVIHVILROW ADDRESS
tCWL tRWL tWCS tWCH
DATA-IN
VIH/W VIL-
DQ0-DQ7
VOHVOL-
URL:www.hbeoc.kr REV.1.0 (August.2002)
HANBit Electronics Co.,Ltd.
PACKAGING INFORMATION
SIMM Design (Front)
HMD8M36M18G
0.25
2.54
1.29 ±0.08mm
Gold 1.04±0.10 1.27 Solder:0.914±0.10mm
ORDERING INFORMATION
Part Number
Density
Org.
Package
SPEED
HMD8M36M18G-5 HMD8M36M18G-6
32MByte 32MByte
36bit 36bit
Pin-SIMM Pin-SIMM
5.0V 5.0V
50ns 60ns
URL:www.hbeoc.kr REV.1.0 (August.2002)
HANBit Electronics Co.,Ltd.

32Mbyte(8Mx36) 72-pin with Parity MODE Ref. SIMM Design Part HMD8M36M1

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