32Mbyte(8Mx32) 72-pin Mode Ref. SIMM Design Part HMD8M32M4E, HMD8M32M4
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HMD8M32M4EG
32Mbyte(8Mx32) 72-pin Mode Ref. SIMM Design Part HMD8M32M4E, HMD8M32M4EG
HMD8M32M4E 32bit dynamic high density memory module. module consists four CMOS DRAMs 50-pin TSOP packages mounted 72-pin, double-sided, FR-4-printed circuit board. 0.1uF 0.22uF decoupling capacitor mounted printed circuit board each DRAM components. module single In-line memory module with edge connections intended mounting 72-pin edge connector sockets. module components powered from single power supply inputs outputs TTL-compatible.
FEATURES
Part Identification HMD8M32M4E-4K Cycles/64ms Ref. Solder HMD8M32M4EG- Cycles/64ms Ref. Gold Access times 60ns High-density 32MByte design Single 0.5V power supply JEDEC Standard pinout mode operation compatible inputs outputs FR4-PCB design
ASSIGNMENT
SYMBOL DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 SYMBOL DQ22 DQ23 /CAS0 /CAS2 /CAS3 /CAS1 /RAS0 /RAS1 SYMBOL DQ24 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 DQ29 DQ13 DQ30 DQ14 DQ31 DQ15
OPTIONS
Timing 50ns access 60ns access Packages 72-pin SIMM
MARKING
60ns
PRESENCE DETECT PINS
50ns
PERFORMANCE RANGE
Speed tRAC 50ns 60ns tCAC 13ns 15ns 90ns 110ns tHPC 26ns 30ns
URL:www.hbe.co.kr REV.1.0 (August. 2002)
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FUNCTIONAL BLOCK DIAGRAM
HMD8M32M4EG
/RAS0
/RAS
/CAS0
/LCAS
/CAS1 /UCAS
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
A0-A11
DQ0-15 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
/RAS /RAS1
/CAS0 /LCAS /CAS1 /UCAS
A0-A11
/RAS0 /RAS /CAS2 /LCAS /CAS3
DQ16-31
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
/RAS /RAS1
/LCAS
/CAS2
/UCAS DQ10 DQ11 DQ12 DQ13 DQ14 A0-A11 DQ15
/UCAS
/CAS3
A0-A11
A0-A11
0.1uf 0.22uf Capacitor each DRAM DRAMs
URL:www.hbe.co.kr REV.1.0 (August. 2002)
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ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage Relative Voltage Supply Relative Power Dissipation Storage Temperature SYMBOL ,OUT TSTG
HMD8M32M4EG
RATING 7.0V 7.0V -55oC 150oC
Short Circuit Output Current 50mA Permanent device damage occur Absolute Maximum Ratings" exceeded. Functional operation should restricted conditions detailed operational sections this data sheet. Exposure absolute maximum rating conditions extended periods affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Voltage reference VSS, TA=0 PARAMETER Supply Voltage Ground Input High Voltage Input Voltage SYMBOL -1.0 TYP. Vcc+1 UNIT
OPERATING CHARACTERISTICS
SYMBOL ICC1 SPEED ICC2 ICC3 Don't care ICC4 ICC5 ICC6 Don't care Il(L) IO(L) ICC2 Standby Current /RAS=/CAS=VIH ICC3 /RAS Only Refresh Current /CAS=V /RAS, Address cycling @tRC=min ICC4 Fast Page Mode Current (/RAS=VIL, /CAS, Address cycling @tPC=min
URL:www.hbe.co.kr REV.1.0 (August. 2002)
UNITS
ICC1 Operating Current (/RAS /CAS Address cycling RC=min.)
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ICC5 Standby Current (/RAS=/CAS=Vcc-0.2V ICC6 /CAS-Before-/RAS Refresh Current (/RAS /CAS cycling RC=min Input Leakage Current (Any input 6.5V, other pins under test Output Leakage Current (Data disabled, VOUT 5.5V Output High Voltage Level (IOH= -5mA Output Voltage Level (IOL 4.2mA
HMD8M32M4EG
NOTE: ICC1, ICC3, ICC4 ICC6 dependent output loading cycle rates. Specified values obtained with output open. specified average current. ICC1 ICC3, address changed maximum once while /RAS=VIL. ICC4, address changed maximum once within page mode cycle.
CAPACITANCE
TA=25 SYMBOL CIN1 CIN3 CIN4 CDQ1
DESCRIPTION Input Capacitance (A0-A11) Input Capacitance (/W) Input Capacitance (/RAS0) Input Capacitance (/CAS0-/CAS3) Input/Output Capacitance (DQ0-31)
UNITS
CHARACTERISTICS
70oC 5V±10%, notes 1,2.) UNIT
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STANDARD OPERATION Random read write cycle time Access time from /RAS Access time from /CAS Access time from column address /CAS output Low-Z Output buffer turn-off delay Transition time (rise fall) /RAS precharge time /RAS pulse width /RAS hold time /CAS hold time /CAS pulse width /RAS /CAS delay time /RAS column address delay time /CAS /RAS precharge time address set-up time address hold time Column address set-up time
URL:www.hbe.co.kr REV.1.0 (August. 2002)
SYMBOL tRAC tCAC tCLZ tOFF tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC
Column address hold time Column Address /RAS lead time Read command set-up time Read command hold referenced /CAS Read command hold referenced /RAS Write command hold time Write command hold referenced /RAS Write command pulse width Write command /RAS lead time Write command /CAS lead time Data-in set-up time Data-in hold time Refresh period Write command set-up time /CAS setup time (C-B-R refresh) /CAS hold time (C-B-R refresh) /RAS precharge /CAS hold time Access time from /CAS precharge /CAS precharge time (Fast page) /RAS pulse width (Fast page /RAS precharge time (C-B-R refresh) /RAS hold time (C-B-R refresh) NOTES tCAH tRAL tRCS tRCH tRRH tWCH tWCR tRWL tCWL tREF tWCS tCSR tCHR tRPC tCPA tRASP tWRP tWRH 200K
HMD8M32M4EG
200K
1.An initial pause 200µs required after power-up followed /RAS-only /CAS-before-/RAS refresh cycles
before proper device operation achieved.
2.VIH (min) (max) reference levels measuring timing input signals. Transition times measured between
VIH(min) VIL(max) assumed inputs.
3.Measured with load equivalent 1TTL loads 100pF 4.Operation within tRCD(max) limit insures that tRAC(max) met. tRCD(max) specified reference point only. tRCD
greater than specified tRCD(max) limit, then access time controlled exclusively CAC.
5.Assumes that tRCD tRCD(max)
tAR, tWCR, tDHR referenced tRAD(max) 7.This parameter defines time which output achieves open circuit condition referenced VOL. tWCS, tRWD, tCWD tAWD restrictive operating parameter. They included data sheet electrical characteristic only. tWCS tWCS(min) cycle early write cycle data will remain high impedance duration cycle. Either tRCH tRRH must satisfied read cycle. These parameters referenced /CAS leading edge early write cycles leading edge readwrite cycles. Operation within tRAD(max) limit insures that tRAC(max) met. tRAD(max) specified reference
URL:www.hbe.co.kr REV.1.0 (August. 2002)
HANBit Electronics Co.,Ltd.
HMD8M32M4EG
point only. tRAD greater than specified tRAD(max) limit. then access time controlled tAA.
TIMING DIAGRAMS
TIMING WAVEFORM READ CYCLE
/RAS
VIHVILtCRP tRCD tRAD tASR tRAH tASC
tRAS tCSH tRSH tCAS tCAH
COLUMN ADDRESS
tCRP
/UCAS,/LCAS
VIHVIL-
tRAL
VIHVILROW ADDRESS
tRCS VIHVIL/OE VIHVILDQ0-DQ15 VOHVOLOPEN
tRRH tOEA tCAC tCLZ
tRCH tWEZ tCEZ
tOEZ
tRAC
DATA-OUT
TIMING WAVEFORM WRITE CYCLE (EARLY WRITE) NOTE Dout Open
/RAS
VIHVILtCRP tRCD tRAD tASR tRAH tASC tCAH
COLUMN ADDRESS
tRAS tCSH tRSH tCAS tRAL
tCRP
VIH/UCAS,/LCAS ILVIHA VIL-
ADDRESS
tCWL tRWL tWCS tWCH
VIH/W VILVIH/OE VILVOHDQ0-DQ15 VOL-
DATA-IN
URL:www.hbe.co.kr REV.1.0 (August. 2002)
HANBit Electronics Co.,Ltd.
PACKAGING INFORMATION
HMD8M32M4EG
107.95 101.19 3.38 R1.57 R3.18±0.51m
18.52mm 10.16 6.35 2.03 6.5mm 6.35 95.25 R1.57±10
7.68 2.54
0.25
Gold 1.04±0.10 1.27 Solder:0.914±0.10mm 1.29±0.08
ORDERING INFORMATION
Part Number
Density
Org.
Package
SPEED
HMD8M32M4EG-5 HMD8M32M4EG-6
32MByte 32MByte
32bit 32bit
Pin-SIMM Pin-SIMM
5.0V 5.0V
50ns 60ns
URL:www.hbe.co.kr REV.1.0 (August. 2002)
HANBit Electronics Co.,Ltd.
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