32Mbyte(8Mx32) 72-pin MODE Ref. SIMM Design Part HMD8M32M16EG HMD
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HMD8M32M16EG
32Mbyte(8Mx32) 72-pin MODE Ref. SIMM Design Part HMD8M32M16EG
HMD8M32M16EG 32bit dynamic high density memory module. module consists sixteen CMOS 4bit DRAMs 24-pin packages mounted 72-pin, double-sided, FR-4-printed circuit board. 0.22uF decoupling capacitor mounted printed circuit board each DRAM components. module single In-line Memory Module with edge connections intended mounting 72-pin edge connector sockets. module components powered from single power supply inputs outputs TTL-compatible.
FEATURES
Part Identification HMD8M32M16EG- 2048 Cycles/32ms Ref. Gold Access times 60ns High-density 32MByte design Single ±0.5V power supply JEDEC standard PDpin pinout mode operation compatible inputs outputs FR4-PCB design
ASSIGNMENT
SYMBOL DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 SYMBOL DQ22 DQ23 /CAS0 /CAS2 /CAS3 /CAS1 /RAS0 /RAS1 SIMM 90ns 110ns tHPC 26ns 30ns VIEW
Note: used HMD8M32M16EG
SYMBOL DQ24 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 DQ29 DQ13 DQ30 DQ14 DQ31 DQ15
OPTIONS
Timing 50ns access 60ns access Packages 72-pin SIMM
MARKING
60ns
PRESENCE DETECT PINS
50ns
PERFORMANCE RANGE
Speed tRAC 50ns 60ns tCAC 13ns 15ns
URL:www.hbe.co.kr REV.1.0 (August.2002)
HANBit Electronics Co.,Ltd.
HMD8M32M16EG
FUNCTIONAL BLOCK DIAGRAM
/CAS0
/RAS0
/CAS /RAS -A10(A11)
DQ0-3
/CAS /RAS A0-A10(A11)
/RAS1
/CAS /RAS -A10(A11)
/CAS1
DQ4-7
/CAS /RAS A0-A10(A11)
/CAS /RAS -A10(A11).
DQ8-11
/CAS /RAS A0-A10(A11)
/CAS /RAS -A10(A11).
/CAS2
DQ12-15
/CAS /RAS A0-A10(A11)
/CAS /RAS -A10(A11).
DQ16-19
/CAS /RAS A0-A10(A11)
/CAS /RAS -A10(A11).
/CAS3
DQ20-23
/CAS /RAS A0-A10(A11)
/CAS /RAS -A10(A11)
DQ24-27
/CAS /RAS A0-A10(A11)
/CAS /RAS -A10(A11).
A0-A10 (A11)
DQ28-31
/CAS /RAS A0-A10(A11)
URL:www.hbe.co.kr REV.1.0 (August.2002)
HANBit Electronics Co.,Ltd.
ABSOLUTE MAXIMUM RATINGS PARAMETER Voltage Relative Voltage Supply Relative Power Dissipation Storage Temperature SYMBOL ,OUT TSTG
HMD8M32M16EG
RATING 7.0V 7.0V -55oC 150oC
Short Circuit Output Current 50mA Permanent device damage occur Absolute Maximum Ratings" exceeded. Functional operation should restricted conditions detailed operational sections this data sheet. Exposure absolute maximum rating conditions extended periods affect device reliability.
RECOMMENDED OPERATING CONDITIONS Voltage reference VSS, TA=0 PARAMETER Supply Voltage Ground Input High Voltage Input Voltage SYMBOL -1.0 TYP. Vcc+1 UNIT
OPERATING CHARACTERISTICS SYMBOL ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 Il(L) IO(L) ICC2 Standby Current /RAS=/CAS=VIH ICC3 /RAS Only Refresh Current /CAS=VIH, /RAS, Address cycling @tRC=min ICC4 Fast Page Mode Current (/RAS=VIL, /CAS, Address cycling @tPC=min
URL:www.hbe.co.kr REV.1.0 (August.2002) HANBit Electronics Co.,Ltd.
SPEED
UNITS
Don't care
Don't care
ICC1 Operating Current (/RAS /CAS Address cycling RC=min.)
ICC5 Standby Current (/RAS=/CAS=Vcc-0.2V ICC6 /CAS-Before-/RAS Refresh Current (/RAS /CAS cycling RC=min
HMD8M32M16EG
Input Leakage Current (Any input 6.5V, other pins under test Output Leakage Current (Data disabled, VOUT 5.5V Output High Voltage Level (IOH= -5mA Output Voltage Level (IOL 4.2mA NOTE: ICC1, ICC3, ICC4 ICC6 dependent output loading cycle rates. Specified values obtained with output open. specified average current. ICC1 ICC3, address changed maximum once while /RAS=VIL. ICC4, address changed maximum once within page mode cycle.
CAPACITANCE
TA=25 DESCRIPTION SYMBOL CIN1 CIN3 CIN4 CDQ1 UNITS
Input Capacitance (A0-A11) Input Capacitance (/W) Input Capacitance (/RAS0) Input Capacitance (/CAS0-/CAS3) Input/Output Capacitance (DQ0-31)
CHARACTERISTICS
70oC 5V±10%, notes 1,2.) UNIT
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STANDARD OPERATION Random read write cycle time Access time from /RAS Access time from /CAS Access time from column address /CAS output Low-Z Output buffer turn-off delay Transition time (rise fall) /RAS precharge time /RAS pulse width /RAS hold time /CAS hold time /CAS pulse width /RAS /CAS delay time /RAS column address delay time /CAS /RAS precharge time address set-up time address hold time Column address set-up time
URL:www.hbe.co.kr REV.1.0 (August.2002)
SYMBOL tRAC tCAC tCLZ tOFF tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC
Column address hold time Column Address /RAS lead time Read command set-up time Read command hold referenced /CAS Read command hold referenced /RAS Write command hold time Write command hold referenced /RAS Write command pulse width Write command /RAS lead time Write command /CAS lead time Data-in set-up time Data-in hold time Refresh period Write command set-up time /CAS setup time (C-B-R refresh) /CAS hold time (C-B-R refresh) /RAS precharge /CAS hold time Access time from /CAS precharge /CAS precharge time (Fast page) /RAS pulse width (Fast page /RAS precharge time (C-B-R refresh) /RAS hold time (C-B-R refresh) NOTES tWRH tCAH tRAL tRCS tRCH tRRH tWCH tWCR tRWL tCWL tREF tWCS tCSR tCHR tRPC tCPA tRASP tWRP 200K
HMD8M32M16EG
200K
1.An initial pause 200µs required after power-up followed /RAS-only /CAS-before-/RAS refresh cycles
before proper device operation achieved.
2.VIH (min) (max) reference levels measuring timing input signals. Transition times measured between
VIH(min) VIL(max) assumed inputs.
3.Measured with load equivalent 1TTL loads 100pF 4.Operation within tRCD(max) limit insures that tRAC(max) met. tRCD(max) specified reference point only. tRCD
greater than specified tRCD(max) limit, then access time controlled exclusively CAC.
5.Assumes that tRCD tRCD(max)
tAR, tWCR, tDHR referenced tRAD(max) 7.This parameter defines time which output achieves open circuit condition referenced VOL. tWCS, tRWD, tCWD tAWD restrictive operating parameter. They included data sheet electrical characteristic only. tWCS(min) cycle early write cycle data will remain high impedance duration cycle. Either tRCH tRRH must satisfied read cycle. These parameters referenced /CAS leading edge early write cycles leading edge readwrite cycles.
URL:www.hbe.co.kr REV.1.0 (August.2002) HANBit Electronics Co.,Ltd.
HMD8M32M16EG
Operation within tRAD(max) limit insures that tRAC(max) met. tRAD(max) specified reference point only. tRAD greater than specified tRAD(max) limit. then access time controlled tAA.
TIMING DIAGRAMS TIMING WAVEFORM READ CYCLE
/RAS
VIHVILtCRP tRCD tRAD tASR tRAH tASC
tRAS tCSH tRSH tCAS tCAH
COLUMN ADDRESS
tCRP
/CAS
VIHVIL-
tRAL
VIHVILROW ADDRESS
tRCS VIHVIL/OE VIHVILDQ0-DQ7 VOHVOLOPEN
tRRH tOEA tCAC tCLZ tREZ
tRCH tWEZ tCEZ
tOEZ
tRAC
DATA-OUT
TIMING WAVEFORM WRITE CYCLE (EARLY WRITE) NOTE Dout Open
tRAS tCRP tRCD tRAD tASR tRAH tASC tCAH
COLUMN ADDRESS
VIH/RAS VIL-
tCSH
tRSH tCAS tRAL
tCRP
VIH/CAS VILVIHA VILROW ADDRESS
tCWL tRWL tWCS tWCH
VIH/W VILVIHVILtDS DQ0-DQ7 VOHVOLURL:www.hbe.co.kr REV.1.0 (August.2002) DATA-IN HANBit Electronics Co.,Ltd.
PACKAGING INFORMATION
SIMM Design
HMD8M32M16EG
108.0 3.38 1.57 101.19 3.18 0.51
21.50 10.16 6.35
2.03 1.02 6.35 95.25 6.35 1.27 3.34
0.25
2.54
1.29 ±0.08mm
Gold 1.04±0.10 1.27 Solder:0.914±0.10mm
ORDERING INFORMATION
Component Number 16EA 16EA
Part Number
Density
Org.
Package
Access Time
HMD8M32M16EG-5 HMD8M32M16EG-6
32MByte 32MByte
32bit 32bit
72Pin-SIMM 72Pin-SIMM
50ns 60ns
URL:www.hbe.co.kr REV.1.0 (August.2002)
HANBit Electronics Co.,Ltd.
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