8Mbyte(2Mx32) Mode, Refresh 72Pin SIMM, Design Part HMD2M32M4EAG

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8Mbyte(2Mx32) Mode, Refresh 72Pin SIMM, Design Part HMD2M32M4EAG

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HMD2M32M4EAG
8Mbyte(2Mx32) Mode, Refresh 72Pin SIMM, Design Part HMD2M32M4EAG
HMD2M32M4EAG 32bit dynamic high-density memory module. module consists four CMOS 16bit DRAMs 42-pin packages mounted 72-pin, double-sided, FR-4-printed circuit board. 0.22uF decoupling capacitor mounted printed circuit board each DRAM components. module single In-line Memory Module with edge connections intended mounting 72-pin edge connector sockets. module components powered from single power supply inputs outputs TTL-compatible.
FEATURES
Part Identification HMD2M32M4EAG 1024 Cycles/32ms Gold Access times 60ns High-density 8MByte design Single ±0.5V power supply JEDEC standard pinout mode operation compatible inputs outputs FR4-PCB design
ASSIGNMENT
SYMBOL DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 SYMBOL DQ22 DQ23 /RAS3 /RAS2 /CAS0 /CAS2 /CAS3 /CAS1 /RAS0 /RAS1 SYMBOL DQ24 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 DQ29 DQ13 DQ30 DQ14 DQ31 DQ15
OPTIONS
Timing 50ns access 60ns access 70ns access Packages 72-pin SIMM
MARKING
PERFORMANCE RANGE
Speed tRAC 50ns 60ns 70ns tCAC 15ns 15ns 15ns 90ns 110ns 130ns
PRESENCE DETECT PINS
URL:www.hbe.co.kr REV. (August.2002)
50ns
60ns
70ns
HANBit Electronics Co.,Ltd.
`FUNCTIONAL BLOCK DIAGRAM
DQ0-15
HMD2M32M4EAG
/RAS0
/RAS
/CAS0
/LCAS
/CAS1
/UCAS
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 A0-A11
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
/RAS1 /RAS /CAS0 /CAS1
LCAS
/UCAS
A0-A11
DQ16-31
/RAS2
/RAS
/CAS2
/LCAS
/CAS3
/UCAS
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
/RAS /RAS3 /CAS2 /LCAS /CAS3 /UCAS
A0-A11 A0-A11
A0-A11
or0.22 Capacitor foreachDRAM DRAMs
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ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage Relative Voltage Supply Relative Power Dissipation Storage Temperature SYMBOL ,OUT TSTG
HMD2M32M4EAG
RATING 7.0V 7.0V -55oC 150oC
Short Circuit Output Current 50mA Permanent device damage occur Absolute Maximum Ratings" exceeded. Functional operation should restricted conditions detailed operational sections this data sheet. Exposure absolute maximum rating conditions extended periods affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference VSS, TA=0 PARAMETER Supply Voltage Ground Input High Voltage Input Voltage SYMBOL -1.0 Vcc+1 UNIT
OPERATING CHARACTERISTICS
SYMBOL ICC1 ICC2 ICC3 SPEED UNITS
ICC4 ICC5 ICC6 Il(L) IO(L)
ICC1 Operating Current (/RAS /CAS Address cycling RC=min.) ICC2 Standby Current /RAS=/CAS=VIH ICC3 /RAS Only Refresh Current /CAS=V /RAS, Address cycling @tRC=min ICC4 Fast Page Mode Current (/RAS=VIL, /CAS, Address cycling @tPC=min ICC5 Standby Current (/RAS=/CAS=Vcc-0.2V ICC6 /CAS-Before-/RAS Refresh Current (/RAS /CAS cycling RC=min Input Leakage Current (Any input 6.5V, other pins under test Output Leakage Current (Data disabled, VOUT 5.5V Output High Voltage Level (IOH= -5mA Output Voltage Level (IOL 4.2mA
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HMD2M32M4EAG
NOTE: ICC1, ICC3, ICC4 ICC6 dependent output loading cycle rates. Specified values obtained with output open. specified average current. ICC1 ICC3, address changed maximum once while /RAS=VIL. ICC4, address changed maximum once within page mode cycle.
CAPACITANCE TA=25
DESCRIPTION Input Capacitance (A0-A10) Input Capacitance (/W) Input Capacitance (/RAS0) Input Capacitance (/CAS0-/CAS3) Input/Output Capacitance (DQ0-31)
SYMBOL CIN1 CIN3 CIN4 CDQ1
UNITS
CHARACTERISTICS 70oC 5V±10%, notes 1,2.)
STANDARD OPERATION Random read write cycle time Access time from /RAS Access time from /CAS Access time from column address /CAS output Low-Z Output buffer turn-off delay Transition time (rise fall) /RAS precharge time /RAS pulse width /RAS hold time /CAS hold time /CAS pulse width /RAS /CAS delay time /RAS column address delay time /CAS /RAS precharge time address set-up time address hold time Column address set-up time Column address hold time Column Address /RAS lead time Read command set-up time Read command hold referenced /CAS
URL:www.hbe.co.kr REV. (August.2002)
UNIT
SYMBOL tRAC tCAC tCLZ tOFF tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH
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Read command hold referenced /RAS Write command hold time Write command pulse width Write command /RAS lead time Write command /CAS lead time Data-in set-up time Data-in hold time Refresh period Ref. tRRH tWCH tRWL tCWL tREF tWCS tCSR tCHR tRPC tCPA tRASP tWRP tWRH
HMD2M32M4EAG
200K 200K
Write command set-up time /CAS setup time (C-B-R refresh) /CAS hold time (C-B-R refresh) /RAS precharge /CAS hold time Access time from /CAS precharge /CAS precharge time (Fast page) /RAS pulse width (Fast page /RAS precharge time (C-B-R refresh) /RAS hold time (C-B-R refresh) NOTES
1.An initial pause 200µs required after power-up followed /RAS-only /CAS-before-/RAS refresh cycles
before proper device operation achieved.
2.VIH (min) (max) reference levels measuring timing input signals. Transition times measured between
VIH(min) VIL(max) assumed inputs.
3.Measured with load equivalent 2TTL loads 100pF 4.Operation within tRCD(max) limit insures that tRAC(max) met. tRCD(max) specified reference point only. tRCD
greater than specified tRCD(max) limit, then access time controlled exclusively CAC.
5.Assumes that tRCD tRCD(max)
tAR, tWCR, tDHR referenced tRAD(max) 7.This parameter defines time which output achieves open circuit condition referenced VOL. tWCS, tRWD, tCWD tAWD restrictive operating parameter. They included data sheet electrical characteristic only. tWCS(min) cycle early write cycle data will remain high impedance duration cycle. Either tRCH tRRH must satisfied read cycle. These parameters referenced /CAS leading edge early write cycles leading edge readwrite cycles. Operation within tRAD(max) limit insures that tRAC(max) met. tRAD(max) specified reference point only. tRAD greater than specified tRAD(max) limit. then access time controlled tAA.
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TIMING DIAGRAMS TIMING
WAVEFORM READ CYCLE /RAS VIHVIL-
HMD2M32M4EAG
tRAS tCRP tRCD tRAD tASR tRAH tASC tCAH
COLUMN ADDRESS
tCSH
tRSH tCAS tRAL
tCRP
VIH/CAS VIL-
VIHA
VILVIHVILVIH-
ADDRESS
tRCS
tRRH tOEA tCAC tCLZ
tRCH
tOFF tOEZ
VIL-
VOHDQ
tRAC
OPEN
VOL-
DATA-OUT
TIMING WAVEFORM WRITE CYCLE (EARLY WRITE)
/RAS VIHVILtCSH tCRP /CAS VIHVILtASR VIHVILtRAH tRAD tASC tCAH
COLUMN ADDRESS
tRAS tCRP
tRCD
tRSH tCAS tRAL
ADDRESS
tCWL tRWL tWCS tWCH
VIH/W VILVIH/OE VILtDS VOHVOLDATA-IN
NOTE Dout Open
URL:www.hbe.co.kr REV. (August.2002)
HANBit Electronics Co.,Ltd.
PACKAGING INFORMATION
72pin -SIMM Design
HMD2M32M4EAG
(Front view)
107.95 3.38 1.57 101.19 3.18 0.51
19.05 10.16 6.35
2.03 1.02 6.35 95.25 6.35 1.27 3.17
0.25
2.54
Gold 1.04±0.10 1.27mm Solder:0.914±0.10mm
1.29±0.08
ORDERING INFORMATION
Part Number
Density
Org.
Package
SPEED
HMD2M32M4EAG-5 HMD2M32M4EAG-6 HMD2M32M4EAG-7
8MByte 8MByte 8MByte
32bit 32bit 32bit
Pin-SIMM Pin-SIMM Pin-SIMM
5.0V 5.0V 5.0V
50ns 60ns 70ns
URL:www.hbe.co.kr REV. (August.2002)
HANBit Electronics Co.,Ltd.

8Mbyte(2Mx32) Mode, Refresh 72Pin SIMM, Design Part HMD2M32M4EAG

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