4Mbyte(1Mx32) Fast Page Mode, Refresh, 72Pin SIMM, Design Part HMD1M32
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HMD1M32M2GL
4Mbyte(1Mx32) Fast Page Mode, Refresh, 72Pin SIMM, Design Part HMD1M32M2GL
HMD1M32M2GL bits Dynamic MODULE which assembled pieces 16bit DRAMs package single sides printed circuit board with decoupling capacitors. HMD1M32M2GL optimized application systems, which required high density large capacity such main memory computers image memory systems, others, which are, requested compact size. HMD1M32M2GL provides common data outputs.
Features ASSIGNMENT
pins Single In-Line Package Fast Page Mode Capability Single +5V± 0.5V power supply Fast Access Time Cycle Time tRAC HMD1M32M2G-5 HMD1M32M2G-6 Power /RAS Only Refresh, /CAS before /RAS Refresh, Hidden Refresh Capability inputs outputs Compatible 1,024 Refresh Cycles/16ms tCAC SYMBOL DQ16 DQ17 DQ18 DQ19 /WEO DQ20 DQ21 SYMBO DQ22 DQ23 NC(A10) /WE2 /RAS /CAS NC(A11) /WE1 SYMBOL DQ24 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 /WE3 DQ29 DQ13 DQ30 DQ14 DQ31 DQ15
DQ31 /RAS /CAS FUNCTION Address Inputs Data Input/Output Address Strobe Column Address Strobe Data Output Enable FUNCTION Read/Write Enable Power (+5V) Ground Connection
URL:www.hbe.co.kr REV.1.0 (August.2002)
HANBit Electronics Co., Ltd.
FUNCTIONAL BLOCK DIAGRAM
/RAS /CAS0 /LCAS /CAS1 /UCAS /RAS
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
HMD1M32M2GL
DQ0-DQ7
A0-A9
DQ8-DQ15
/RAS /RAS /LCAS /CAS2 /UCAS /CAS3
DQ9D DQ11 DQ12 DQ13 DQ14 DQ15
DQ16-DQ23
DQ24-DQ31
A0-A9
A0-A9
0.1uF Capacitor
URL:www.hbe.co.kr REV.1.0 (August.2002)
HANBit Electronics Co., Ltd.
ABSOLUTE MAXIMUM RATINGS*
SYMBOL TSTG VIN/VOUT IOUT PARAMETER Ambient Temperature under Bias Storage Temperature (Plastic) Voltage Relative Power Supply Voltage Short Circuit Output Current Power Dissipation RATING -1.0 -1.0
HMD1M32M2GL
UNIT
*NOTE: Stress greater than above absolute Maximum Ratings?
cause permanent damage device.
RECOMMENDED OPERATING CONDITIONS 70C)
PARAMETER Supply Voltage Ground Input High Voltage Input Voltage *NOTE: voltages referenced SYMBOL -1.0 TYP. Vcc+1 UNIT
OPERATING CHARACTERISTICS
SYMBOL ICC1 (/RAS,/CAS,Address Cycling min) ICC2 ICC3 (/RAS Cycling, /CAS VIH,: min) Fast Page Mode Current ICC4 (/RAS =VIL, /CAS, Address Cycling min) ICC5 ICC6 Standby Current (/RAS,/CAS 0.2V) /CAS before /RAS Refresh Current (tRC min) Self Refresh Current ICCS (/RAS=/UCAS=/LCAS=VIL, /WE=/OE=A0~A9= 0.2V 0.2V, DQ0~DQ31= 0.2V, 0.2V Open) Input Leakage Current II(L) IO(L) (Any Input (0V<=VIN<= 0.5V, Other Pins Under Test Output Leakage Current(DOUT Disabled, 0V<=V OUT<= Vcc) Standby Current (/RAS,/CAS VIH) /RAS Only Refresh Current PARAMETER Output High Level Voltage (IOUT -5mA) Output Level Voltage (IOUT 4.2mA) Operating Current UNIT
URL:www.hbe.co.kr REV.1.0 (August.2002)
HANBit Electronics Co., Ltd.
Note: depends output load condition when device selected. (max) specified output open condition. Address changed once less while /RAS Address changed once less while /CAS
HMD1M32M2GL
CAPACITANCE
TA=25 5V+/- 10%, 1Mhz SYMBOL UNITS NOTE
DESCRIPTION Input Capacitance (A0-A9) Input Capacitance (/WE,/RAS, /CAS0/CAS3,/OE) Input/Output Capacitance (DQ0-31)
CDQ1
Note: Capacitance measured with Boonton Meter effective capacitance measuring method. /CAS disable DOUT.
CHARACTERISTICS
SYMBOL tRWC tRAC tCAC tOFF tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH
70oC 5V±10%, /VIL 2.4/0.8V, /VOL =2.4/0.4V, notes 1,2) UNIT 3,4,10 3,4,5 3,10 NOTE
PARAMETER Random Read Write Cycle Time Read-modify-writer cycle time Access Time from /RAS Access Time from /CAS Access Time from Column Address Output Buffer Turn-off Time Transition Time (Rise Fall) /RAS Precharge Time /RAS Pulse Width /RAS Hold Time /CAS Hold Time /CAS Pulse Width /RAS /CAS Delay Time /RAS Column Address Delay Time /CAS /RAS Precharge Time Address Setup Time Address Hold Time Column Address Setup Time Column Address Hold Time Column Address /RAS Lead Time Read Command Setup Time Read Command Hold Time /CAS
URL:www.hbe.co.kr REV.1.0 (August.2002)
HANBit Electronics Co., Ltd.
tRRH tWCH tRWL tCWL tREF twcs tCWD tRWD tAWD tCPWD tCSR (/CAS-before-/RAS Refresh Cycle) /CAS Hold Time tCHR (/CAS-before-/RAS Refresh Cycle) tRPC tCPA tRASP tRHCP Precharge tOEA tOED tOEZ tOEH tRASS tPRS Access Time data delay Output buffer turn delay time from command hold time /RAS Pulse Width(CBR self refresh) /RAS Precharge Time(CBR self refresh) /RAS Precharge /CAS Hold Time Access Time from /CAS Precharge Fast Page Mode Cycle Time Fast Page Mode /RAS Precharge Time Fast Page Mode /CAS Pulse Time /RAS Hold Time time from /CAS 200K Read Command Hold Time /RAS Write Command Hold Time Write Command Pulse Width Write Command /RAS Lead Time Write Command /CAS Lead Time Data-in Setup Time Data-in Hold Time Refresh Period (1024 Cycle) Write Command Setup Time /CAS delay time /RAS delay time Column Address delay time /CAS precharge delay time /CAS Setup Time
HMD1M32M2GL
7,13
200K
/CAS Hold Time(CBR self refresh) tCHS Note: initial pause 200us required after power-up followed /RAS-only refresh /CAS-before-/RAS refresh cycles before proper device operation achieved. Input voltage levels VIL. VIH(min) VIL(max) reference levels measuring timing input signals. Also, transition times measured between assumed inputs. Measured with load circuit equivalent 2TTL loads 100pF. Operation with tRCD (max) limit insures that tRAC (max) met, tRCD (max) specified reference point only, tRCD greater than specified tRCD(max) limit, then access time controlled exclusively tCAC Assumes that tRCD tRCD (max). This parameter defines time which output achieves open circuit condition referenced TWCS, TRWD, TCWD, TCPWD restrictive operating parameter. They included data sheet electrical characteristics only. twcs twcs (min), cycle early write cycle data will remain open circuit (high impedance) throughout
URL:www.hbe.co.kr REV.1.0 (August.2002)
HANBit Electronics Co., Ltd.
HMD1M32M2GL
entire cycle. tCWD tCWD (min), tRWD tRWD (min), TCPWD>= TCPWD(min), then cycle read-modify-write cycle data output will contain data read from selected address. neither above conditions satisfied, condition data indeterminate. Either tRCH tRRH must satisfied read cycles. These parameters referenced /CAS falling edge early write cycles falling edge controlled write cycle read-modify-write cycles. Operation with tRAD (max) limit insures that tRAC (max) met, tRAD (max) specified reference point only, tRAD greater than specified tRAD (max) limit, then access time controlled exclusively tAA. tASC, tCAH referenced earlier /CAS falling edge. specified from later /CAS rising edge previous cycle earlier /CAS falling edge next cycle. tCWD referenced later /CAS falling edge word read-modify-write cycle. tCWL specified from falling edge earlier /CAS rising edge tCSR referenced earlier /CAS falling edge before /RAS transition low. tCHR referenced later /CAS rising edge after /RAS transition low.
PACKAGING INFORMATION
0.25
2.54
1.27±0.08 1.27
URL:www.hbe.co.kr REV.1.0 (August.2002)
HANBit Electronics Co., Ltd.
ORDERING INFORMATION
Part Number Density Org. Package Component Number
HMD1M32M2GL
MODE
SPEED
HMD1M32M2GL-5 HMD1M32M2GL-6
4MByte 4MByte
Pin-SIMM Pin-SIMM
50ns 60ns
URL:www.hbe.co.kr REV.1.0 (August.2002)
HANBit Electronics Co., Ltd.
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