4Mbyte(1Mx32) Fast Page Mode, Refresh, 72Pin SIMM, Design Part HMD1M32

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4Mbyte(1Mx32) Fast Page Mode, Refresh, 72Pin SIMM, Design Part HMD1M32

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HMD1M32M2G
4Mbyte(1Mx32) Fast Page Mode, Refresh, 72Pin SIMM, Design Part HMD1M32M2G
HMD1M32M2G bits Dynamic MODULE which assembled pieces 16bit DRAMs package single sides printed circuit board with decoupling capacitors. HMD1M32M2G optimized application systems, which required high density large capacity such main memory computers image memory systems, others, which are, requested compact size. HMD1M32M2G provides common data outputs.
ASSIGNMENT Features
pins Single In-Line Package Fast Page Mode Capability Single +5V± 0.5V power supply Fast Access Time Cycle Time tRAC HMD1M32M2G-6 HMD1M32M2G-7 Power Active: 1,870/1,650/1,430 mW(MAX) Standby: 11mW(CMOS level MAX) /RAS Only Refresh, /CAS before /RAS Refresh, Hidden Refresh Capability inputs outputs Compatible 1,024 Refresh Cycles/16ms tCAC SYMBOL DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 SYMBOL DQ22 DQ23 /RAS2 /CAS0 /CAS2 /CAS3 /CAS1 /RAS0 SYMBOL DQ24 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 DQ29 DQ13 DQ30 DQ14 DQ31 DQ15
PRESENCE DETECT PINS (Optional)
60NS 70NS
DQ31 /RAS0, /RAS2 /CAS0 /CAS3
URL:www.hbe.co.kr REV.1.0 (August.2002)
FUNCTION Address Inputs Data Input/Output Address Strobe Column Address Strobe Read/Write Enable
FUNCTION Presence Detect Power (+5V) Ground Connection HANBiT Electronics Co.,
FUNCTIONAL BLOCK DIAGRAM
HMD1M32M2G
/RAS0
/RAS
/CAS0
/LCAS
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQ0-DQ7
/CAS1
/UCAS
DQ8-DQ15
/RAS2
/RAS
/CAS2
/LCAS
DQ9D DQ11 DQ12 DQ13 DQ14 DQ15
DQ16-DQ23
/CAS3
/UCAS
DQ24-DQ31
A0-A9
0.1uF Capacitor
ABSOLUTE MAXIMUM RATINGS*
SYMBOL TSTG VIN/VOUT IOUT PARAMETER Ambient Temperature under Bias Storage Temperature (Plastic) Voltage Relative Power Supply Voltage Short Circuit Output Current Power Dissipation RATING -1.0 -1.0 UNIT
*NOTE: Stress greater than above absolute Maximum Ratings?
cause permanent damage device.
URL:www.hbe.co.kr REV.1.0 (August.2002)
HANBiT Electronics Co.,
RECOMMENDED OPERATING CONDITIONS 70C)
PARAMETER Supply Voltage Ground Input High Voltage Input Voltage *NOTE: voltages referenced SYMBOL -1.0 TYP.
HMD1M32M2G
Vcc+1
UNIT
OPERATING CHARACTERISTICS
SYMBOL Output Level Output High Level Voltage (IOUT -5mA) Output Level Output Level Voltage (IOUT 4.2mA) 60ns Operating Current ICC1 Average Power Supply Operating Current (/RAS,/CAS,Address Cycling min) Standby Current (TTL) ICC2 Power Supply Standby Current (/RAS,/CAS VIH) /RAS Only Refresh Current 60ns ICC3 Average Power Supply Current /RAS Only Mode (/RAS Cycling, /CAS VIH,: min) Fast Page Mode Current Average Power Supply Current Fast Page Mode ICC4 (/RAS VIL, /CAS, Address Cycling min) 70ns 60ns 70ns 70ns PARAMETER UNIT NOTE
Standby Current (CMOS) ICC5 Power Supply Standby Current (/RAS,/CAS 0.2V) /CAS before /RAS Refresh Current ICC6 (tRC min) 70ns 60ns
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Standby Current /RAS ICC7 /CAS DOUT Enable Input Leakage Current II(L) Input (0V<=VIN<=7V) Other Pins Under Test Output Leakage Current IO(L) (DOUT Disabled, 0V<=VOUT<=7V)
HMD1M32M2G
Note: 1.Icc depends output load condition when device selected. (max) specified output open condition. Address changed once less while /RAS VIL. Address changed once less while /CAS
CAPACITANCE
TA=25 5V+/- 10%, 1Mhz
DESCRIPTION Input Capacitance (A0-A9) Input Capacitance (/WE) Input Capacitance (/RAS0,/RAS2) Input Capacitance (/CAS0-/CAS3) Input/Output Capacitance (DQ0-31)
SYMBOL CDQ1
UNITS
NOTE
Note: Capacitance measured with Boonton Meter effective capacitance measuring method. /CAS disable DOUT.
CHARACTERISTICS
70oC 5V±10%, notes 1,15.)
GMM731000CNS/SG writes data only early write cycle (twcs>=twcs(min)) Delayed write cycle available because common. READ, WRITE REFRESH CYCLE (Common Parameters) SYMBOL tRAS tCAS tASR tRAH tASC PARAMETER Random Read Write Cycle Time /RAS Precharge Time /RAS Pulse Width /CAS Pulse Width Address Setup Time Address Hold Time Column Address Setup Time UNIT NOTE
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HANBiT Electronics Co.,
tCAH tRCD tRAD tRSH tCSH tCRP tREF Column Address Hold Time /RAS /CAS Delay Time /RAS Column Address Delay Time /RAS Hold Time /CAS Hold Time /CAS /RAS Precharge Time Transition Time (Rise Fall) Refresh Period (1024 Cycle)
HMD1M32M2G
READ CYCLE SYMBOL tRAC tCAC tRCS tRCH tRRH tRAL tOFF PARAMETER Access Time from /RAS Access Time from /CAS Access Time from Column Address Read Command Setup Time Read Command Hold Time /CAS Read Command Hold Time /RAS Column Address /RAS Lead Time Output Buffer Turn-off Time 3,5,14 UNIT NOTE
WRITE CYCLE SYMBOL twcs tWCH tRWL tCWL PARAMETER Write Command Setup Time Write Command Hold Time Write Command Pulse Width Write Command /RAS Lead Time Write Command /CAS Lead Time Data-in Setup Time Data-in Hold Time UNIT NOTE
REFRESH CYCLE SYMBOL PARAMETER /CAS Setup Time (/CAS-before-/RAS Refresh Cycle) /CAS Hold Time (/CAS-before-/RAS Refresh Cycle) UNIT NOTE
tCRS tCHR
URL:www.hbe.co.kr REV.1.0 (August.2002)
HANBiT Electronics Co.,
tRPC /RAS Precharge /CAS Hold Time
HMD1M32M2G
FAST PAGE MODE CYCLE SYMBOL tRASP tACP PARAMETER Fast Page Mode Cycle Time Fast Page Mode /RAS Precharge Time Fast Page Mode /CAS Pulse Time Access Time from /CAS Precharge 100K 100K UNIT NOTE
/RAS Hold Time from /CAS Precharge tRHCP Note: measurements assume 5ns.
Assumes that tRCD<=tRCD(max) tRCD<=tRCD(max). tRCD tRCD greater than maximum recommended value shown this table, tRCD exceeds value shown. Measured with load circuit equivalent 2TTL loads 100PpF. Assumes that tRCD tRCD (max) tRCD<= tRCD (max). 5.Assumes that tRCD tRCD (max) tRCD>= tRCD (max). 6.Either tRCH tRRH must satisfied read cycles. tOFF(max) defines time which outputs achieve open circuit condition referenced output voltage levels. VIH(min) VIL(max) reference levels measuring timing input signals. Also, transition times measured between VIL. Operation with tRCD (max) limit insures that tRAC (max) met, tRCD (max) specified reference point only, tRCD greater than specified tRCD (max) limit, then access time controlled exclusively tCAC Operation with tRAD (max) limit insures that tRAC (max) met, tRAD (max) specified reference point only, tRAD greater than specified tRAD (max) limit, then access time controlled exclusively tAA. TWCS restrictive operating parameter. included data sheet electrical characteristics only. twcs twcs (min), cycle early write cycle data will remain open circuit(high impedance) throughout entire cycle. These parameters referenced /CAS leading edge early write cycles. tRASP defines /RAS pulse width Fast Page Mode cycles. Access time determined longer tCAC tACP initial pause 200us required after power followed minimum eight initialization cycle (eny combination cycles containing /RAS clock such /RAS only refresh). internal refresh count used, mnimum eight /CAS before /RAS refresh cycle required.
URL:www.hbe.co.kr REV.1.0 (August.2002)
HANBiT Electronics Co.,
HMD1M32M2G
PACKAGING INFORMATION
107.95 101.19 3.38 R1.57 3.18
19.05 6.35 2.03 6.35 6.35 R1.57±1.0 95.25
10.16
5.08
0.25
2.54
1.27 1.27±0.08
ORDERING INFORMATION
Part Number Density Org. Package Component Number MODE SPEED
HMD1M32M2G-6
4MByte
Pin-SIMM
60ns
URL:www.hbe.co.kr REV.1.0 (August.2002)
HANBiT Electronics Co.,
HMD1M32M2G-7 4MByte Pin-SIMM
HMD1M32M2G
70ns
URL:www.hbe.co.kr REV.1.0 (August.2002)
HANBiT Electronics Co.,

4Mbyte(1Mx32) Fast Page Mode, Refresh, 72Pin SIMM, Design Part HMD1M32

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