1Mbit(1Mx1bit) Fast Page Mode, Refresh, 20Pin ZIP, Design Part HMD1M1Z

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1Mbit(1Mx1bit) Fast Page Mode, Refresh, 20Pin ZIP, Design Part HMD1M1Z

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HMD1M1Z1
1Mbit(1Mx1bit) Fast Page Mode, Refresh, 20Pin ZIP, Design Part HMD1M1Z1
HMD1M1Z1 bits Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access memory cells within same row. Power supply voltage (+5V access time (-5, -6), power consumption(Normal power), package type (ZIP) optional features this Module. HMD1M1Z1 have CAS-before-RAS refresh, RAS-only refresh Hidden refresh capabilities. HMD1M1Z1 optimized application systems, which required high density large capacity such main memory main frames mini computers, personal computer high performance microprocessor systems. HMD1M1Z1 provides common data outputs.
Features
Fast Page Mode operation CAS-before-RAS refresh capability RAS-only Hidden refresh capability Fast parallel test mode capability TTL(5V) compatible inputs outputs Early write output enable controlled write Available 20pin packages Single +5V± power supply 1,024 Refresh Cycles/16ms Performance Range Speed HMD1M1Z1-5 HMD1M1Z1-6 tRAC tCAC
ASSIGNMENT
SYMBOL /CAS DOUT /RAS A9NC
/RAS /CAS FUNCTION Address Inputs Data Input/Output Address Strobe Column Address Strobe FUNCTION Read/Write Enable Power (+5V) Ground Connection
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ABSOLUTE MAXIMUM RATINGS*
SYMBOL TSTG VIN/VOUT IOUT PARAMETER Ambient Temperature under Bias Storage Temperature (Plastic) Voltage Relative Power Supply Voltage Short Circuit Output Current Power Dissipation RATING -1.0 -1.0
HMD1M1Z1
UNIT
*NOTE: Stress greater than above absolute Maximum Ratings?
cause permanent damage device.
RECOMMENDED OPERATING CONDITIONS 70C)
PARAMETER Supply Voltage Ground Input High Voltage Input Voltage *NOTE: voltages referenced SYMBOL -1.0 TYP. Vcc+1 UNIT
OPERATING CHARACTERISTICS
SYMBOL ICC1 ICC2 ICC3 PARAMETER Output High Level Voltage (IOUT -5mA) Output Level Voltage (IOUT 4.2mA) Operating Current (/RAS,/CAS,Address Cycling min) Standby Current (/RAS,/CAS VIH) /RAS Only Refresh Current (/RAS Cycling, /CAS VIH,: min) Fast Page Mode Current ICC4 ICC5 ICC6 (/RAS =VIL, /CAS, Address Cycling min) Standby Current (/RAS,/CAS 0.2V) /CAS before /RAS Refresh Current (tRC min) Self Refresh Current ICCS (/RAS=/UCAS=/LCAS=VIL, /WE=/OE=A0~A9= 0.2V 0.2V, DQ0~DQ31= 0.2V, 0.2V Open) Input Leakage Current II(L) (Any Input (0V<=VIN<= 0.5V, Other Pins Under Test IO(L) Output Leakage Current(DOUT Disabled, 0V<=V OUT<= Vcc) UNIT
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HMD1M1Z1
Note: depends output load condition when device selected. (max) specified output open condition. Address changed once less while /RAS Address changed once less while /CAS
CAPACITANCE
TA=25 5V+/- 10%, 1Mhz SYMBOL UNITS NOTE
DESCRIPTION Input Capacitance (A0-A9) Input Capacitance (/WE,/RAS, /CAS0/CAS3,/OE) Input/Output Capacitance (DQ0-31)
CDQ1
Note: Capacitance measured with Boonton Meter effective capacitance measuring method. /CAS disable DOUT.
CHARACTERISTICS
SYMBOL tRWC tRAC tCAC tOFF tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS
70oC 5V±10%, /VIL 2.4/0.8V, /VOL =2.4/0.4V, notes 1,2) UNIT 3,4,10 3,4,5 3,10 NOTE
PARAMETER Random Read Write Cycle Time Read-modify-writer cycle time Access Time from /RAS Access Time from /CAS Access Time from Column Address Output Buffer Turn-off Time Transition Time (Rise Fall) /RAS Precharge Time /RAS Pulse Width /RAS Hold Time /CAS Hold Time /CAS Pulse Width /RAS /CAS Delay Time /RAS Column Address Delay Time /CAS /RAS Precharge Time Address Setup Time Address Hold Time Column Address Setup Time Column Address Hold Time Column Address /RAS Lead Time Read Command Setup Time
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tRCH tRRH tWCH tRWL tCWL tREF twcs tCWD tRWD tAWD tCPWD tCSR Read Command Hold Time /CAS Read Command Hold Time /RAS Write Command Hold Time Write Command Pulse Width Write Command /RAS Lead Time Write Command /CAS Lead Time Data-in Setup Time Data-in Hold Time Refresh Period (1024 Cycle) Write Command Setup Time /CAS delay time /RAS delay time Column Address delay time /CAS precharge delay time /CAS Setup Time (/CAS-before-/RAS Refresh Cycle) /CAS Hold Time tCHR tRPC tCPA tRASP tRHCP tRASS tPRS tCHS Note: cycles before proper device operation achieved. (/CAS-before-/RAS Refresh Cycle) /RAS Precharge /CAS Hold Time Access Time from /CAS Precharge Fast Page Mode Cycle Time Fast Page Mode /RAS Precharge Time Fast Page Mode /CAS Pulse Time /RAS Hold Time time from /CAS Precharge /RAS Pulse Width(CBR self refresh) /RAS Precharge Time(CBR self refresh) /CAS Hold Time(CBR self refresh) 200K 200K
HMD1M1Z1
7,13
initial pause 200us required after power-up followed /RAS-only refresh /CAS-before-/RAS refresh
Input voltage levels VIL. VIH(min) VIL(max) reference levels measuring timing input signals. Also, transition times measured between assumed inputs. Measured with load circuit equivalent 2TTL loads 100pF. Operation with tRCD (max) limit insures that tRAC (max) met, tRCD (max) specified reference point only, tRCD greater than specified tRCD(max) limit, then access time controlled exclusively tCAC Assumes that tRCD tRCD (max). This parameter defines time which output achieves open circuit condition referenced
HANBit Electronics Co.,Ltd.
HMD1M1Z1
TWCS, TRWD, TCWD, TCPWD restrictive operating parameter. They included data sheet electrical characteristics only. twcs twcs (min), cycle early write cycle data will remain open circuit (high impedance) throughout entire cycle. tCWD tCWD (min), tRWD tRWD (min), TCPWD>= TCPWD(min), then cycle read-modify-write cycle data output will contain data read from selected address. neither above conditions satisfied, condition data indeterminate. Either tRCH tRRH must satisfied read cycles. These parameters referenced /CAS falling edge early write cycles falling edge controlled write cycle read-modify-write cycles. Operation with tRAD (max) limit insures that tRAC (max) met, tRAD (max) specified reference point only, tRAD greater than specified tRAD (max) limit, then access time controlled exclusively tAA. tASC, tCAH referenced earlier /CAS falling edge. specified from later /CAS rising edge previous cycle earlier /CAS falling edge next cycle. tCWD referenced later /CAS falling edge word read-modify-write cycle. tCWL specified from falling edge earlier /CAS rising edge tCSR referenced earlier /CAS falling edge before /RAS transition low. tCHR referenced later /CAS rising edge after /RAS transition low.
PACKAGING INFORMATION
HANBit Electronics Co.,Ltd.
HMD1M1Z1
1.94 0.20
1.27 0.20
1.94 0.20
1.8±0.30
2.54
ORDERING INFORMATION
Part Number Density Org. Package Component Number MODE SPEED
HMD1M1Z1-5 HMD1M1Z1-6
1Mbit 1Mbit
1Bit 1Bit
Pin-ZIP Pin-ZIP
50ns 60ns
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1Mbit(1Mx1bit) Fast Page Mode, Refresh, 20Pin ZIP, Design Part HMD1M1Z

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