64Mbyte (16Mx36) EDO/with Parity Mode Ref. 72pin-SIMM Design Part HMD1
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HMD16M36M12EG
64Mbyte (16Mx36) EDO/with Parity Mode Ref. 72pin-SIMM Design Part HMD16M36M12EG
HMD16M36M12EG 36bit dynamic high-density memory module. module consists eight CMOS 4bit DRAMs 32-pin TSOP packages four CMOS 16Mx1bit DRAMs TSOP packages mounted 72-pin glass-epoxy substrate. 0.22uF decoupling capacitor mounted printed circuit board each DRAM components. module Single In-line Memory Module with edge connections intended mounting 72-pin edge connector sockets. module components powered from single power supply inputs outputs TTL-compatible.
FEATURES
wPart Identification HMD16M36M12EG Cycles/64ms Ref, Gold Access times 60ns High-density 64MByte design Single ±0.5V power supply JEDEC standard Pdpin pinout compatible inputs outputs w/CAS-before-/RAS Hidden Refresh capability w/RAS-only refresh capability wEDO Mode Operation SYMBOL DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
ASSIGNMENT
SYMBOL DQ24 DQ25 /RAS2 DQ26 DQ17 DQ35 /CAS0 /CAS2 /CAS3 /CAS1 /RAS0 SYMBOL DQ27 DQ10 DQ28 DQ11 DQ29 DQ12 DQ30 DQ13 DQ31 DQ32 DQ14 DQ33 DQ15 DQ34 DQ16
OPTIONS
Timing 50ns access 60ns access Packages 72-pin SIMM
MARKING
PERFORMANCE RANGE
Speed tRAC 50ns 60ns tCAC 13ns 15ns 90ns 110ns
PRESENCE DETECT PINS (Optional)
50ns 60ns
72PIN SIMM
VIEW
URL:www.hbe.co.kr REV.1.0(August.2002)
HANBit Electronics Co.,Ltd.
FUNCTIONAL BLOCK DIAGRAM
HMD16M36M12EG
DQ0-DQ35
/CAS0 /RAS0
DQ0-DQ3
A0-A11 A0-A11
/CAS2 /RAS2
DQ18-DQ21
A0-A11
DQ4-DQ7
A0-A11 A0-A11
DQ22-DQ25
A0-A11
A0-A11 A0-A11
DQ26 A0-A11
/CAS1
DQ9-DQ12
A0-A11 A0-A11
/CAS3
DQ27-DQ30
A0-A11
DQ13-DQ16
A0-A11 A0-A11
DQ17
DQ31-DQ34
A0-A11
A0-A11 A0-A11
DQ35 A0-A11
A0-A11
URL:www.hbe.co.kr REV.1.0(August.2002)
HANBit Electronics Co.,Ltd.
ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage Relative Voltage Supply Relative Power Dissipation Storage Temperature SYMBOL ,OUT TSTG
HMD16M36M12EG
RATING 7.0V 7.0V -55oC 125oC
Short Circuit Output Current 50mA Permanent device damage occur Absolute Maximum Ratings" exceeded. Functional operation should restricted conditions detailed operational sections this data sheet. Exposure absolute maximum rating conditions extended periods affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Voltage reference VSS, TA=0 PARAMETER Supply Voltage Ground Input High Voltage Input Voltage SYMBOL -1.0 TYP. UNIT
OPERATING CHARACTERISTICS
SYMBOL ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 Il(L) IO(L) ICC1 Operating Current (/RAS /CAS Address cycling RC=min.)
URL:www.hbe.co.kr REV.1.0(August.2002) HANBit Electronics Co.,Ltd.
SPEED
1080 1080 1080
UNITS
Don't care
Don't care
Don't care
ICC2 Standby Current /RAS=/CAS=VIH ICC3 /RAS Only Refresh Current /CAS=V /RAS, Address cycling @tRC=min ICC4 Fast Page Mode Current (/RAS=VIL, /CAS, Address cycling @tPC=min ICC5 Standby Current (/RAS=/CAS=Vcc-0.2V ICC6 /CAS-Before-/RAS Refresh Current (/RAS /CAS cycling RC=min
HMD16M36M12EG
Input Leakage Current (Any input 6.5V, other pins under test Output Leakage Current (Data disabled, VOUT 5.5V Output High Voltage Level (IOH= -5mA Output Voltage Level (IOL 4.2mA NOTE: ICC1, ICC3, ICC4 ICC6 dependent output loading cycle rates. Specified values obtained with output open. specified average current. ICC1 ICC3, address changed maximum once while /RAS=VIL. ICC4, address changed maximum once within page mode cycle.
CAPACITANCE
TA=25 SYMBOL CIN1 CIN3 CIN4 CDQ1 UNITS
DESCRIPTION Input Capacitance (A0-A11) Input Capacitance (/W) Input Capacitance (/RAS0) Input Capacitance (/CAS0-/CAS3) Input/Output Capacitance (DQ0-31)
CHARACTERISTICS
PARAMETER Random read write cycle time Access time from /RAS Access time from /CAS Access time from column address /CAS output Low-Z Output buffer turn-off delay Transition time (rise fall) /RAS precharge time /RAS pulse width /RAS hold time /CAS hold time /CAS pulse width /RAS /CAS delay time
70oC 5V±10%, notes 1,2.) SYMBOL tRAC tCAC tCLZ tOFF tRAS tRSH tCSH tCAS tRCD UNIT
URL:www.hbe.co.kr REV.1.0(August.2002)
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/RAS column address delay time /CAS /RAS precharge time address set-up time address hold time Column address set-up time Column address hold time Column address hold referenced /RAS Column Address /RAS lead time Read command set-up time Read command hold referenced /CAS Read command hold referenced /RAS Write command hold time Write command hold referenced /RAS Write command pulse width Write command /RAS lead time Write command /CAS lead time Data-in set-up time Data-in hold time Data-in hold referenced /RAS Refresh period Write command set-up time /CAS setup time (C-B-R refresh) /CAS hold time (C-B-R refresh) /RAS precharge /CAS hold time Access time from /CAS precharge Fast page mode cycle time /CAS precharge time (Fast page) /RAS pulse width (Fast page /RAS precharge time(C-B-R refresh) /RAS hold time (C-B-R refresh) /CAS precharge(C-B-R counter test) tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWCR tRWL tCWL tDHR tREF tWCS tCSR tCHR tRPC tCPA tRASP tWRP tWRH tCPT 200K
HMD16M36M12EG
200K
NOTES
1.An initial pause 200µs required after power-up followed /RAS-only /CAS-before-/RAS refresh cycles
before proper device operation achieved.
2.VIH (min) (max) reference levels measuring timing input signals. Transition times measured between
VIH(min) VIL(max) assumed inputs.
3.Measured with load equivalent 2TTL loads 100pF 4.Operation within tRCD(max) limit insures that tRAC(max) met. tRCD(max) specified reference point only. tRCD
URL:www.hbe.co.kr REV.1.0(August.2002) HANBit Electronics Co.,Ltd.
HMD16M36M12EG
greater than specified tRCD(max) limit, then access time controlled exclusively CAC.
5.Assumes that tRCD tRCD(max)
tAR, tWCR, tDHR referenced tRAD(max) 7.This parameter defines time which output achieves open circuit condition referenced VOL. tWCS, tRWD, tCWD tAWD restrictive operating parameter. They included data sheet electrical characteristic only. tWCS(min) cycle early write cycle data will remain high impedance duration cycle. Either tRCH tRRH must satisfied read cycle. These parameters referenced /CAS leading edge early write cycles leading edge readwrite cycles. Operation within tRAD(max) limit insures that tRAC(max) met. tRAD(max) specified reference point only. tRAD greater than specified tRAD(max) limit. then access time controlled tAA.
URL:www.hbe.co.kr REV.1.0(August.2002)
HANBit Electronics Co.,Ltd.
PACKAGING INFORMATION
SIMM Design Unit
HMD16M36M12EG
107.95 0.20
3.38± 3.38±
27.0 ±0.2 6.35±
10.16±
2.03± 1.0± 6.35± 6.35± 95.25± 1.27± 3.34±
Front View
0.25
2.54
1.27 Gold 1.04±0.10 1.27 Solder:0.914±0.10
ORDERING INFORMATION
Part Number Density Org. Package Ref. MODE SPEED
HMD16M36M12EG-5 HMD16M36M12EG-6
64MByte 64MByte
Pin-SIMM-Gold Pin-SIMM-Gold
EDO/ Parity EDO/ Parity
50ns 60ns
URL:www.hbe.co.kr REV.1.0(August.2002)
HANBit Electronics Co.,Ltd.
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