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64Mbyte(16Mx32) 72-pin Mode Ref. SIMM Design Part HMD16M32M8G HMD


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HMD16M32M8G
64Mbyte(16Mx32) 72-pin Mode Ref. SIMM Design Part HMD16M32M8G
HMD16M32M8G 16Mbit dynamic high-density memory module. module consists eight CMOS 4bit DRAMs 32-pin TSOPII packages mounted 72-pin, double-sided, FR-4-printed circuit board. 0.1uF decoupling capacitor mounted printed circuit board each DRAM components. module Single In-line Memory Module with edge connections intended mounting 72-pin edge connector sockets. module components powered from single power supply inputs outputs TTL-compatible.
ASSIGNMENT FEATURES
wHMD16M32M8G: Cycles/64ms Refresh Gold Access times 60ns High-density 64MByte design Single ±0.5V power supply JEDEC standard pinout FP(Fast Page) mode operation compatible inputs outputs FR4-PCB design
SYMBOL SYMBOL SYMBOL SYMBOL
90ns 110ns
DQ16 DQ17 DQ18 DQ19
DQ20 DQ21 DQ22 DQ23 /RAS2
/CAS0 /CAS2 /CAS3 /CAS1 /RAS0 DQ24 DQ25 DQ10 DQ26
DQ11 DQ27 DQ12 DQ28 DQ29 DQ13 DQ30 DQ14 DQ31 DQ15
OPTIONS
Timing 50ns access 60ns access Packages 72-pin SIMM
MARKING
PERFORMANCE RANGE
SPEED tRAC 50ns 60ns tCAC 13ns 15ns
wPART IDENTIFICATION
PRESENCE DETECT PINS 50ns 60ns
URL: www.hbe.co.kr REV. (August. 2002)
HANBit Electronics Co.,Ltd.
FUNCTIONAL BLOCK DIAGRAM
HMD16M32M8G
/CAS0 /RAS0
A0-A11
DQ0-DQ3
A0-A11
DQ4-DQ7
/CAS1
A0-A11
DQ8-DQ11
A0-A11
DQ12-DQ15
/CAS2
/RAS2
A0-A11
DQ16-DQ19
A0-A11
DQ20-DQ23
/CAS3
A0-A11
DQ24-DQ27
A0-A11
DQ28-DQ31
A0-A11
0.1uF 0.22uF Capacitor each DRAM
DRAMs
URL: www.hbe.co.kr REV. (August. 2002)
HANBit Electronics Co.,Ltd.
ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage Relative Voltage Supply Relative Power Dissipation Storage Temperature SYMBOL ,OUT TSTG
HMD16M32M8G
RATING 7.0V 7.0V -55oC 150oC
Short Circuit Output Current 50mA Permanent device damage occur Absolute Maximum Ratings" exceeded. Functional operation should restricted conditions detailed operational sections this data sheet. Exposure absolute maximum rating conditions extended periods affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Voltage reference VSS, TA=0 PARAMETER Supply Voltage Ground Input High Voltage Input Voltage SYMBOL -1.0 TYP. Vcc+1 UNIT
OPERATING CHARACTERISTICS
SYMBOL ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 Il(L) IO(L) SPEED UNITS
URL: www.hbe.co.kr REV. (August. 2002)
HANBit Electronics Co.,Ltd.
ICC1 Operating Current (/RAS /CAS Address cycling RC=min.) ICC2 Standby Current /RAS=/CAS=VIH ICC3 /RAS Only Refresh Current /CAS=V /RAS, Address cycling @tRC=min ICC4 Fast Page Mode Current (/RAS=VIL, /CAS, Address cycling @tPC=min ICC5 Standby Current (/RAS=/CAS=Vcc-0.2V ICC6 /CAS-Before-/RAS Refresh Current (/RAS /CAS cycling RC=min Input Leakage Current (Any input 6.5V, other pins under test Output Leakage Current (Data disabled, VOUT 5.5V Output High Voltage Level (IOH= -5mA Output Voltage Level (IOL 4.2mA
HMD16M32M8G
NOTE: ICC1, ICC3, ICC4 ICC6 dependent output loading cycle rates. Specified values obtained with output open. specified average current. ICC1 ICC3, address changed maximum once while /RAS=VIL. ICC4, address changed maximum once within page mode cycle.
CAPACITANCE
TA=25 SYMBOL CIN1 CIN3 CIN4 CDQ1
DESCRIPTION Input Capacitance (A0-A11) Input Capacitance (/W) Input Capacitance (/RAS0) Input Capacitance (/CAS0-/CAS3) Input/Output Capacitance (DQ0-31)
UNITS
CHARACTERISTICS
70oC 5V±10%, notes 1,2.) UNIT
PARAMETER Random read write cycle time Access time from /RAS Access time from /CAS Access time from column address /CAS output Low-Z Output buffer turn-off delay Transition time (rise fall) /RAS precharge time /RAS pulse width /RAS hold time /CAS hold time /CAS pulse width /RAS /CAS delay time /RAS column address delay time
URL: www.hbe.co.kr REV. (August. 2002)
SYMBOL tRAC tCAC tCLZ tOFF tRAS tRSH tCSH tCAS tRCD tRAD
HANBit Electronics Co.,Ltd.
/CAS /RAS precharge time address set-up time address hold time Column address set-up time Column address hold time Column address hold referenced /RAS Column Address /RAS lead time Read command set-up time Read command hold referenced /CAS Read command hold referenced /RAS Write command hold time Write command hold referenced /RAS Write command pulse width Write command /RAS lead time Write command /CAS lead time Data-in set-up time Data-in hold time Data-in hold referenced /RAS Refresh period Write command set-up time /CAS setup time (C-B-R refresh) /CAS hold time (C-B-R refresh) /RAS precharge /CAS hold time Access time from /CAS precharge Fast page mode cycle time /CAS precharge time (Fast page) /RAS pulse width (Fast page /RAS precharge time (C-B-R refresh) /RAS hold time (C-B-R refresh) /CAS precharge(C-B-R counter test) NOTES tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWCR tRWL tCWL tDHR tREF tWCS tCSR tCHR tRPC tCPA tRASP tWRP tWRH tCPT 100K
HMD16M32M8G
100K
1.An initial pause 200µs required after power-up followed /RAS-only /CAS-before-/RAS refresh cycles
before proper device operation achieved.
2.VIH (min) (max) reference levels measuring timing input signals. Transition times measured between
VIH(min) VIL(max) assumed inputs.
3.Measured with load equivalent 1TTL loads 100pF 4.Operation within tRCD(max) limit insures that tRAC(max) met. tRCD(max) specified reference point only. tRCD
greater than specified tRCD(max) limit, then access time controlled exclusively CAC.
5.Assumes that tRCD tRCD(max)
URL: www.hbe.co.kr REV. (August. 2002)
HANBit Electronics Co.,Ltd.
tAR, tWCR, tDHR referenced tRAD(max)
HMD16M32M8G
7.This parameter defines time which output achieves open circuit condition referenced VOL. tWCS, tRWD, tCWD tAWD restrictive operating parameter. They included data sheet electrical characteristic only. tWCS(min) cycle early write cycle data will remain high impedance duration cycle. Either tRCH tRRH must satisfied read cycle. These parameters referenced /CAS leading edge early write cycles leading edge readwrite cycles. Operation within tRAD(max) limit insures that tRAC(max) met. tRAD(max) specified reference point only. tRAD greater than specified tRAD(max) limit. then access time controlled tAA.
Timing Diagrams
TIMING WAVEFORM READ CYCLE
URL: www.hbe.co.kr REV. (August. 2002)
HANBit Electronics Co.,Ltd.
TIMING WAVEFORM WRITE CYCLE (EARLY WRITE)
HMD16M32M8G
URL: www.hbe.co.kr REV. (August. 2002)
HANBit Electronics Co.,Ltd.
WRITE CYCLE (/OE CONTROLLED WRITE) Note: Dout=open
HMD16M32M8G
URL: www.hbe.co.kr REV. (August. 2002)
HANBit Electronics Co.,Ltd.
/CAS-BEFORE-/RAS REFRESH COUNTER TEST CYCLE
HMD16M32M8G
URL: www.hbe.co.kr REV. (August. 2002)
HANBit Electronics Co.,Ltd.
PACKAGING INFORMATION
SIMM Design
107.95 3.38 1.57
HMD16M32M8G
101.19
3.18mmDIA 0.51mm
20.00 6.35
2.03 10.16
6.35
1.02
6.35 95.25
1.27
3.34
0.25mm
2.54
Gold 1.04±0.10
1.27±10%
1.27
Solder:0.914±0.10mm
ORDERING INFORMATION
Part Number Density Org. Package Component Number MODE SPEED
HMD16M32M8G-5 HMD16M32M8G-6
64Byte 64Byte
Pin-SIMM Pin-SIMM
50ns 60ns
URL: www.hbe.co.kr REV. (August. 2002)
HANBit Electronics Co.,Ltd.

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