User-configurable Pipeline Flow Through mode Turn Around) functionalit

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User-configurable Pipeline Flow Through mode Turn Around) functionalit

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GS8321Z18/32/36E-xxxV
User-configurable Pipeline Flow Through mode Turn Around) functionality allows zero wait read-write-read utilization Fully pin-compatible with both pipelined flow through NtRAMTM, NoBLand ZBTSRAMs IEEE 1149.1 JTAG-compatible Boundary Scan core power supply supply Linear Interleave Burst mode Pin-compatible with 2Mb, 4Mb, 8Mb, 18Mb devices Byte write operation (9-bit Bytes) chip enable signals easy depth expansion automatic power-down JEDEC-standard 165-bump FP-BGA package RoHS-compliant 165-bump package available
36Mb Pipelined Flow Through Synchronous SRAM
MHz-133
Because synchronous device, address, data inputs, read/ write control inputs captured rising edge input clock. Burst order control (LBO) must tied power rail proper operation. Asynchronous inputs include Sleep mode enable, Output Enable. Output Enable used override synchronous control output drivers turn RAM's output drivers time. Write cycles internally self-timed initiated rising edge clock input. This feature eliminates complex offchip write pulse generation required asynchronous SRAMs simplifies input signal timing. GS8321Z18/32/36E-xxxV configured user operate Pipeline Flow Through mode. Operating pipelined synchronous device, addition rising-edgetriggered registers that capture input signals, device incorporates rising-edge-triggered output register. read cycles, pipelined SRAM output data temporarily stored edge triggered output register during access cycle then released output drivers next rising edge clock. GS8321Z18/32/36E-xxxV implemented with GSI's high performance CMOS technology available JEDECstandard 165-bump FP-BGA package.
Functional Description
GS8321Z18/32/36E-xxxV 36Mbit Synchronous Static SRAM. GSI's SRAMs, like ZBT, NtRAM, NoBL other pipelined read/double late write flow through read/ single late write SRAMs, allow utilization available bandwidth eliminating need insert deselect cycles when device switched from read write cycles.
Parameter Synopsis
tCycle Curr (x18) Curr (x32/x36) Flow tCycle Through Curr (x18) 2-1-1-1 Curr (x32/x36) Pipeline 3-1-1-1 -250 -225 -200 -166 -150 -133 Unit
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GS8321Z18/32/36E-xxxV
Bump BGA-x18 Commom I/O-Top View (Package
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
Bump BGA-15 Body-1.0 Bump Pitch
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GS8321Z18/32/36E-xxxV
Bump BGA-x32 Common I/O-Top View (Package
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
Bump BGA-15 Body-1.0 Bump Pitch
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GS8321Z18/32/36E-xxxV
Bump BGA-x36 Common I/O-Top View (Package
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
Bump BGA-15 Body-1.0 Bump Pitch
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GS8321Z18/32/36E-xxxV
GS8321Z18/32/36E-xxxV 165-Bump Description Symbol
VDDQ
Type
Description
Address field LSBs Address Counter Preset Inputs Address Inputs Data Input Output pins Byte Write Enable DQA, DQB, DQC, I/Os; active Connect Clock Input Signal; active high Clock Enable; active Write Enable; active Chip Enable; active Chip Enable; active Chip Enable; active high Flow Through Pipeline Mode Control Output Enable; active Burst address counter advance enable; active high Sleep mode control; active high Linear Burst Order mode; active Scan Test Mode Select Scan Test Data Scan Test Data Scan Test Clock Must Connect High Core power supply Core Ground Output driver power supply
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GS8321Z18/32/36E-xxxV
GS8321Z18/32/36E-xxxV SRAM Functional Block Diagram
DQa-DQn
Write Data
Register
Write Data
Write Address
Burst Counter
Register
SA1' SA0'
Read, Write
Data Coherency
Control Logic
Write Address
Register
Match
A0-An
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Write Drivers
Memory Array
Register
Sense Amps
GS8321Z18/32/36E-xxxV
Functional Details
Clocking Deassertion Clock Enable (CKE) input blocks Clock input from reaching RAM's internal circuits. used suspend operations. Failure observe Clock Enable set-up hold requirements will result erratic operation. Pipeline Mode Read Write Operations inputs (with exception Output Enable, Linear Burst Order Sleep) synchronized rising clock edges. Single cycle read write operations must initiated with Advance/Load (ADV) held low, order load address. Device activation accomplished asserting three Chip Enable inputs (E1, E3). Deassertion Enable inputs will deactivate device. Function Read Write Byte Write Byte Write Byte Write Byte Write Bytes Write Abort/NOP
Read operation initiated when following conditions satisfied rising edge clock: asserted low, three chip enables (E1, active, write enable input signals deasserted high, asserted low. address presented address inputs latched address register presented memory core control logic. control logic determines that read access progress allows requested data propagate input output register. next rising edge clock read data allowed propagate through output register onto output pins. Write operation occurs when selected, active write input sampled rising edge clock. Byte Write Enable inputs (BA, determine which bytes will written. none activated. write cycle with Byte Write inputs active no-op cycle. pipelined SRAM provides double late write functionality, matching write command versus data pipeline length cycles) read command versus data pipeline length cycles). first rising edge clock, Enable, Write, Byte Write(s), Address registered. Data associated with that address required third rising edge clock. Flow Through Mode Read Write Operations Operation Flow Through mode very similar operations Pipeline mode. Activation read cycle Burst Address Counter identical. Flow Through mode device begin driving data immediately after address clocked into RAM, rather than holding data until following (second) clock edge. Therefore, Flow Through mode read pipeline cycle shorter than Pipeline mode. Write operations initiated same way, differ that write pipeline cycle shorter well, preserving ability turn from reads writes without inserting dead cycles. While pipelined RAMs implement double late write protocol, Flow Through mode single late write protocol mode observed. Therefore, Flow Through mode, address control registered first rising edge clock data required data input pins second rising edge clock.
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GS8321Z18/32/36E-xxxV
Synchronous Truth Table Operation
Read Cycle, Begin Burst Read Cycle, Continue Burst NOP/Read, Begin Burst Dummy Read, Continue Burst Write Cycle, Begin Burst Write Cycle, Continue Burst Write Abort, Continue Burst Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle Deselect Cycle, Continue Sleep Mode Clock Edge Ignore, Stall
Type Address
External Next External Next External Next Next None None None None None None Current
High-Z High-Z
Notes
1,10 1,2,10 1,3,10
High-Z 1,2,3,10 High-Z High-Z High-Z High-Z High-Z High-Z
Notes: Continue Burst cycles, whether read write, same control inputs. Deselect continue cycle only entered into Deselect cycle executed first. Dummy Read Write abort considered NOPs because SRAM performs operation. Write abort occurs when sampled Byte Write pins active write operation performed. wired minimize number control signals provided SRAM. Output drivers will automatically turn during write cycles. High occurs during pipelined read cycle, will remain active (Low High occurs during write cycle, will remain High Don't Care; Logic High; Logic Low; High Byte Write signals high; more Byte/Write signals inputs, except must meet setup hold times rising clock edge. Wait states inserted setting high. This device contains circuitry that ensures outputs High during power-up. 2-bit burst counter incorporated. address counter incriminated Burst continue cycles.
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GS8321Z18/32/36E-xxxV
Pipelined Flow Through Read Write Control State Diagram
Deselect
Read
Write
Burst Read
Burst Write
Input Command Code
Notes:
Hold command (CKE Low) shown because prevents state change.
Transition
Current State Next State (n+1)
represent input command codes indicated Synchronous Truth Table.
Clock (CK)
Command
Current State
Next State
Current State Next State Definition Pipelined Flow Through Read/Write Control State Diagram
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GS8321Z18/32/36E-xxxV
Pipeline Mode Data State Diagram
Intermediate
High (Data
Intermediate Intermediate Intermediate
Data Valid)
Intermediate
High
Intermediate
Input Command Code
Notes:
Hold command (CKE Low) shown because prevents state change.
Transition
Current State
Transition Next State (n+2)
Intermediate State (N+1)
represent input command codes indicated Truth Tables.
Clock (CK)
Command
Current State
Intermediate State
Next State
Current State Next State Definition Pipeline Mode Data State Diagram
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GS8321Z18/32/36E-xxxV
Flow Through Mode Data State Diagram
High (Data
Data Valid)
High
Input Command Code
Notes:
Hold command (CKE Low) shown because prevents state change.
Transition
Current State Next State (n+1)
represent input command codes indicated Truth Tables.
Clock (CK)
Command
Current State
Next State
Current State Next State Definition for: Pipeline Flow through Read Write Control State Diagram
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GS8321Z18/32/36E-xxxV
Burst Cycles Although RAMs designed sustain 100% bandwidth eliminating turnaround cycle when there transition from read write, multiple back-to-back reads writes also performed. SRAMs provide on-chip burst address generator that utilized, desired, further simplify burst read write implementations. control pin, when driven high, commands SRAM advance internal address counter counter generated address read write SRAM. starting address first cycle burst cycle series loaded into SRAM driving low, into Load mode. Burst Order burst address counter wraps around initial state after four addresses (the loaded address three more) have been accessed. burst sequence determined state Linear Burst Order (LBO). When this low, linear burst sequence selected. When installed with tied high, Interleaved burst sequence selected. tables below details.
Mode Functions Mode Name
Burst Order Control Output Register Control Power Down Control
Name
State
Function
Linear Burst Interleaved Burst Flow Through Pipeline Active Standby,
Note: There pull-up device pull-down device pin, this input unconnected chip will operate default states specified above table.
Burst Counter Sequences
Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0]
address address address address
Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0]
address address address address
Note: burst counter wraps initial state clock.
Note: burst counter wraps initial state clock.
1999.05.18
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GS8321Z18/32/36E-xxxV
Sleep Mode During normal operation, must pulled low, either user it's internal pull down resistor. When pulled high, SRAM will enter Power Sleep mode after cycles. this time, internal state SRAM preserved. When returns low, SRAM operates normally after recovery time. Sleep mode current, power-down mode which device deselected current reduced ISB2. duration Sleep mode dictated length time high state. After entering Sleep mode, inputs except become disabled outputs High-Z asynchronous, active high input that causes device enter Sleep mode. When driven high, ISB2 guaranteed after time tZZI met. Because asynchronous input, pending operations operations progress properly completed asserted. Therefore, Sleep mode must initiated until valid pending operations completed. Similarly, when exiting Sleep mode during tZZR, only Deselect Read commands applied while SRAM recovering from Sleep mode.
Sleep Mode Timing Diagram
tZZR tZZS tZZH
Designing Compatibility SRAMs offer users configurable selection between Flow Through mode Pipelinemode signal found vendors offer this option, however most mark VDDQ pipelined parts flow through parts. SRAMs fully compatible with these sockets.
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GS8321Z18/32/36E-xxxV
Absolute Maximum Ratings
(All voltages reference VSS)
Symbol
VDDQ VI/O IOUT TSTG TBIAS
Description
Voltage Pins Voltage VDDQ Pins Voltage Pins Voltage Other Input Pins Input Current Output Current Package Power Dissipation Storage Temperature Temperature Under Bias
Value
-0.5 -0.5 -0.5 VDDQ +0.5 max.) -0.5 +0.5 max.) +/-20 +/-20
Unit
Note: Permanent damage device occur Absolute Maximum Ratings exceeded. Operation should restricted Recommended Operating Conditions. Exposure conditions exceeding Absolute Maximum Ratings, extended period time, affect reliability this component.
Power Supply Voltage Ranges (1.8 V/2.5 Version) Parameter
Supply Voltage Supply Voltage VDDQ Supply Voltage VDDQ Supply Voltage
Symbol
VDD1 VDD2 VDDQ1 VDDQ2
Min.
Typ.
Max.
Unit
Notes
Notes: part numbers Industrial Temperature Range versions character "I". Unless otherwise noted, performance specifications quoted evaluated worst case temperature range marked device. Input Under/overshoot voltage must VDDn+2 exceed maximum, with pulse width exceed tKC.
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GS8321Z18/32/36E-xxxV
VDDQ2 VDDQ1 Range Logic Levels Parameter
Input High Voltage Input Voltage
Symbol
Min.
0.6*VDD -0.3
Typ.
Max.
0.3*VDD
Unit
Notes
Notes: part numbers Industrial Temperature Range versions character "I". Unless otherwise noted, performance specifications quoted evaluated worst case temperature range marked device. Input Under/overshoot voltage must VDDn+2 exceed maximum, with pulse width exceed tKC.
Recommended Operating Temperatures Parameter
Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions)
Symbol
Min.
Typ.
Max.
Unit
Notes
Notes: part numbers Industrial Temperature Range versions character "I". Unless otherwise noted, performance specifications quoted evaluated worst case temperature range marked device. Input Under/overshoot voltage must VDDn+2 exceed maximum, with pulse width exceed tKC.
Undershoot Measurement Timing
Overshoot Measurement Timing
Capacitance
25oC, MHZ,
Parameter
Input Capacitance Input/Output Capacitance Note: These parameters sample tested.
Symbol
CI/O
Test conditions
VOUT
Typ.
Max.
Unit
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GS8321Z18/32/36E-xxxV
Test Conditions Parameter
Input high level Input level Input slew rate Input reference level Output reference level Output load
Conditions
V/ns VDD/2 VDDQ/2 Fig. VDDQ/2
Distributed Test Capacitance
Figure
Output Load 30pF*
Notes: Include scope capacitance. Test conditions specified with output loading shown Fig. unless otherwise noted. Device deselected defined Truth Table.
Electrical Characteristics Parameter
Input Leakage Current (except mode pins) Input Current Output Leakage Current
Symbol
Test Conditions
Output Disable, VOUT
-100
Output Characteristics (1.8 V/2.5 Version) Parameter
Output High Voltage Output High Voltage Output Voltage Output Voltage
Symbol
VOH1 VOH2 VOL1 VOL2
Test Conditions
VDDQ VDDQ 2.375
VDDQ
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Operating Currents
-250 Mode Symbol 70°C 85°C
Rev: 1.05 6/2006 -225 70°C 85°C 85°C 85°C 85°C 85°C 70°C 70°C 70°C 70°C Unit -200 -166 -150 -133 Pipeline (x32/ x36) Flow Through Pipeline (x18) Flow Through IDDQ Pipeline Flow Through Pipeline Flow Through IDDQ IDDQ IDDQ
Parameter
Test Conditions
Operating Current
Device Selected; other inputs Output open
17/32
Standby Current
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Deselect Current
Device Deselected; other inputs
Notes: IDDQ apply combination VDD1, VDD2, VDDQ1, VDDQ2 operation. parameters listed worst case scenario.
GS8321Z18/32/36E-xxxV
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GS8321Z18/32/36E-xxxV
Electrical Characteristics
Parameter Clock Cycle Time Clock Output Valid Pipeline Clock Output Invalid Clock Output Low-Z Setup time Hold time Clock Cycle Time Clock Output Valid Flow Through Clock Output Invalid Clock Output Low-Z Setup time Hold time Clock HIGH Time Clock Time Clock Output High-Z Output Valid output Low-Z output High-Z setup time hold time recovery Symbol tKQX tKQX tLZ1 tHZ1 tOLZ1 tOHZ1 tZZS2 tZZH2 tZZR
-250
-225
-200
-166
-150
-133
Unit
Notes: These parameters sampled 100% tested. asynchronous signal. However, order recognized given clock cycle, must meet specified setup hold times specified above.
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GS8321Z18/32/36E-xxxV
Pipeline Mode Timing (NBT)
Write Read Suspend Read Write writeno-op Read Deselect
Q(B) Q(C) D(D) Q(E) tKQX
D(A)
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GS8321Z18/32/36E-xxxV
Flow Through Mode Timing (NBT)
Write Write Write
Read
Cont
Read
Write
Read
Write
A0-An
D(A) D(B)
D(B+1) Q(C)
tKQX
Q(D)
D(E) Q(F)
tKQX
D(G)
tOLZ tOHZ
*Note: High(False)
JTAG Port Operation
Overview JTAG Port this operates manner that compliant with IEEE Standard 1149.1-1990, serial boundary scan interface standard (commonly referred JTAG). JTAG Port input interface levels scale with VDD. JTAG output drivers powered VDDQ. Disabling JTAG Port possible this device without utilizing JTAG port. port reset power-up will remain inactive unless clocked. TCK, TDI, designed with internal pull-up circuits.To assure normal operation with JTAG Port unused, TCK, TDI, left floating tied either VSS. should left unconnected.
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GS8321Z18/32/36E-xxxV
JTAG Descriptions
Name
Test Clock Test Mode Select
Description
Clocks events. inputs captured rising edge outputs propagate from falling edge TCK. input sampled rising edge TCK. This command input controller state machine. undriven input will produce same result logic input level. input sampled rising edge TCK. This input side serial registers placed between TDO. register placed between determined state Controller state machine instruction that currently loaded Instruction Register (refer Controller State Diagram). undriven will produce same result logic input level.
Test Data
Test Data
Output that active depending state state machine. Output changes response falling edge TCK. This output side serial registers placed between TDO.
Note: This device does have TRST (TAP Reset) pin. TRST optional IEEE 1149.1. Test-Logic-Reset state entered while held high five rising edges TCK. Controller also reset automaticly power-up.
JTAG Port Registers
Overview various JTAG registers, refered Test Access Port orTAP Registers, selected (one time) sequences applied strobed. Each Registers serial shift register that captures serial input data rising edge pushes serial data next falling edge TCK. When register selected, placed between pins. Instruction Register Instruction Register holds instructions that executed controller when moved into Run, Test/Idle, various data register states. Instructions bits long. Instruction Register loaded when placed between pins. Instruction Register automatically preloaded with IDCODE instruction power-up whenever controller placed Test-Logic-Reset state. Bypass Register Bypass Register single register that placed between TDO. allows serial test data passed through RAM's JTAG Port another device scan chain with little delay possible. Boundary Scan Register Boundary Scan Register collection flip flops that preset logic level found RAM's input pins. flip flops then daisy chained together levels found shifted serially JTAG Port's pin. Boundary Scan Register also includes number place holder flip flops (always logic relationship between device pins bits Boundary Scan Register described Scan Order Table following. Boundary Scan Register, under control Controller, loaded with contents RAMs ring when controller Capture-DR state then placed between pins when controller moved Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD EXTEST instructions used activate Boundary Scan Register.
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GS8321Z18/32/36E-xxxV
JTAG Block Diagram
Boundary Scan Register
Bypass Register
Instruction Register Code Register
Control Signals Test Access Port (TAP) Controller
Identification (ID) Register Register 32-bit register that loaded with device vendor specific 32-bit code when controller Capture-DR state with IDCODE command loaded Instruction Register. code loaded from 32-bit on-chip ROM. describes various attributes indicated below. register then placed between pins when controller moved into Shift-DR state. register first reach when shifting begins.
Register Contents
Technology JEDEC Vendor Code Presence Register
Used
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GS8321Z18/32/36E-xxxV
Controller Instruction
Overview There classes instructions defined Standard 1149.1-1990; standard (Public) instructions, device specific (Private) instructions. Some Public instructions mandatory 1149.1 compliance. Optional Public instructions must implemented prescribed ways. this device used monitor input pads, used load address, data control signals into preload buffers. When controller placed Capture-IR state least significant bits instruction register loaded with When controller moved Shift-IR state Instruction Register placed between TDO. this state desired instruction serially loaded through input (while previous contents shifted TDO). instructions, executes newly loaded instructions only when controller moved Update-IR state. instruction this device listed following table.
JTAG Controller State Diagram
Test Logic Reset
Test Idle
Select
Select
Capture
Capture
Shift
Shift
Exit1
Exit1
Pause
Pause
Exit2
Exit2
Update
Update
Instruction Descriptions BYPASS When BYPASS instruction loaded Instruction Register Bypass Register placed between TDO. This occurs when controller moved Shift-DR state. This allows board level scan path shortened facilitate testing other devices scan path.
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GS8321Z18/32/36E-xxxV
SAMPLE/PRELOAD SAMPLE/PRELOAD Standard 1149.1 mandatory public instruction. When SAMPLE PRELOAD instruction loaded Instruction Register, moving controller into Capture-DR state loads data RAMs input buffers into Boundary Scan Register. Boundary Scan Register locations associated with input pin, loaded with default state identified Boundary Scan Chain table this section datasheet. Because clock independent from Clock (TCK) possible attempt capture ring contents while input buffers transition (i.e. metastable state). Although allowing sample metastable inputs will harm device, repeatable results cannot expected. input signals must stabilized long enough meet TAPs input data capture set-up plus hold time (tTS plus tTH). RAMs clock inputs need paused other operation except capturing ring contents into Boundary Scan Register. Moving controller Shift-DR state then places boundary scan register between pins. EXTEST EXTEST IEEE 1149.1 mandatory public instruction. executed whenever instruction register loaded with logic EXTEST command does block override RAM's input pins; therefore, RAM's internal state still determined input pins. Typically, Boundary Scan Register loaded with desired pattern data with SAMPLE/PRELOAD command. Then EXTEST command used output Boundary Scan Register's contents, parallel, RAM's data output drivers falling edge when controller Update-IR state. Alternately, Boundary Scan Register loaded parallel using EXTEST command. When EXTEST instruction selected, sate RAM's input pins, well default values Scan Register locations associated with pin, transferred parallel into Boundary Scan Register rising edge Capture-DR state, RAM's output pins drive value Boundary Scan Register location with which each output associated. IDCODE IDCODE instruction causes loaded into register when controller Capture-DR mode places register between pins Shift-DR mode. IDCODE instruction default instruction loaded power time controller placed Test-Logic-Reset state. SAMPLE-Z SAMPLE-Z instruction loaded instruction register, outputs forced inactive drive state (highZ) Boundary Scan Register connected between when controller moved Shift-DR state. These instructions Reserved Future Use. this device they replicate BYPASS instruction.
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GS8321Z18/32/36E-xxxV
JTAG Instruction Summary Instruction
EXTEST IDCODE SAMPLE-Z SAMPLE/ PRELOAD
Code
Description
Places Boundary Scan Register between TDO. Preloads Register places between TDO. Captures ring contents. Places Boundary Scan Register between TDO. Forces output drivers High-Z. this instruction; Reserved Future Use. Replicates BYPASS instruction. Places Bypass Register between TDO. Captures ring contents. Places Boundary Scan Register between TDO. private instruction. this instruction; Reserved Future Use. Replicates BYPASS instruction. Places Bypass Register between TDO.
Notes
BYPASS Places Bypass Register between TDO. Notes: Instruction codes expressed binary, left, right. Default instruction automatically loaded power-up test-logic-reset state.
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GS8321Z18/32/36E-xxxV
JTAG Port Recommended Operating Conditions Characteristics (1.8/2.5 Version) Parameter
Test Port Input Voltage Test Port Input Voltage Test Port Input High Voltage Test Port Input High Voltage TMS, Input Leakage Current TMS, Input Leakage Current Output Leakage Current Test Port Output High Voltage Test Port Output Voltage Test Port Output CMOS High Test Port Output CMOS
Symbol
VILJ1 VILJ2 VIHJ1 VIHJ2 IINHJ IINLJ IOLJ VOHJ VOLJ VOHJC VOLJC
Min.
-0.3 -0.3 VDD1 VDD2 -300 VDDQ
Max.
VDD1 VDD2 VDD1 +0.3 VDD2 +0.3
Unit Notes
Notes: Input Under/overshoot voltage must VDDn exceed maximum, with pulse width exceed tTKC. VILJ VDDn VILJn Output Disable, VOUT VDDn output driver served VDDQ supply. IOHJ IOLJ IOHJC -100 IOLJC +100
JTAG Port Test Conditions Parameter
Input high level Input level Input slew rate Input reference level Output reference level
Conditions
V/ns VDDQ/2 VDDQ/2
JTAG Port Test Load
VDDQ/2
Distributed Test Capacitance
30pF*
Notes: Include scope capacitance. Test conditions shown unless otherwise noted.
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GS8321Z18/32/36E-xxxV
JTAG Port Timing Diagram
tTKC tTKQ Parallel SRAM input
tTKH
tTKL
JTAG Port Electrical Characteristics
Parameter Cycle Time Valid High Pulse Width Pulse Width Time Hold Time Symbol tTKC tTKQ tTKH tTKL Unit
Boundary Scan (BSDL Files) information regarding Boundary Scan Chain, obtain BSDL files this part, please contact Applications Engineering Department apps@gsitechnology.com.
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GS8321Z18/32/36E-xxxV
Package Dimensions-165-Bump FPBGA (Package
CORNER
VIEW
BOTTOM VIEW (165x)
CORNER
10.0 0.20(4x) 15±0.05
17±0.05
14.0
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0.36~0.46 1.50 MAX.
SEATING PLANE
0.20
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GS8321Z18/32/36E-xxxV
Ordering Information Synchronous Burst RAMs
Part Number1
GS8321Z18E-250V GS8321Z18E-225V GS8321Z18E-200V GS8321Z18E-166V GS8321Z18E-150V GS8321Z18E-133V GS8321Z32E-250V GS8321Z32E-225V GS8321Z32E-200V GS8321Z32E-166V GS8321Z32E-150V GS8321Z32E-133V GS8321Z36E-250V GS8321Z36E-225V GS8321Z36E-200V GS8321Z36E-166V GS8321Z36E-150V GS8321Z36E-133V GS8321Z18E-250IV GS8321Z18E-225IV GS8321Z18E-200IV GS8321Z18E-166IV GS8321Z18E-150IV GS8321Z18E-133IV GS8321Z32E-250IV GS8321Z32E-225IV GS8321Z32E-200IV GS8321Z32E-166IV
Type
Voltage Option
Package
Speed2 (MHz/ns)
250/6.5 225/7 200/7.5 166/8 150/8.5 133/8.5 250/6.5 225/7 200/7.5 166/8 150/8.5 133/8.5 250/6.5 225/7 200/7.5 166/8 150/8.5 133/8.5 250/6.5 225/7 200/7.5 166/8 150/8.5 133/8.5 250/6.5 225/7 200/7.5 166/8
Status4
GS8321Z32E-150IV 150/8.5 Notes: Customers requiring delivery Tape Reel should character part number. Example: GS8321Z18E-150IT. speed column indicates cycle frequency (MHz) device Pipeline mode latency (ns) Flow Through mode. Each device Pipeline/Flow Through mode-selectable user. Commercial Temperature Range. Industrial Temperature Range. offers other versions this type device many different configurations with variety different features, only some which covered this data sheet. Technology site (www.gsitechnology.com) complete listing current offerings.
Rev: 1.05 6/2006
29/32
2003, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
GS8321Z18/32/36E-xxxV
Ordering Information Synchronous Burst RAMs
Part Number1
GS8321Z32E-133IV GS8321Z36E-250IV GS8321Z36E-225IV GS8321Z36E-200IV GS8321Z36E-166IV GS8321Z36E-150IV GS8321Z36E-133IV GS8321Z18GE-250V GS8321Z18GE-225V GS8321Z18GE-200V GS8321Z18GE-166V GS8321Z18GE-150V GS8321Z18GE-133V GS8321Z32GE-250V GS8321Z32GE-225V GS8321Z32GE-200V GS8321Z32GE-166V GS8321Z32GE-150V GS8321Z32GE-133V GS8321Z36GE-250V GS8321Z36GE-225V GS8321Z36GE-200V GS8321Z36GE-166V GS8321Z36GE-150V GS8321Z36GE-133V GS8321Z18GE-250IV GS8321Z18GE-225IV GS8321Z18GE-200IV GS8321Z18GE-166IV GS8321Z18GE-150IV
Type
Voltage Option
Package
RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant
Speed2 (MHz/ns)
133/8.5 250/6.5 225/7 200/7.5 166/8 150/8.5 133/8.5 250/6.5 225/7 200/7.5 166/8 150/8.5 133/8.5 250/6.5 225/7 200/7.5 166/8 150/8.5 133/8.5 250/6.5 225/7 200/7.5 166/8 150/8.5 133/8.5 250/6.5 225/7 200/7.5 166/8 150/8.5
Status4
GS8321Z18GE-133IV RoHS-compliant 133/8.5 Notes: Customers requiring delivery Tape Reel should character part number. Example: GS8321Z18E-150IT. speed column indicates cycle frequency (MHz) device Pipeline mode latency (ns) Flow Through mode. Each device Pipeline/Flow Through mode-selectable user. Commercial Temperature Range. Industrial Temperature Range. offers other versions this type device many different configurations with variety different features, only some which covered this data sheet. Technology site (www.gsitechnology.com) complete listing current offerings.
Rev: 1.05 6/2006
30/32
2003, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
GS8321Z18/32/36E-xxxV
Ordering Information Synchronous Burst RAMs
Part Number1
GS8321Z32GE-250IV GS8321Z32GE-225IV GS8321Z32GE-200IV GS8321Z32GE-166IV GS8321Z32GE-150IV GS8321Z32GE-133IV GS8321Z36GE-250IV GS8321Z36GE-225IV GS8321Z36GE-200IV GS8321Z36GE-166IV GS8321Z36GE-150IV
Type
Voltage Option
Package
RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant
Speed2 (MHz/ns)
250/6.5 225/7 200/7.5 166/8 150/8.5 133/8.5 250/6.5 225/7 200/7.5 166/8 150/8.5
Status4
GS8321Z36GE-133IV RoHS-compliant 133/8.5 Notes: Customers requiring delivery Tape Reel should character part number. Example: GS8321Z18E-150IT. speed column indicates cycle frequency (MHz) device Pipeline mode latency (ns) Flow Through mode. Each device Pipeline/Flow Through mode-selectable user. Commercial Temperature Range. Industrial Temperature Range. offers other versions this type device many different configurations with variety different features, only some which covered this data sheet. Technology site (www.gsitechnology.com) complete listing current offerings.
Rev: 1.05 6/2006
31/32
2003, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
GS8321Z18/32/36E-xxxV
36Mb Sync SRAM Data Sheet Revision History
DS/DateRev. Code: Old; 8321ZVxx_r1 8321ZVxx_r1; 8321ZVxx_r1_01 8321ZVxx_r1_01; 8321ZVxx_r1_02 8321ZVxx_r1_02; 8321ZVxx_r1_03 8321ZVxx_r1_03; 8321ZVxx_r1_04 8321ZVxx_r1_04; 8321Zxx_V_r1_05 Content Types Changes Format Content Page;Revisions;Reason Creation datasheet Updated Characteristics table with numbers Removed address numbers (except Corrected package mechanical drawing thickness Corrected description table page Updated format Updated mechanicals Pb-free information added Updated entire document reflect part nomenclature change
Content Content/Format Content Content
Rev: 1.05 6/2006
32/32
2003, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.

User-configurable Pipeline Flow Through mode Turn Around) functionalit

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