GF9331 Data Sheet Features support 10/8-bit HDTV/SDTV input video

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GF9331 Data Sheet Features support 10/8-bit HDTV/SDTV input video

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GF9331 HDTV/SDTV Motion Co-processor
GF9331 Data Sheet Features
support 10/8-bit HDTV/SDTV input video signals seamless interface Gennum's GF9330 high performance de-interlacer through filter control multi-directional edge detection control support multiplexed non-multiplexed video 3-field vertical motion detection control fully configurable support custom video modes ability extract information from embedded seamless interface popular ADCs NTSC/PAL decoders user configuration through dedicated host interface, supporting parallel serial interfaces tolerant inputs 3.3V supply device 2.5V core logic
Device Overview GF9331 high performance motion co-processor that used conjunction with Gennum's GF9330 HDTV/SDTV 10-bit De-interlacer. Together, GF9331 GF9330 provide 10-bit broadcast quality de-interlacing standard high-definition video signals 1080p60. Although GF9330 fully function stand alone de-interlacer, GF9331 provides added features form filter selection control that enables multi-directional edge adaptive 3-field vertical motion detection. Edge detection interpolation removes edge artifacts that tend occur while de-interlacing shallow horizontal edges while vertical motion detection reduces motion artifacts. Filter selection controls sent GF9330 pixel-by-pixel basis. GF9331 integrates necessary line delays motion edge detectors. GF9331 also provides seamless interfaces off-chip SDRAMs that form required field delays. Ordering Information
Part Number
GF9331-CBP
Applications
HDTV Up/Down Converters Production Equipment Video Walls Projection Systems Plasma Displays Home Theatre Systems Players
Package
Temp. Range
70oC
Edge Detection
Encoder
Control GF9330
Pre-filter
Vertical Motion Detection
Delay
Delayed Video GF9330
External Memory Interface
Block Diagram
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GF9331 Data Sheet
Contents
Features Applications.1 Device Overview Ordering Information Descriptions Electrical Characteristics Tolerant Inputs Tolerance 3.3V Supply Device 2.5V Core Logic Detailed Device Description Input Data Formats Input Synchronization 3.2.1 Support Both 8-bit 10-bit Input Data 3.2.2 Generic Input Format Signalling Seamless Interface GF9330 High Performance De-Interlacer Directional Filter Control Seamless Interface External SDRAMs Host Interface 3.5.1 Host Interface Serial Mode 3.5.2 Host Interface Parallel Mode 3.5.3 Control Register Definitions Closed Captioning RESET Modes Operation 3.8.1 Motion Processing Mode (MODE=1) 3.8.2 Disabled Mode (MODE=0).26 Processing Input Formats 3.10 Vertical Motion Detection 3.10.1 Vertical Motion Feature Control 3.11 Edge Direction Detection 3.11.1 Edge Direction Detection Feature Control 3.12 Video Output 3.13 Processing Latency Package Dimensions Revision History
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GF9331 Data Sheet
Descriptions
RESET
S2_DAT0
S2_DAT2
S2_DAT4
S2_DAT7
S2_DAT10
S2_DAT13
S2_CLK
S2_ADDR2 S2_ADDR7 S2_ADDR10 S2_ADDR13 S2_CS S2_WE Y_OUT9
Y_IN9 S2_DAT1 S2_DAT3 S2_DAT5 S2_DAT8 S2_DAT11 S2_DAT14 S2_ADDR0 S2_ADDR3 S2_ADDR6 S2_ADDR9 S2_ADDR12 S2_CAS S2_RAS Y_OUT8
Y_IN8 Y_IN7 Y_IN6 S2_DAT6 S2_DAT9 S2_DAT12 S2_DAT15 S2_ADDR1 S2_ADDR4 S2_ADDR5 S2_ADDR8 S2_ADDR11 Y_OUT6 Y_OUT7
Y_IN5 Y_IN4 Y_IN3 Y_OUT3 Y_OUT4 Y_OUT5
Y_IN2 Y_IN1 Y_IN0 HOST_EN VDD_INT VDD_IO VDD_IO VDD_INT VDD_IO Y_OUT0 Y_OUT1 Y_OUT2
VCLK_IN MODE VDD_CLKD VDD_INT VDD_IO VDD_IO VDD_INT
SER_MD STD4 STD3 STD2 VSS_CLKD VDD_INT
MEMCLK_IN STD1 STD0
C_IN9 C_IN8 VDD_IO
VIEW GF9331
TGND TGND TGND TGND
VDD_INT
C_OUT9
VDD_IO
C_OUT6
C_OUT7
C_OUT8
C_IN7 C_IN6 C_IN5 C_IN4 TGND TGND TGND TGND C_OUT3 C_OUT4 C_OUT5
C_IN0 C_IN1 C_IN2 C_IN3 VDD_INT TGND TGND TGND TGND C_OUT2 C_OUT1 C_OUT0
ED_MODE VM_MODE TGND TGND TGND TGND VDD_IO FIL_SEL3 FIL_SEL2
FVH_EN F_IN V_IN H_IN VDD_IO FIL_SEL1 FIL_SEL0
VDD_INT H_OUT
DAT_IO4 DAT_IO5 DAT_IO6 DAT_IO7 VDD_INT VDD_IO VDD_IO VDD_INT V_OUT
DAT_IO0 DAT_IO1 DAT_IO2 DAT_IO3 VDD_INT VDD_IO VDD_IO VDD_INT VDD_IO F_OUT
TCLK
S1_ADDR11 S1_ADDR8 S1_ADDR5 S1_ADDR2 S1_ADDR0 S1_DAT15 S1_DAT12 S1_DAT9 S1_DAT6 S1_DAT3
S1_RAS S1_CAS S1_ADDR12 S1_ADDR9 S1_ADDR6 S1_ADDR3 S1_ADDR1 S1_DAT14 S1_DAT11 S1_DAT8 S1_DAT5 S1_DAT2
S1_WE S1_CS S1_ADDR13 S1_ADDR10 S1_ADDR7 S1_ADDR4 S1_CLK S1_DAT13 S1_DAT10 S1_DAT7 S1_DAT4 S1_DAT1 S1_DAT0
GND/TGND: VDD_IO: +3.3V VDD_INT: +2.5V Connection
Figure 1-1: View (328-pin BGA)
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GF9331 Data Sheet
Table 1-1: Descriptions Symbol
RESET VCLK_IN
Grid
Type
Description
Active low, asynchronous RESET. Resets internal logic default conditions. Should applied power Video input clock. When input SDTV input clock will 72MHz. When input format HDTV, input clock will 74.25 74.25/1.001MHz. Memory clock SDRAM operation when VLCK_IN 36MHz. 90MHz input (supplied off-chip crystal oscillator). 8/10-bit input data separate luminance multiplexed luminance colour difference video data. When supplying 8-bit data GF9331, Y_IN[1:0] will 8-bit data supplied Y_IN[9:2]. 8/10-bit input data colour difference video data. When supplying 8-bit data GF9331, C_IN[1:0] will 8-bit data supplied C_IN[9:2]. Video timing control. F_IN identifies EVEN fields incoming video signal. F_IN will Field HIGH Field Video timing control. V_IN represents vertical blanking signal associated with incoming video signal. V_IN HIGH during vertical blanking interval during active video. Video timing control. H_IN represents horizontal blanking signal associated with incoming video signal. H_IN HIGH during horizontal blanking during active video. Control signal input. When HIGH, F_IN, V_IN, H_IN input pins will used video data signalling. When LOW, embedded TRS's will detected video data signalling. Control signal input. When HIGH, vertical motion detection enabled. Control signal input. When HIGH, edge direction detection enabled. Video format definition. Defines video standard when operating without host interface. Table 3-1: Encoding STD[4:0] Selecting Input Data Format. STD[4:0] read into device falling transition HOST_EN after RESET. Operating mode selection. When HIGH, GF9331 motion co-processing enabled. When LOW, GF9331 motion co-processing bypassed. Modes Operation. MODE read into device falling transition HOST_EN after RESET. Host interface enable. When HIGH, GF9331 configured through host interface. When LOW, GF9331 manually configured input pins. These values loaded falling transition HOST_EN. Host interface mode selection. Enables serial mode operation when HIGH. Enables parallel mode operation when LOW. Functions active chip select input host interface parallel mode operation. Functions serial clock input host interface serial mode operation. Host interface bi-directional data parallel mode. serial mode, DAT_IO[7] serves serial data output DAT_IO[0] serves serial data input pin.
MEMCLK_IN Y_IN[9:0]
C_IN[9:0]
F_IN V_IN
H_IN
FVH_EN
VM_MODE ED_MODE STD[4:0]
MODE
HOST_EN
SER_MD
DAT_IO[7:0]
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GF9331 Data Sheet
Table 1-1: Descriptions (Continued) Symbol
Grid
Type
Description
Host interface Read/Write control parallel mode. read cycle defined when HIGH, write cycle defined when LOW. Host interface Address/Data control parallel mode. data contains address when HIGH, data word when LOW. serial mode, this serves chip select (active low). Output data separate luminance multiplexed luminance colour difference video data. Output data colour difference video data. Filter selection control output GF9330. FIL_SEL[3:0] used switch GF9330's internal directional filters pixel pixel basis. Output control signal. H_OUT horizontal blanking output. Output control signal. F_OUT ODD/EVEN field indicator. Output control signal. V_OUT vertical blanking output. SDRAM bank clock. Active SDRAM chip select Field Buffer Active SDRAM address strobe Field Buffer Active SDRAM column address strobe Field Buffer Active SDRAM write enable Field Buffer SDRAM address Field Buffer
Y_OUT[9:0] C_OUT[9:0] FIL_SEL[3:0] H_OUT F_OUT V_OUT S1_CLK S1_CS S1_RAS S1_CAS S1_WE S1_ADDR[13:0]
A20, B20, C20, C19, D20, D19, D18, E20, E19, H20, J20, J19, J18, K20, K19, K18, L18, L19, M19, M20, N19, W10, V11, W11, Y11, V12, W12, Y12, V13, W13, Y13, V14, W14, Y14, V15, W15, Y15, A13, B13, C13, A12, B12, C12, A11, B11, C11, C10, B10, A10,
S1_DAT[15:0]
SDRAM data Field Buffer
S2_CLK S2_CS S2_RAS S2_CAS S2_WE S2_ADDR[13:0]
SDRAM bank clock. Active SDRAM chip select Field Buffer Active SDRAM address strobe Field Buffer Active SDRAM column address strobe Field Buffer Active SDRAM write enable Field Buffer SDRAM address Field Buffer
S2_DAT[15:0]
SDRAM data Field Buffer
JTAG data input; connect used. JTAG mode select; connect used.
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GF9331 Data Sheet
Table 1-1: Descriptions (Continued) Symbol
TCLK VDD_CLKD VSS_CLKD VDD_IO
Grid
E10, E15, F15, J16, M16, T10, E12, F16, G16, P16, R16, E11, E14, E16, F14, G15, H16, J10, J11, J12, K10, K11, K12, K16, L10, L11, L12, L16, M10, M11, M12, N16, P15, T11, T14, T16, U18, U19, U20, A16, A17, A18, A19, B16, B17, B18, B19, C14, C15, C16, C17, C18, D10, D11, D12, D13, D14, D15, D16, D17, E13, E17, F17, F18, F19, F20, G17, G18, G19, G20, H17, H18, H19, J17, K17, L17, M17, M18, N17, N18, P17, P18, P19, R17, R18, R19, T13, T17, T18, T19, U10, U11, U12, U13, U14, U15, U16, U16, U17, V16, V17, V18, V19, V20, W16, W17, W18, W19, W20, Y17, Y18, Y19,
Type
Description
JTAG test clock; connect used. JTAG data output. supply internal clock doubler. Ground connection internal clock doubler. supply.
VDD_INT
supply.
TGND
Device ground Thermal ground (electrically equivalent).
connection.
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GF9331 Data Sheet
Electrical Characteristics
Tolerant Inputs
Input cells used design able withstand 3.3V CMOS input signals, well compatible inputs without degrading performance long-term reliability.
Tolerance
GF9331 protection. testing done accordance with Gennum's standard testing procedure.
3.3V Supply Device 2.5V Core Logic
GF9331 operates from single +3.3V supply device single +2.5V supply core logic.
Table 2-1: Absolute Maximum Ratings Parameter
Device Supply Voltage Device Core Supply Voltage Input Voltage Range (any input) Operating Temperature Range Storage Temperature Range Lead Temperature (soldering seconds) 70oC -40oC 125oC 260oC
Symbol
VDDIO VDDCORE
Value
-0.5 -0.5 -0.5 +4.6V
Table 2-2: Electrical Characteristics VDDIO 3.6V, VDDCORE 2.25 2.75V, 70oC, unless otherwise shown. Parameter
Device Supply Voltage Device Core Supply Voltage Device Supply Current Device Core Supply Current Input Leakage Current VDDIO=3.3V VDDCORE=2.5V IIN=0V IIN=VDD
Conditions
Symbol
VDDIO VDDCORE IDDIO IDDCORE ILEAK
+3.0 +2.25
+3.3 +2.5
+3.6 +2.75
Units
Notes
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GF9331 Data Sheet
Table 2-2: Electrical Characteristics (Continued) VDDIO 3.6V, VDDCORE 2.25 2.75V, 70oC, unless otherwise shown. Parameter
Tristate Leakage Current Input Logic Voltage Input Logic HIGH Voltage Output Logic Voltage Output Logic HIGH Voltage IOL= IOH= -4mA
Conditions
Symbol
ITRILEAK
Units
Notes
Production, test performed room temperature.
Table 2-3: Electrical Characteristics SDRAM Interfaces SDRAM Interface signals include S1_CLK, S1_CS, S1_RAS, S1_CAS, S1_WE, S1_ADDR[13:0] S1_DAT[15:0]. SDRAM Interface signals include S2_CLK, S2_CS, S2_RAS, S2_CAS, S2_WE, S2_ADDR[13:0] S2_DAT[15:0]. VDDIO 3.6V, VDDCORE 2.25 2.75V, 70oC, unless otherwise shown. Parameter
Clock Input Frequency Input Data Setup Time Input Data Hold Time Input Clock Duty Cycle Output Data Delay Time VDDIO=3.6V, CL=15pF load VDDIO=3.6V, CL=15pF load VDDIO=3.6V, CL=15pF load VDDIO=3.6V, CL=15pF load VDDIO=3.6V, CL=15pF load tOD_SD
Conditions
Symbol
FHSCI_SD tSU_SD tIH_SD
Units
Notes
Output Data Hold Time
tOH_SD
Output Enable Time
tOEN_SD
Output Disable Time
tODIS_SD
Output Data Rise/Fall Time
tODRF_SD
a.Based simulation results, verified during device characterization process. b.50% levels. c.Two clock cycles allocated data turnaround. d.20% levels.
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GF9331 Data Sheet
Table 2-4: Electrical Characteristics Host Interfaces Host Interface signals include HOST_EN, SER_MD, DAT_IO[7:0], A_D. VDDIO 3.6V, VDDCORE 2.25 2.75V, 70oC, unless otherwise shown. Parameter
Clock Input Frequency Input Data Setup Time Input Data Hold Time Input Clock Duty Cycle Output Data Delay Time VDDIO=3.6V, CL=15pF load VDDIO=3.6V, CL=15pF load VDDIO=3.6V, CL=15pF load VDDIO=3.6V, CL=15pF load VDDIO=3.6V, CL=15pF load tOD_HI
Conditions
Symbol
FHSCI_HI tSU_HI tIH_HI
10.0
Units
Notes
Output Data Hold Time
tOH_HI
Output Enable Time
tOEN_HI
Output Disable Time
tODIS_HI
Output Data Rise/Fall Time
tODRF_HI
a.Based simulation results, verified during device characterization process. b.50% levels. c.20% levels.
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GF9331 Data Sheet
Detailed Device Description
Input Data Formats
GF9331 supports multiple input data formats with multiplexed separate channels. Data supplied GF9331 through Y_IN[9:0] C_IN[9:0] busses. Table 3-1: Encoding STD[4:0] Selecting Input Data Format outlines data formats that GF9331 supports according setting STD[4:0] pins host interface bits, STD[4:0]. NOTE: progressive video standards GF9331 must manually bypass mode (MODE=0, register). Host Interface host interface details.
Table 3-1: Encoding STD[4:0] Selecting Input Data Format
STD[4:0]
00000
Description
525i (30/1.001) component SMPTE 125M. Multiplexed YCbCr data applied Y_IN. C_IN should LOW. NOTE: Input clock 27MHz.
00001 00010
Reserved 525i (30/1.001) component 16x9 SMPTE 267M. Multiplexed YCbCr data applied Y_IN. C_IN should LOW. NOTE: Input clock 36MHz.
00011 00100
Reserved 625i (25Hz) component tech. 3267E. Multiplexed YCbCr data applied Y_IN. C_IN should LOW. NOTE: Input clock 27MHz.
00101 00110
Reserved 625i (25Hz) component 16x9 ITU-R BT.601-5 Part Multiplexed YCbCr data applied Y_IN. C_IN should LOW. NOTE: Input clock 36MHz.
00111 01000
Reserved 525p (60/1.001Hz) SMPTE 293M. YCbCr data stream applied Y_IN. C_IN should LOW. Timing information extracted from embedded sequences. NOTE: Input clock 54MHz.
01001 01010 01011 01100
Reserved Reserved Reserved 625p (50Hz) ITU-R BT.1358. YCbCr data stream applied Y_IN. C_IN should LOW. Timing information extracted from embedded sequences. NOTE: Input clock 54MHz.
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GF9331 Data Sheet
Table 3-1: Encoding STD[4:0] Selecting Input Data Format (Continued)
STD[4:0]
01101
Description
625p (50Hz) with 18MHz sampling. YCbCr data stream applied Y_IN. C_IN should LOW. Timing information extracted from embedded sequences. NOTE: Input clock 72MHz.
01110
Generic input data format with 4:1:1 sampling. YCbCr data applied both Y_IN C_IN. externally supplied signals used synchronize input data stream. NOTE: Input clock 27MHz.
01111
Generic input data format with 4:2:2 sampling single multiplexed YCbCr input format. YCbCr data applied Y_IN. C_IN should LOW. externally supplied signals used synchronize input data stream. NOTE: Input clock 36MHz.
10000
720p 60/1.001Hz) SMPTE 296M-2001. Data applied Y_IN. data applied C_IN. NOTE: Input clock 74.25MHz 74.25/1.001MHz.
10001
720p 30/1.001Hz) SMPTE 296M-2001. Data applied Y_IN. data applied C_IN. NOTE: Input clock 74.25MHz 74.25/1.001MHz.
10010
1080p 30/1.001Hz) SMPTE 274M. data applied Y_IN. data applied C_IN. NOTE: Input clock 74.25MHz 74.25/1.001MHz.
10011
720p (50Hz) SMPTE 296M-2001. Data applied Y_IN. data applied C_IN. NOTE: Input clock 74.25MHz.
10100
1080p (25Hz) SMPTE 274M. data applied Y_IN. data applied C_IN. NOTE: Input clock 74.25MHz.
10101
720p (25Hz) SMPTE 296M-2001. Data applied Y_IN. data applied C_IN. NOTE: Input clock 74.25MHz.
10110
1080p 24/1.001Hz) SMPTE 274M. data applied Y_IN. data applied C_IN. NOTE: Input clock 74.25MHz 74.25/1.001MHz.
10111
720p 24/1.001Hz) SMPTE 296M-2001. Data applied Y_IN. data applied C_IN. NOTE: Input clock 74.25MHz 74.25/1.001MHz.
11000
1080i 30/1.001Hz) SMPTE 274M. data applied Y_IN. Cb/Cr data applied C_IN. NOTE: Input clock 74.25 74.25/1.001MHz.
11001
1080p 30/1.001Hz Segmented Frame Format) SMPTE RP211-2000. data applied Y_IN. data applied C_IN. NOTE: Input clock 74.25MHz 74.25/1.001MHz.
11010
1080i (25Hz) SMPTE 274. data applied Y_IN. data applied C_IN. NOTE: Input clock 74.25MHz.
11011
1080p (25Hz Segmented Frame Format) SMPTE RP211-2000. data applied Y_IN. data applied C_IN. NOTE: Input clock 74.25MHz.
11100
1080i (25Hz) SMPTE 295M. data applied Y_IN. data applied C_IN. NOTE: Input clock 74.25MHz.
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GF9331 Data Sheet
Table 3-1: Encoding STD[4:0] Selecting Input Data Format (Continued)
STD[4:0]
11101
Description
1080p 24/1.001Hz Segmented Frame Format) SMPTE RP211-2000. data applied Y_IN. data applied C_IN. NOTE: Input clock 74.25MHz 74.25/1.001MHz.
11110
1035i (30Hz) SMPTE 260M. data applied Y_IN. data applied C_IN. NOTE: Input clock 74.25MHz.
11111
Generic input data format with 4:2:2 sampling separate format. Data applied Y_IN. data applied C_IN. externally supplied F_IN, V_IN H_IN signals used synchronize input data stream. NOTE: Input clock 74.25MHz 74.25/1.00MHz.
Input Synchronization
GF9331 obtains relevant timing information from either embedded information externally supplied H_IN, V_IN sand F_IN signals. When FVH_EN HIGH using either host interface external pin, GF9331 relies externally supplied H_IN, V_IN F_IN signals timing information. When FVH_EN LOW, GF9331 extracts embedded timing information from video data stream ignores timing information present F_IN, V_IN H_IN pins.
3.2.1 Support Both 8-bit 10-bit Input Data
GF9331 supports 8-bit 10-bit input data. When operating with 8-bit input data, LSBs GF9331's 10-bit input should input data applied MSBs input bus.
3.2.2 Generic Input Format Signalling
GF9331 supports generic input data formats with either 4:1:1 4:2:2 sampling structures that require 2046 active samples line have maximum total line width 4096 (active blanking) samples. addition, there limit 2048 lines interlaced frame. following host interface parameters programmable describe generic input data format relative F_IN, V_IN H_IN signals. Figure 3-1: Generic Input Format Definition.
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GF9331 Data Sheet
OUTPUT H_BLANK_SIZE EVEN FIELD V_BLANK_SIZE_EVEN FIELD
FIELD
F_OFFSET_ODD V_OFFSET_ODD FIELD V_BLANK_SIZE_ODD EVEN FIELD
EVEN FIELD
F_OFFSET_EVEN V_OFFSET_EVEN EVEN FIELD FIELD
Figure 3-1: Generic Input Format Definition
3.2.2.1 H_BLANK_SIZE This parameter defines number samples that comprise horizontal blanking region. This parameter maximum value 4095 less than total line width (active blanking) sample size. Twelve bits within host interface dedicated this parameter. GF9331 stores processes active video samples only (i.e. H_IN =0). 3.2.2.2 V_BLANK_SIZE_ODD This parameter defines number lines that comprise vertical blanking interval that follows field. This parameter maximum value 255. Eight bits within host interface dedicated this parameter. GF9331 stores processes active video samples only (i.e. V_IN =0). Figure 3-1: Generic Input Format Definition. 3.2.2.3 V_BLANK_SIZE_EVEN This parameter defines number lines that comprise vertical blanking interval that follows even field. This parameter maximum value 255. Eight bits within host interface dedicated this parameter. GF9331 stores processes active video samples only (i.e. V_IN =0). Figure 3-1: Generic Input Format Definition.
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GF9331 Data Sheet 3.2.2.4 V_OFFSET_ODD This parameter defines number lines from V_IN transition active video field region. This parameter maximum value 255. Eight bits within host interface dedicated this parameter. This parameter been added accommodate video decoders which output non-standard timing signal. Figure 3-2: V_Offset Definition.
Last active line H_IN Vertical Blanking Region
V_IN
V_OFFSET_ODD/EVEN
Figure 3-2: V_Offset Definition
3.2.2.5 V_OFFSET_EVEN This parameter defines number lines from V_IN transition even active video field region. This parameter maximum value 255. Eight bits within host interface dedicated this parameter. This parameter been added accommodate video decoders which output non-standard timing V_IN signal. Figure 3-2: V_Offset Definition. 3.2.2.6 F_OFFSET_ODD This parameter defines number lines from F_IN transition vertical blanking interval following field. This parameter maximum value 255. Eight bits within host interface dedicated this parameter. This parameter been added accommodate video decoders which output non-standard timing F_IN signal. Figure 3-1: Generic Input Format Definition. 3.2.2.7 F_OFFSET_EVEN This parameter defines number lines from F_IN transition vertical blanking interval following even field. This parameter maximum value 255. Eight bits within host interface dedicated this parameter. This parameter been added accommodate video decoders which output non-standard timing F_IN signal. Figure 3-1: Generic Input Format Definition. 3.2.2.8 H_POLARITY This parameter defines polarity H_IN pin. With H_POLARITY LOW, falling transition H_IN indicates active video. With H_POLARITY HIGH, rising transition H_IN indicates active video. within host interface dedicated this parameter.
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GF9331 Data Sheet 3.2.2.9 F_POLARITY This parameter defines polarity F_IN pin. Refer Table 3-2: F_POLARITY F_POLARITY encoding. within host interface dedicated this parameter.
Table 3-2: F_POLARITY F_POLARITY Register
F_IN
F_IN Function
Even Field Field Field Even Field
3.2.2.10 V_POLARITY This parameter defines polarity V_IN pin. With V_POLARITY LOW, falling transition V_IN indicates active video. With V_POLARITY HIGH, rising transition V_IN indicates active video. within host interface dedicated this parameter.
Seamless Interface GF9330 High Performance De-Interlacer Directional Filter Control
GF9330 operate stand-alone de-interlacer operate conjunction with GF9331 Motion Co-processor. GF9331 contains adaptive multi-directional edge detectors, well vertical motion detector. Edge sensitive control signals directly GF9330. These control signals adaptively switch GF9330's internal de-interlacing filters pixel pixel basis. These control signals GF9330 GF9331 over FIL_SEL[3:0] control bus. NOTE: Y_OUT[9:0] pins GF9331 must connected Y_IN[9:0] pins GF9330. C_OUT[9:0] pins GF9331 must connected C_IN[9:0] pins GF9330. F_OUT, V_OUT H_OUT pins GF9331 must connected F_IN, V_IN H_IN pins GF9330. FIL_SEL[3:0] output GF9331 must connected FIL_SEL[3:0] input GF9330. Refer Figure 3-3: Using GF9331 with GF9330 Motion Adaptive De-interalcing with edge vertical motion detection pictorial description connections between GF9330 GF9331.
Y_IN[9:0] Y_OUT[9:0] Y_IN[9:0] C_IN[9:0] FIL_SEL[3:0] Y1_OUT[11:0] C1_OUT[11:0]
C_IN[9:0]
GF9331
C_OUT[9:0] FIL_SEL[3:0]
GF9330
Y2_OUT[11:0] C2_OUT[11:0]
Figure 3-3: Using GF9331 with GF9330 Motion Adaptive De-interalcing with edge vertical motion detection
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GF9331 Data Sheet
Seamless Interface External SDRAMs
GF9331 requires independent external field buffers, each implemented with 1Mx16-bit (min) SDRAM configuration. This configuration supports operational modes.
Table 3-3: SDRAM Configuration Format Bypass Configuration Banka Total ADDR BANKb SDRAM properties (per bank) Min. Freq. (MHz)
Recomended
Min. Access Time (ns)
Latency
1(1Mx16) 1(1Mx16) 1(1Mx16) 1(1Mx16)
Micron: MT48LC4M16A2, MT48LC8M16A2
a.There b.This assuming 8-column structure.
Host Interface
GF9331 provides both serial parallel host interface control ports configuration internal parameters. GF9331 also able operate stand-alone mode, with host interface control. stand-alone mode, video standard STD[4:0] mode operation MODE (pins registers, depending HOST_EN state). These values loaded into device falling transition HOST_EN after setting RESET LOW. Both serial parallel interfaces share common pins described Table 3-4: Host Interface Common Pins.
Table 3-4: Host Interface Common Pins GF9331 Name
DAT_IO[0] DAT_IO[1] DAT_IO[2] DAT_IO[3] DAT_IO[4] DAT_IO[5] DAT_IO[6]
Parallel Mode
CHIP select Data/address (bit Data/address (bit Data/address (bit Data/address (bit Data/address (bit Data/address (bit Data/address (bit
Serial Mode
SCLK Serial Clock Serial data (not used) (not used) (not used) (not used) (not used) (not used)
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GF9331 Data Sheet
Table 3-4: Host Interface Common Pins (Continued) GF9331 Name
DAT_IO[7] HOST_EN SER_MD
Parallel Mode
Data/address (bit Address/data select Read/write select Host Interface enable Parallel mode enable
Serial Mode
Serial data Serial chip select (not used) Host Interface enable HIGH Serial mode enable
3.5.1 Host Interface Serial Mode
Gennum Serial Peripheral Interface (GSPI) wire interface comprised serial data (SDI), serial data (SDO), active serial chip select (SCS), clock (SCLK). interface operates master/slave configuration, where master provides SCLK, SDI, signals slave slaves. master uC_SDO drives slave(s) input. tristate output that allows multiple devices drive master uC_SDI. Serial mode operation supports both continuous burst clock configurations. interface illustrated Figure 3-4: Host Interface Serial Mode.
MASTER (uC)
uC_SCLK uC_SDO uC_SDI uC_SCS
SLAVE (GF9331)
SCLK (CS) (DAT_IO0) (DAT_IO7) (A_D)
Figure 3-4: Host Interface Serial Mode
3.5.1.1 Serial Command Word Description command word consists 16-bit word transmitted first contains read/write bit, Auto-Configure control bit, nine reserved bits 5-bit address shown Figure 3-5: Serial Command Word Representation.
Figure 3-5: Serial Command Word Representation
indicates Read command `1', write command when `1'.
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GF9331 Data Sheet 3.5.1.2 Auto-Configure auto-configure feature will executed when Auto-Configure control (used during write operations only). Auto-Configure registers will updated their appropriate settings based current video standard operational mode. When setting Auto-Configure bit, command word should with only register `1'. remaining register bits should `0'. complete Auto-Configuration more data bits must loaded into device. state these bits either HIGH LOW. Before Auto-Configuring device, standard mode must using either host interface (HOST_EN HIGH) external pins (with falling transition HOST_EN). This simplifies configuration while allowing customization many features format parameters. 3.5.1.3 Serial Data Word Description serial data word consists 16-bit word shown Figure 3-6: Serial Data Word Representation. Serial data transmitted received first.
Figure 3-6: Serial Data Word Representation
Both command data words clocked into GF9331 rising edge serial clock (SCLK), which operate either continuous burst fashion. first (MSB) serial output (SDO) available following last falling SCLK edge "read" command word. remaining bits clocked falling edges SCLK.
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GF9331 Data Sheet 3.5.1.4 Serial Write Operation write cycles consist command word followed data word, both transmitted GF9331 SDI. first 16-bit word transmitted following falling transition command word. Several write cycles performed while LOW. Figure 3-7: Write Cycle.
tSU_HI SCLK
tIH_HI tSU_HI
Figure 3-7: Write Cycle
3.5.1.5 Serial Read Operation read cycles consist command word transmitted GF9331 followed data word transmitted from GF9331 SDO. first 16-bit word transmitted following falling transition command word. Several read cycles performed while LOW. Figure 3-8: Read Cycle.
OEN_HI SCLK
OD_HI ODIS_HI
Figure 3-8: Read Cycle
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GF9331 Data Sheet
3.5.2 Host Interface Parallel Mode
Gennum Parallel Peripheral Interface (GPPI) consists 8-bit multiplexed address/data (DATA_IO[7:0]), chip select (CS), read/write (R_W), address/data (A_D) shown Figure 3-9: Host Interface Parallel Mode.
MASTER (uC) SLAVE (GF9331)
uC_CS
uC_ADDR/DATA
ADDR/DATA (DAT_IO[7:0])
uC_R/W
uC_A/D
Figure 3-9: Host Interface Parallel Mode
Data strobed in/out parallel interface falling edge GF9331 drives DAT_IO[7:0] when HIGH LOW, otherwise this port high impedance state. 3.5.2.1 Parallel Address Word Description 8-bit address word loads address accessed allows Auto-Configure set. Auto-Configure bit, followed reserved bits 5-bit address shown Figure 3-10: Parallel Address Word Representation.
Figure 3-10: Parallel Address Word Representation
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GF9331 Data Sheet 3.5.2.2 Parallel Write Operation write cycle parallel interface shown Figure 3-11: Write Cycle Parallel Interface. First 8-bit address word provided DAT_IO port setting HIGH. address word contains auto-update flag, which allows automatic configuration predefined registers (used during write operations only).
tOEN_HI
DAT_IO(7.0)
ADDRESS
(UB) DATA_IN
(LB) DATA_IN
ADDRESS
(UB) DATA_OUT
(LB) DATA_OUT
tSU_HI
tIH_HI
tODIS_HI
Figure 3-11: Write Cycle Parallel Interface
LSB's address word contain address location read write operation. remaining address word bits DAT_IO[6:5] reserved. address word registered falling edge Following this, driven data words sent upper byte (UB) word first each clocked falling edge 8-bit data words must follow each address word occupy each 16-bit parameter which defined Figure 3-12: Host Interface Register Allocation. 3.5.2.3 Parallel Read Operation read cycle begins with address write setting HIGH. address clocked falling edge Following address, must driven HIGH driven allow upper byte data clocked first falling edge followed lower byte second falling edge
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GF9331 Data Sheet
CLK_X1_SEL
START_OPERATION EXT_MEMCLK_SEL
Address
FIELD2_HAS_TOP_LINE PROGRESSIVE_INPUT
CMD_RESET
Address Address Address Address Address Address
EVEN_LINES_PER_FRAME[1:0]
NO_LINE_DELAYS(9:0) H_BLANK_SIZE(11:0)
FORMAT_SD
ID_MODE(1:0) V_BLANK_SIZE_ODD(7:0)
Address Address Address Address Address Address Address Address Address Address Address Address Address Address Address Address
V_BLANK_SIZE_EVEN(7:0)
CC_BLANK_START_LINE(7:0)
CC_BLANK_END_LINE(7:0)
V_OFFSET_ODD(7:0) F_OFFSET_ODD(7:0)
H_POLARITY V_POLARITY F_POLARITY FVH_EN_BIT
CC_BLANK_EN
V_OFFESET_EVEN(7:0) F_OFFESET_EVEN(7:0) EDGE_CTL MODE STD(4:0) VM_CTL
Address Address Address Address Address Address Address Address Address
Figure 3-12: Host Interface Register Allocation
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GF9331 Data Sheet
3.5.3 Control Register Definitions
host interface internal registers divided into classes: User Configurable (UC) Auto-Configurable (AC). Address locations through contain parameters which configured user. Locations through automatically configured based STD[4:0] MODE registers, user configured desired.
Table 3-5: Control Register Definitions Address
Location
Register Name
STD[4:0] MODE VM_CTL EDGE_CTL CC_BLANK_EN
Class
Description
Defines video standard described Input Data Formats. Enables (MODE=1) bypasses (MODE=0) GF9331 processing. Enables (VM_CTL=1) bypass (VM_CTL=0) vertical motion detection. Enables (EDGE_CTL=1) bypasses (EDGE_CTL=0) edge detection. Enables (CC_BLANK_EN=1) bypasses (CC_BLANK_EN=0) blanking close captioned video region. Enables GF9331 external F_IN, V_IN, H_IN controls (FVH_EN=1) place embedded (FVH_EN=0). When '1', F_IN follows normal convention where F_IN field (odd) field (even). Defines polarity V_IN pin. When '1', V_IN follows normal convention where V_IN HIGH vertical blanking region. Defines polarity H_IN pin. When '1', H_IN follows normal convention where H_IN HIGH horizontal blanking region. Defines number lines from F_IN transition vertical blanking interval following even field. This parameter maximum value 255. Defines number lines from F_IN transition vertical blanking interval following field. This parameter maximum value 255. Defines number lines from V_IN transition even active video field region. This parameter maximum value 255. Defines number lines from V_IN transition active video field region. This parameter maximum value 255.
Default
00000
FVH_EN
F_POLARITY V_POLARITY
H_POLARITY
F_OFFSET_EVEN[7:0]
00000000
15:8
F_OFFSET_ODD[7:0]
00000000
V_OFFSET_EVEN[7:0]
00000000
15:8
V_OFFSET_ODD[7:0]
00000000
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GF9331 Data Sheet
Table 3-5: Control Register Definitions (Continued) Address
Location
Register Name
CC_BLANK_END_ LINE [7:0]
Class
Description
Defines last line number which closed captioned blanking ends. this parameter, line defined first active line field/frame. Defines first line number which closed captioned blanking starts. this parameter, line defined first active line field/frame. Defines number lines that comprise vertical blanking interval that follows even input field. This parameter maximum value 255. Defines number lines that comprise vertical blanking interval that follows input field. This parameter maximum value 255. Used configure GF9331 SDRAM controller into 8-bit mode video formats. This auto-configured based standard mode selection. Configures GF9331 accept progressive video format. This auto-configured based standard mode selection. Defines type video sequence input video de-multiplexing. When "00" input represents 4:2:2 sequence, "01" represents 4:1:1 sequence, "10" represents format. This word auto-configured based video standard mode. Defines number horizontal blanked input words line that corresponds times number blanking pixels line 4:2:2 modes equal number pixels line formats (maximum 4095). This value auto-configured. HIGH when field line first line video frame (SMPTE 260M). video standards that have even number lines frame such SMPTE 295M, otherwise Defines number line delays implement within external field delay. This value auto-configured based standard mode. calculation NO_LINE_DELAYS (Number lines frame 3)/2
Default
00000000
15:8
CC_BLANK_START_ LINE [7:0]
V_BLANK_SIZE_EVEN [7:0]
00000000
Auto
15:8
V_BLANK_SIZE_ ODD[7:0]
Auto
FORMAT_SD
Auto
PROGRESSIVE_INPUT
Auto
15:14
ID_MODE[1:0]
Auto
11:0
H_BLANK_SIZE[11:0]
Auto
FIELD2_HAS_TOP_ LINE
Auto
15:14
EVEN_LINES_PER_ FRAME[1:0]
NO_LINE_DELAYS[9:0]
Auto Auto
EXT_MEMCLK_SEL
Controls selection SDRAM clock source. VCLK_IN frequencies less than 36MHz, internal clock doubler used. other modes external source required (MEMCLK_IN). This parameter normally modes other cases.
Auto
CLK_X1_SEL
Auto
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GF9331 Data Sheet
Table 3-5: Control Register Definitions (Continued) Address
Location
Register Name
CMD_RESET
Class
Description
This parameter forces GF9331 enter reset state. reset remains effect until this parameter cleared with subsequent command. using external F_IN, V_IN H_IN signals, this parameter must following completion programming F_IN, V_IN H_IN offsets.
Default
START_OPERATION
Closed Captioning
GF9331 provides blanking function selected input video lines. Consecutive lines within each input field blanked, when this function enabled, beginning with CC_BLANK_START_LINE register ending with CC_BLANK_END_LINE register. blanking applied prior processing video data. blanking function enabled with CC_BLANK_EN bit. BLANK_START_LINE BLANK_END_LINE each allocated 8-bits within host interface.
RESET
RESET active which will reset internal logic it's default conditions when LOW. power recommended reset device ensure internal registers their default state. When applying reset, GF9331 will load STD[4:0] MODE[2:0] settings from external pins. further configuration done, these settings will used operation device.
Modes Operation
device supports enabled disabled modes operation. basic operating mode GF9331 selected using MODE MODE register within host interface. Table 3-6: Modes Operation.
Table 3-6: Modes Operation Mode
Disabled Motion processing input video signal
Description
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GF9331 Data Sheet
3.8.1 Motion Processing Mode (MODE=1)
When operate motion co-processor GF9331 performs edge vertical motion detection provides optimal control GF9330 filters through FIL_SEL[3:0] pixel pixel basis.
3.8.2 Disabled Mode (MODE=0)
GF9331 also disabled mode operation. disabled mode, motion co-processing operations performed FIL_SEL[3:0] output "0000". this mode, input video still routed Y_OUT C_OUT pins GF9330 (NOTE: Only active portion input video signal passed through device GF9330, other data will lost from input data stream). Table 3-6: Modes Operation. video channel maintained bypass mode, however, processing takes place. Therefore, field buffers still chip must known programmed state.
Processing Input Formats
GF9331 provides motion processing formats identified Table 3-7: Processing Input Formats.
Table 3-7: Processing Input Formats STD[4:0] Input Format Motion Processing Mode
Supported Supported Supported Supported
Disabled Mode
Supported Supported Supported Supported Supported Supported Supported
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101
525i (30/1.001) SMPTE 125M Reserved 525i (30/1.001) SMPTE 267M 16x9 Reserved 625i (25) Tech. 3267 Reserved 625i (25) ITU-R BT.601 Part Reserved 525p (60/1.001) SMPTE 293M Reserved Reserved Reserved 625p (50) ITU-R BT-1358 625p (50) 16x9
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GF9331 Data Sheet
Table 3-7: Processing Input Formats (Continued) STD[4:0] Input Format Motion Processing Mode
Supported Supported Supported Supported Supported Supported Supported
Disabled Mode
Supported Supported Supported Supported Supported Supported Supported Supported Supported Supported Supported Supported Supported Supported Supported Supported Supported Supported
01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
Generic 4:1:1 Generic 4:2:2 720p 60/1.001) SMPTE 296M-2001 (System 720p 30/1.001) SMPTE 296M-2001 (System 1080p 30/1.001) SMPTE 274M (System 720p (50) SMPTE 296M-2001 (System 1080p (25) SMPTE 274M (System 720p (25) SMPTE 296M-2001 (System 1080p 24/1.001) SMPTE 274M (System #11) 720p 24/1.001) SMPTE 296M-2001 (System 1080i 30/1.001) SMPTE 274M (System 1080PsF 30/1.001) SMPTE RP211-2000 (System #13) 1080i (25) SMPTE 274M (System 1080PsF (25) SMPTE RP211-2000 (System #14) 1080i (25) SMPTE 295M (System 1080PsF 24/1.001) SMPTE RP211-2000 (System #16) 1035i 30/1.001) SMPTE 260M Generic 4:2:2
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GF9331 Data Sheet
3.10 Vertical Motion Detection
GF9331 detects objects moving vertical direction (e.g. rolling credits). performing motion detection, special vertical filter enabled within GF9331 interpolating pixels with vertical motion, thereby reducing slow motion de-interlacing artifacts. This vertical motion detection signal provided GF9330 through control (FIL_SEL[3:0]).
3.10.1 Vertical Motion Feature Control
GF9331 able operate automatic disabled mode vertical motion detection video input stream. When operate disabled mode (VM_MODE=0 VM_CTL=0), internal vertical motion detection circuitry disabled. When operate automatic mode (VM_MODE=1 VM_CTL=1) GF9331 internally detects vertical motion. Table 3-8: Vertical Motion Control.
Table 3-8: Vertical Motion Control External VM_MODE
Host Interface VM_CTL
Description
Vertical Motion Detection Disabled Vertical Motion Detection Enabled
3.11 Edge Direction Detection
order reduce edge artifacts caused de-interlacing process, pixel gradients analysed calculated along different edge directions. analysis based several complex techniques including vertical-temporal filtering, gradient morphological operations. Edge interpolation filters GF9330 enabled based edge information provided GF9331 through FIL_SEL[3:0] control bus.
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GF9331 Data Sheet
3.11.1 Edge Direction Detection Feature Control
GF9331 able operate automatic disabled mode edge detection video input stream. When operate disabled mode (ED_MODE=0 EDGE_CTL=0), internal edge direction detection circuitry disabled. When operate automatic mode (ED_MODE=1 EDGE_CTL=1) GF9331 internally detects edge directions. Table 3-9: Edge Detection Feature Control.
Table 3-9: Edge Detection Feature Control External ED_MODE
Host Interface EDGE_CTL
Description
Edge Direction Detection Disabled Edge Direction Detection Enabled
3.12 Video Output
GF9331 supports input formats defined Input Data Formats. Routing video data GF9330 done Y_OUT[9:0] C_OUT[9:0] busses. Note that only active portion input video signal passed through device GF9330 unchanged. other ancillary data discarded from input data stream. Timing information provided H_OUT, V_OUT F_OUT pins.
3.13 Processing Latency
GF9331 processing latency constant lines pixels modes operation (including bypass).
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GF9331 Data Sheet
Package Dimensions
1213 151617
1.00 (3X) REF.
0.75 0.15 (X328)
24.00 REF.
27.00 0.20
4.00, (4X) 24.00 REF. 24.13 27.00 0.20
24.13
1.27
1.27
1.17 REF.
0.56 REF.
Figure 4-1: Package dimensions
0.60 0.10
2.33 0.13
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GF9331 Data Sheet
Revision History
Version
133232
Date
June 2004
Changes Modifications
Corrections text bypass mode memories used. Changed document format.
October 2002
Adding tri-state leakage current; correcting spelling errors; adding 8-bit serial command word diagram.
CAUTION
ELECTROSTATIC SENSITIVE DEVICES
OPEN PACKAGES HANDLE EXCEPT STATIC-FREE WORKSTATION
DOCUMENT IDENTIFICATION
DATA SHEET product development phase specifications subject change without notice. Gennum reserves right remove product time. Listing product does constitute offer sale.
GENNUM CORPORATION Mailing Address: P.O. 489, Stn. Burlington, Ontario, Canada Tel. (905) 632-2996 Fax. (905) 632-5946 Shipping Address: Fraser Drive, Burlington, Ontario, Canada GENNUM JAPAN CORPORATION Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku, Tokyo, 160-0023 Japan Tel. (03) 3349-5501, Fax. (03) 3349-5505 GENNUM LIMITED Long Garden Walk, Farnham, Surrey, England TEL. (0)1252 (0)1252 Gennum Corporation assumes responsibility circuits described herein makes representations that they free from patent infringement. Copyright June 2001 Gennum Corporation. rights reserved. Printed Canada www.gennum.com Proprietary Confidential 18303 June 2004

GF9331 Data Sheet Features support 10/8-bit HDTV/SDTV input video

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